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Study of performance degradations in DC-DC converter due to hot carrier stress by simulation
Microelectronics Reliability 46 (2006) 1840–1843
.
www.elsevier.com/locate/microrel
Study of performance degradations in DC-DC converter due to hot carrier stress by simulation .
C. Yu, L. Jiang, and J. S. Yuan .
Chip Design and Reliability Laboratory, University of Central Florida, Orlando FL 32816, USA Tel: (407) 823-5719, Fax: (407) 823-5835, email:[email protected], [email protected] .
Abstract The hot carrier effects on the 0.25 μm high voltage LDMOS has been examined by the accelerated stress experiment. Although the model parameters changed slightly, the switching performances degraded significantly, which have been simulated with the compact models extracted from the test devices by ICCAP. A full bridge DC-DC converter with the compact models was proposed in Cadence SpectreRF. The simulated results show that the efficiency of the full bridge DC-DC converter degraded significantly due to the hot carrier effects. .
1. Introduction A power MOSFET is a high-voltage transistor that conducts large amounts of current when turned on. Although a LDMOS is usually designed to reduce the hot carrier (HC) effect by increasing the drain region, the power MOSFETs are used at high voltages and currents [1] – [3]. Under these conditions, hot carrier effects cannot be avoided and cause shifts in device parameters, such as threshold voltage, gain and on-resistance [4]. The evaluation of hot carrier induced degradation becomes very important for developing reliable circuits. The parameter shifts in the power MOSFETs due to HC effects can degrade the performances of their applications, such as the DC-DC converters. Until now, little attention has been paid to the HC effects on the power MOSFETs. The switching performances of the power MOSFETs are sensitive to the device parameters. Little changes in the device parameters can lead to significant performance degradation in the device switching performances, thus the DC-DC converters.
0026-2714/$ - see front matter Ó 2006 Published by Elsevier Ltd. doi:10.1016/j.microrel.2006.07.079
In this paper, the parameter shifts in our 0.25 μ m high voltage LDMOS has been examined experimentally [4]. The results and discussions have been presented. The performance degradations in a full bridge DC-DC converter were evaluation by simulation with the compact models extracted from the test devices. 2. Experimental Results and Discussions The test device is 0.25 × 10 μm2 high voltage LDMOS. It was built on a highly doped p-type substrate to provide isolation to the n-channel device. A lightly doped p-type epi-layer was added to accommodate high voltage capability. The selfaligned channel below the metallized poly-silicon gate was used to improve the device transconductance and gain. The lightly doped drain extension region was introduced to sustain the high drain-source voltage in combination with the epilayer. More device details were given in [4]. The Agilent 4156B Precision Semiconductor Parameter Analyzer was used for stress and I-V characteristic measurement. Agilent 4284A LRC
C. Yu et al. / Microelectronics Reliability 46 (2006) 1840–1843
meter was used to get the capacitances. During the test, the source and substrate were grounded. The stress voltage was applied on the drain and gate. The drain and gate voltage were set at 11.5 V and 3 V for HC stress, respectively. The threshold voltage (Vth), peak transconductance (gm,max), onresistance (Ron), gate-source capacitance (Cgs), and gate-drain capacitance (Cgd) are reported [4] and summarized in Table 1. They changed slightly due to the HC stress. The increases in Vth come from the changes in interface states during HC stress. The changes in Vth lead to the shifts in peak transconductances. Ron is composed of several components including source diffusion resistance, channel resistance, drift region resistance. It is a function of the Vth, transconductance, and drain current. The shifts in these parameters result in the changes of Ron [4]. 3. Degradation in Switching Performance To investigate the stress effects on the switching performance, the circuit as shown in Fig. 1 has been proposed in Cadence. The oscillograms of the gate-to-source voltage neatly delineate between the charge required for the gate-to-source capacitance, and the charge required for the gate-to-drain, or “Miller” capacitance [5]. The switching performances of transistors are determined by the parasitic capacitances, which shifted after stress. The shifts in switching performance were carried out by applying the compact model extracted from the test device before and after stress using ICCAP. It is shown in Fig. 2. Initially, the switch is closed. The gate voltage and drain current are zero. The switch is opened at about 5 us; the gate-tosource capacitance starts to charge, and the gate-tosource voltage increases. Because the shifts in gate-to-source capacitance due to stress, the VGS curve changed after stress in this period. No current flows in the drain until the gate reaches the threshold voltage. At next period, the gate-tosource capacitance continues to charge, the gate voltage continues to rise and the drain current rises proportionally. The threshold voltage changed after stress. Therefore, the start rising point for the drain current shifts. So long as the actual drain current is still building up towards the available drain current, ID, the freewheeling rectifier stays in conduction, the voltage across it remains low, and the voltage across the switch continues to be virtually the full circuit voltage, VDD. The top end of the drain-togate capacitance therefore remains at a fixed
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potential. When the drain current reaches ID, and the freewheeling rectifier shuts off; the potential of the drain now is no longer tied to the supply voltage. The drain current now stays constant at the value ID enforced by the current sourcetarts to fall. Since the gate voltage is inextricably related to the drain current by the intrinsic transfer characteristic of the device, the gate voltage now stays constant because the “enforced” drain current is constant. For the time being therefore, no further charge is consumed by the gate-to-source capacitance, because the gate voltage remains constant. Thus the drive current now diverts, in its entirety, into the capacitance Cgd, and the drive circuit charge now contributes exclusively to discharging the Cgd capacitance [5]. Due to the shifts in Cgd after stress, the VGS, VDS, and drain current curves shift due to the stress this. The drain voltage excursion during the next period is relatively large, and hence the total drive charge is typically higher for the Cgd than for the Cgs. When the drain voltage falls to a value equal to ID × RON, and the switch device now comes out of the “active” region of operation. The gate voltage is now no longer constrained by the transfer characteristic of the device to relate to the drain current, and is free to increase. From Sec. 2, one gets that RON degraded after stress. Therefore, the second start rising point of VGS changed after stress. The switching performances degraded significantly after stress for 300 seconds.
Fig. 1 Simplified schematic for the switching performance simulation for the power device in Cadence.
Table 1. Parameter shifts due to HC stress. Stress Time (s) 0 120 300
Vth (V)
gm,max (S)
Ron (Ω)
Cgs (pF)
Cgd (pF)
0.514 0.519 0.52
0.044 0.0446 0.0447
7.88 8.85 9.0
0.378 0.381 0.382
0.014 0.015 0.016
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C. Yu et al. / Microelectronics Reliability 46 (2006) 1840–1843
3.0
2.0
15
ID (t) (mA)
VGS(t) and VDS(t) (V)
20 2.5
determined by gate drive internal impedance. From Sec. 2, one gets that Cgd changed 12.5% and Cgs changed 1% after 300 second stress. Therefore, the performance degradation in the DC-DC converter is anticipated. The primary voltage and transformer primary current waveforms are given in Fig. 4 and Fig. 5. One gets that the switching performance shifts in the power LDMOSFET can bring slight changes in the primary voltage and current.
0.25VDS(t) 1.5
ID(t)
10
1.0
6 4
VGS(t)
0.5 0.0
5 2 0
0 5.0
5.5
-2
Time ( us )
-4 -6
Fig. 2 Simulated gate charge plots for VD = 10 V, ID = 100mA, and IG = 0.5 mA. Stress time is 300 s.
0
5
10
(a) 4. HC Effects on full bridge DC-DC converter Voltage of Primary Side (V)
6
A full bridge DC-DC converter given in [3] [6] was established in Cadence with the extracted models from the test device. Here, the input voltage is 12 V, output voltage is 3.3 V, and output inductance is 2.3 μH. Isolation transformer turns ratio is 4: 2. The switching frequency is 200 KHz. The ‘fresh’ and stressed models (stress for 300 seconds) were used for the simulation respectively.
Fresh Stressed
5
4 5.0
5.2
5.4
5.6
5.8
6.0
Time (s)
(b)
Fig. 3 Simplified schematic for the full bridge DCDC converter
For the DC-DC converter application, Cgd is the most important capacitance [6]. It dominates the output switching waveforms through the ‘Miller’ effects. The effects of gate-source capacitance on gate voltage - Cgs and current waveforms are
Fig. 4 Simulated voltage waveforms of the primary side of the transformer. (a) Simulation from 0 us to 10 us; (b) Details in the circle shown in (a).
The efficiency relates to the transient (dynamic) performance of the switching devices [6]. As discussed above, the transient performance of the power device changed after stress. Although the changes is not severe, the efficiency curves for the
C. Yu et al. / Microelectronics Reliability 46 (2006) 1840–1843
fresh and stressed devices tell us that it degraded significantly after HC stress, as shown in Fig. 6.
30 20 10
5. Conclusion Although the parameters shift slightly in our 0.25 μ m high voltage LDMOS, the switching performances degraded significantly. A full bridge DC-DC converter was evaluated by simulation. The primary voltage and current change slightly due to HC stress. However, the key performance – efficiency, suffers from the HC stress significantly.
0
References -10 -20 -30 0
5
10
Current of Primary Side (mA)
(a)
20
10
Fresh Stressed 0 5.0
5.1
5.2
5.3
5.4
5.5
5.6
(b)
Time (s)
Fig. 5 Simulated voltage waveforms of the primary side of the transformer. (a) Simulation from 0 us to 10 us; (b) Details in the circle shown in (a).
Efficiency (%)
90
80
70
Fresh Stressed
60
50 0
5
10
Output Power (mW)
Fig. 6 Efficiency curves. Stress time is 300 s.
[1] H. Mao, S. Deng, J. A. Qahouq, and I. Batarseh, “Active-Clamp Snubbers for Isolated Half-Bridge DC-DC Converters,” IEEE Trans. Pow. Elec., vol. 20, pp. 12941302, Novermber 2005. [2] L. Wuidart, “Topologies for switched mode power supplies,” App. note, p. 17, STMicroelectronics. [3] I. K. Budihardjo, P. O. Lauritzen, and H. A. Mantooth, “Performance Requirements for Power MOSFET Models,” IEEE Tran. Power Elec., vol. 12, pp. 36-45, January 1997. [4] L. Jiang, “Hot-Electron Induced Switching Performance Degradation in High Voltage Submicron LDMOS Transistors,” Dissertation proposal, 2006. [5] http://www.powerdesigners.com/InfoWeb/desi gn center /Appnotes_Archive/an-944.pdf. [6] S. J. Jeon, G. H. Cho, “A Zero-Voltage and Zero-current Swithcing Full Bridge DC-DC Converter with Transformer Isolation,” IEEE Tran. Power Elec., vol. 16, pp. 573-580, September 2001.
1843
.
www.elsevier.com/locate/microrel
Study of performance degradations in DC-DC converter due to hot carrier stress by simulation .
C. Yu, L. Jiang, and J. S. Yuan .
Chip Design and Reliability Laboratory, University of Central Florida, Orlando FL 32816, USA Tel: (407) 823-5719, Fax: (407) 823-5835, email:[email protected], [email protected] .
Abstract The hot carrier effects on the 0.25 μm high voltage LDMOS has been examined by the accelerated stress experiment. Although the model parameters changed slightly, the switching performances degraded significantly, which have been simulated with the compact models extracted from the test devices by ICCAP. A full bridge DC-DC converter with the compact models was proposed in Cadence SpectreRF. The simulated results show that the efficiency of the full bridge DC-DC converter degraded significantly due to the hot carrier effects. .
1. Introduction A power MOSFET is a high-voltage transistor that conducts large amounts of current when turned on. Although a LDMOS is usually designed to reduce the hot carrier (HC) effect by increasing the drain region, the power MOSFETs are used at high voltages and currents [1] – [3]. Under these conditions, hot carrier effects cannot be avoided and cause shifts in device parameters, such as threshold voltage, gain and on-resistance [4]. The evaluation of hot carrier induced degradation becomes very important for developing reliable circuits. The parameter shifts in the power MOSFETs due to HC effects can degrade the performances of their applications, such as the DC-DC converters. Until now, little attention has been paid to the HC effects on the power MOSFETs. The switching performances of the power MOSFETs are sensitive to the device parameters. Little changes in the device parameters can lead to significant performance degradation in the device switching performances, thus the DC-DC converters.
0026-2714/$ - see front matter Ó 2006 Published by Elsevier Ltd. doi:10.1016/j.microrel.2006.07.079
In this paper, the parameter shifts in our 0.25 μ m high voltage LDMOS has been examined experimentally [4]. The results and discussions have been presented. The performance degradations in a full bridge DC-DC converter were evaluation by simulation with the compact models extracted from the test devices. 2. Experimental Results and Discussions The test device is 0.25 × 10 μm2 high voltage LDMOS. It was built on a highly doped p-type substrate to provide isolation to the n-channel device. A lightly doped p-type epi-layer was added to accommodate high voltage capability. The selfaligned channel below the metallized poly-silicon gate was used to improve the device transconductance and gain. The lightly doped drain extension region was introduced to sustain the high drain-source voltage in combination with the epilayer. More device details were given in [4]. The Agilent 4156B Precision Semiconductor Parameter Analyzer was used for stress and I-V characteristic measurement. Agilent 4284A LRC
C. Yu et al. / Microelectronics Reliability 46 (2006) 1840–1843
meter was used to get the capacitances. During the test, the source and substrate were grounded. The stress voltage was applied on the drain and gate. The drain and gate voltage were set at 11.5 V and 3 V for HC stress, respectively. The threshold voltage (Vth), peak transconductance (gm,max), onresistance (Ron), gate-source capacitance (Cgs), and gate-drain capacitance (Cgd) are reported [4] and summarized in Table 1. They changed slightly due to the HC stress. The increases in Vth come from the changes in interface states during HC stress. The changes in Vth lead to the shifts in peak transconductances. Ron is composed of several components including source diffusion resistance, channel resistance, drift region resistance. It is a function of the Vth, transconductance, and drain current. The shifts in these parameters result in the changes of Ron [4]. 3. Degradation in Switching Performance To investigate the stress effects on the switching performance, the circuit as shown in Fig. 1 has been proposed in Cadence. The oscillograms of the gate-to-source voltage neatly delineate between the charge required for the gate-to-source capacitance, and the charge required for the gate-to-drain, or “Miller” capacitance [5]. The switching performances of transistors are determined by the parasitic capacitances, which shifted after stress. The shifts in switching performance were carried out by applying the compact model extracted from the test device before and after stress using ICCAP. It is shown in Fig. 2. Initially, the switch is closed. The gate voltage and drain current are zero. The switch is opened at about 5 us; the gate-tosource capacitance starts to charge, and the gate-tosource voltage increases. Because the shifts in gate-to-source capacitance due to stress, the VGS curve changed after stress in this period. No current flows in the drain until the gate reaches the threshold voltage. At next period, the gate-tosource capacitance continues to charge, the gate voltage continues to rise and the drain current rises proportionally. The threshold voltage changed after stress. Therefore, the start rising point for the drain current shifts. So long as the actual drain current is still building up towards the available drain current, ID, the freewheeling rectifier stays in conduction, the voltage across it remains low, and the voltage across the switch continues to be virtually the full circuit voltage, VDD. The top end of the drain-togate capacitance therefore remains at a fixed
1841
potential. When the drain current reaches ID, and the freewheeling rectifier shuts off; the potential of the drain now is no longer tied to the supply voltage. The drain current now stays constant at the value ID enforced by the current sourcetarts to fall. Since the gate voltage is inextricably related to the drain current by the intrinsic transfer characteristic of the device, the gate voltage now stays constant because the “enforced” drain current is constant. For the time being therefore, no further charge is consumed by the gate-to-source capacitance, because the gate voltage remains constant. Thus the drive current now diverts, in its entirety, into the capacitance Cgd, and the drive circuit charge now contributes exclusively to discharging the Cgd capacitance [5]. Due to the shifts in Cgd after stress, the VGS, VDS, and drain current curves shift due to the stress this. The drain voltage excursion during the next period is relatively large, and hence the total drive charge is typically higher for the Cgd than for the Cgs. When the drain voltage falls to a value equal to ID × RON, and the switch device now comes out of the “active” region of operation. The gate voltage is now no longer constrained by the transfer characteristic of the device to relate to the drain current, and is free to increase. From Sec. 2, one gets that RON degraded after stress. Therefore, the second start rising point of VGS changed after stress. The switching performances degraded significantly after stress for 300 seconds.
Fig. 1 Simplified schematic for the switching performance simulation for the power device in Cadence.
Table 1. Parameter shifts due to HC stress. Stress Time (s) 0 120 300
Vth (V)
gm,max (S)
Ron (Ω)
Cgs (pF)
Cgd (pF)
0.514 0.519 0.52
0.044 0.0446 0.0447
7.88 8.85 9.0
0.378 0.381 0.382
0.014 0.015 0.016
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C. Yu et al. / Microelectronics Reliability 46 (2006) 1840–1843
3.0
2.0
15
ID (t) (mA)
VGS(t) and VDS(t) (V)
20 2.5
determined by gate drive internal impedance. From Sec. 2, one gets that Cgd changed 12.5% and Cgs changed 1% after 300 second stress. Therefore, the performance degradation in the DC-DC converter is anticipated. The primary voltage and transformer primary current waveforms are given in Fig. 4 and Fig. 5. One gets that the switching performance shifts in the power LDMOSFET can bring slight changes in the primary voltage and current.
0.25VDS(t) 1.5
ID(t)
10
1.0
6 4
VGS(t)
0.5 0.0
5 2 0
0 5.0
5.5
-2
Time ( us )
-4 -6
Fig. 2 Simulated gate charge plots for VD = 10 V, ID = 100mA, and IG = 0.5 mA. Stress time is 300 s.
0
5
10
(a) 4. HC Effects on full bridge DC-DC converter Voltage of Primary Side (V)
6
A full bridge DC-DC converter given in [3] [6] was established in Cadence with the extracted models from the test device. Here, the input voltage is 12 V, output voltage is 3.3 V, and output inductance is 2.3 μH. Isolation transformer turns ratio is 4: 2. The switching frequency is 200 KHz. The ‘fresh’ and stressed models (stress for 300 seconds) were used for the simulation respectively.
Fresh Stressed
5
4 5.0
5.2
5.4
5.6
5.8
6.0
Time (s)
(b)
Fig. 3 Simplified schematic for the full bridge DCDC converter
For the DC-DC converter application, Cgd is the most important capacitance [6]. It dominates the output switching waveforms through the ‘Miller’ effects. The effects of gate-source capacitance on gate voltage - Cgs and current waveforms are
Fig. 4 Simulated voltage waveforms of the primary side of the transformer. (a) Simulation from 0 us to 10 us; (b) Details in the circle shown in (a).
The efficiency relates to the transient (dynamic) performance of the switching devices [6]. As discussed above, the transient performance of the power device changed after stress. Although the changes is not severe, the efficiency curves for the
C. Yu et al. / Microelectronics Reliability 46 (2006) 1840–1843
fresh and stressed devices tell us that it degraded significantly after HC stress, as shown in Fig. 6.
30 20 10
5. Conclusion Although the parameters shift slightly in our 0.25 μ m high voltage LDMOS, the switching performances degraded significantly. A full bridge DC-DC converter was evaluated by simulation. The primary voltage and current change slightly due to HC stress. However, the key performance – efficiency, suffers from the HC stress significantly.
0
References -10 -20 -30 0
5
10
Current of Primary Side (mA)
(a)
20
10
Fresh Stressed 0 5.0
5.1
5.2
5.3
5.4
5.5
5.6
(b)
Time (s)
Fig. 5 Simulated voltage waveforms of the primary side of the transformer. (a) Simulation from 0 us to 10 us; (b) Details in the circle shown in (a).
Efficiency (%)
90
80
70
Fresh Stressed
60
50 0
5
10
Output Power (mW)
Fig. 6 Efficiency curves. Stress time is 300 s.
[1] H. Mao, S. Deng, J. A. Qahouq, and I. Batarseh, “Active-Clamp Snubbers for Isolated Half-Bridge DC-DC Converters,” IEEE Trans. Pow. Elec., vol. 20, pp. 12941302, Novermber 2005. [2] L. Wuidart, “Topologies for switched mode power supplies,” App. note, p. 17, STMicroelectronics. [3] I. K. Budihardjo, P. O. Lauritzen, and H. A. Mantooth, “Performance Requirements for Power MOSFET Models,” IEEE Tran. Power Elec., vol. 12, pp. 36-45, January 1997. [4] L. Jiang, “Hot-Electron Induced Switching Performance Degradation in High Voltage Submicron LDMOS Transistors,” Dissertation proposal, 2006. [5] http://www.powerdesigners.com/InfoWeb/desi gn center /Appnotes_Archive/an-944.pdf. [6] S. J. Jeon, G. H. Cho, “A Zero-Voltage and Zero-current Swithcing Full Bridge DC-DC Converter with Transformer Isolation,” IEEE Tran. Power Elec., vol. 16, pp. 573-580, September 2001.
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