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Study of surface-trap-induced gate depletion region of field-modulating plate GaAs–FETs
Solid-State Electronics 50 (2006) 372–377 www.elsevier.com/locate/sse
Study of surface-trap-induced gate depletion region of field-modulating plate GaAs–FETs Akio Wakejima *, Kazuki Ota, Kohji Matsunaga System Devices Research Laboratories, NEC Corporation, 2-9-1 Seiran, Otsu, Shiga 520-0833, Japan Received 7 June 2005; received in revised form 10 January 2006; accepted 10 January 2006 Available online 21 February 2006
The review of this paper was arranged by Prof. C. Tu
Abstract To investigate the cause of the superior RF output power performance of GaAs–FETs with a field-modulating plate, the impact of a field-modulating plate on the surface-trap-induced gate depletion region is evaluated using pulsed I–V characteristics of GaAs–FETs with and without a field-modulating plate. In conventional FETs (without a field-modulating plate), the very high density of the trapped electrons (1012 cm2), which are localized at the gate edge on the drain side, generates a surface depletion region extending deeply in the vertical direction. In FETs with a field-modulating plate, on the other hand, this detrimental phenomenon is significantly suppressed. Finally, this investigation shows that both RF saturated output power measured and that calculated using pulsed I–V characteristics are reasonably consistent. 2006 Elsevier Ltd. All rights reserved. Keywords: GaAs; FET; High power amplifier; Surface trap; Field-modulating plate
1. Introduction Wireless communication continues to grow rapidly, and there is strong demand for high output power amplifiers with high efficiency. It is well-recognized that a GaAsbased power device is inherently suited for high frequency and high power operation because of its excellent electron transport characteristics. However, GaAs-based FETs have serious operation voltage limitations. A common technique to obtain high gate breakdown voltages for a GaAs power FET has been the optimization of gate-todrain recess parameters. However, such attempts have resulted in very limited success since there is commonly a trade-off between breakdown voltage and RF output power [1]. To overcome this trade-off, a GaAs–FET with a field-modulating plate (FP-FET) has been developed [2–8]. It is comprised of an additional MIS-type electrode *
Corresponding author. Tel.: +81 77 537 7688; fax: +81 77 537 7689. E-mail address: [email protected] (A. Wakejima).
0038-1101/$ - see front matter 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2006.01.002
located on the surface passivation layer between the gate and the drain that is modulated in-phase with the gate voltage. Such GaAs-based FP-FETs demonstrated superior RF output power under high voltage operation [4,8]. Two explanations for superior RF output power performance of FP-FETs have been proposed. One, a field-modulating plate can reduce the high electric field between the gate and the drain, so that RF operation at higher drain voltage is enabled [2,5]. This phenomenon is directly evaluated by comparing the gate-to-drain breakdown voltage between FP-FETs and conventional FETs [2]. The other explanation for the superior RF output power performance of FP-FETs is that the field-modulating plate suppresses drain current frequency dispersion caused by surfacetrapped charges [2,6]. So far, for the surface trapping effect between gate and drain, several analyses have been reported based on device simulation results [9–12]. Also, some papers have discussed the trapping effect from the point of view of gate breakdown characteristics [10,11, 13,14]. However, there has been no report of the superior
A. Wakejima et al. / Solid-State Electronics 50 (2006) 372–377
RF power performance of field-modulating plate GaAs– FETs relating to surface-trapped charges. In this paper, we investigate the surface-trap-induced gate depletion region of GaAs–FETs with and without a field-modulating plate using pulsed I–V characteristics [15–17]. We also discuss the relationship between the surface-trap-induced gate depletion region and RF output power. 2. FP-FET structure Fig. 1 illustrates a cross-sectional view of the fabricated FP-FET with an overhanging gate configuration. The epitaxial layers, grown by metal organic chemical vapor deposition (MOCVD), consist of a buffer layer, a 30-nm-thick Si-doped (1 · 1018 cm3) GaAs channel layer, a 20-nmthick Al0.3Ga0.7As Schottky contact layer, a 20-nm-thick GaAs gate buried layer, and a 150-nm-thick Si-doped (5 · 1017 cm3) GaAs Ohmic contact layer. After defining a wide recess region by selective dry etching, a 200-nmthick SiO2 film was deposited on the surface by conventional low-pressure chemical vapor deposition at 320 C. WSi/Au metals were then sputter-deposited in the recessed region to form a buried gate electrode. The eaves of the Tshaped gate overhang on the SiO2 film toward the drain electrode so that the MIS region functions as a field-modulating plate. The gate and gate-to-drain recess lengths (Lg and Lgdr) were 0.8 and 2.5 lm, respectively. The length of the field-modulating plate (Lw), defined as the overhanging length of eaves from the gate edge to the edge on the drain side, was determined to be 1.5 lm for a FP-FET. For comparison, a conventional FET (Lw = 0 lm) was also fabricated. These FETs exhibited almost identical DC drain I–V characteristics with a maximum drain current (I dc max ) of about 190 mA/mm, defined at a drain voltage (Vd) of 4 V, and a gate voltage (Vg) of +1 V, and a threshold voltage (Vth) of 0.43 V. The gate-to-drain breakdown voltage, defined at a gate current of 1 mA/mm, was about 55 V for the FP-FET and about 50 V for the conventional FET.
Fig. 1. Schematic cross section of the fabricated FP-FET structure.
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3. Pulsed I–V characteristics It has often been discussed that drain pulsed I–V measurements [16,17] effectively obtain realistic I–V characteristics of FETs under RF operation. Fig. 2 shows a schematic of gate and drain voltage distributions as a function of time and the transient response of the drain current in pulsed I–V measurements in this paper. During transient from an initial biasing condition of Vd = Vd1 and Vg = Vg1 to a final biasing condition of Vd = Vd2 and Vg = Vg2, Vd was first changed from Vd1 to Vd2 at time (t) of 0. Then Vg was changed from Vg1 to Vg2 at t = 0.1 ls. After that, the final biasing condition continued for 4.0 ls. Then Vg was changed from Vg2 to Vg1 at t = 4.1 ls, and Vd was changed from Vd2 to Vd1 at t = 4.5 ls. The pulse period was 103 ls. The drain current (I pd ) was measured at t = 3.4 ls. Vg1 was determined to be fixed at 0.2 V, which is a comparable gate voltage for class AB RF operation for the fabricated FETs. Fig. 3 shows pulsed I–V characteristics (solid lines) for (a) the FP-FET with Lw = 1.5 lm and (b) the conventional FET (Lw = 0 lm) at Vd1 = 20 V. DC I–V characteristics are also plotted by dotted lines for reference. Fig. 3(b) indicates that pulsed I–V characteristics for the conventional FET are seriously degraded from the DC I–V characteristics. In the FP-FET (see Fig. 3(a)) on the other hand, degradation is significantly suppressed. To quantitatively evaluate differences in I–V characteristics for both FETs, channel constriction factors (DImax and DRon) are defined as DI max ¼
I pmax I dc max I dc max
ð1Þ
Rpon Rdc on ; Rdc on
ð2Þ
and DRon ¼
Fig. 2. Gate and drain voltage distributions as a function of time and transient response of drain current in pulsed I–V measurements. Pulse period and pulse duty were 103 ls and 0.4%, respectively. Pulsed drain current (I pd ) was measured at t = 3.4 ls.
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(a)
(b)
Fig. 3. Comparison between pulsed I–V characteristics (—) and DC I–V characteristics ( ) for (a) the FP-FET with Lw = 1.5 lm and (b) the conventional FET. Pulsed I–V characteristics were measured under initial biasing conditions of Vd1 = 20 V and Vg1 = 0.2 V.
(a)
(b)
Fig. 4. Channel constriction factors ((a) DImax and (b) DRon) as a function of Vd1. Results for FP- and conventional FETs are indicated by s and 4, respectively. p dc where I pmax (I dc max ) and Ron (Ron ) are the maximum drain current and the on-resistance obtained from pulsed (DC) I–V characteristics, respectively. DImax and DRon as a function of Vd1 are shown in Fig. 4(a) and (b), respectively. In pulsed I–V measurements, Vd1 ranged from 4 to 24 V. For the conventional FET, increased Vd1 leads to steep degradation in I pmax and Rpon . At Vd1 = 24 V, DImax and DRon for conventional FET are 44% and 120%, respectively. On the other hand, these detrimental effects of I–V characteristics, which have been discussed as current collapse or channel constriction, are significantly suppressed by employing a field-modulating plate. At Vd1 = 24 V, for example, DImax and DRon for the FP-FET are only 15% and 25%, respectively.
Fig. 5 illustrates such a situation, where the dotted line and the gray area indicate the depletion region under Vg = Vg1 (negative) and Vg = Vg2 (positive), respectively. To simplify the channel constriction situation, it is assumed that depletion depth is constant under the surface-trapped region and that it abruptly changes at the edge of the electron-trapped surface (see Fig. 5). Based on Statz’s model [19], the drain current (Id) is decided by saturated electron velocity (Vs) and sheet carrier density. Using this model
4. Evaluation of extended gate depletion region The above degradation in pulsed I–V characteristics is explained by the channel constriction effect caused by electron trapping at the gate edge on the drain side [2,6,7,12,15]. This is because the time constant of the electron detrapping process of the surface-trapped electrons is hundreds of ls to ms [12,15,18], and in pulsed I–V measurements trapped electrons are frozen at surface states under ls order pulsed biasing conditions, i.e., the depletion region underneath the trapped electrons cannot respond to the gate voltage.
Fig. 5. Schematic of channel constriction effect caused by trapped electrons at the surface. Dotted lines and gray area indicate depletion region under Vg = Vg1 (negative) and Vg = Vg2 (positive), respectively.
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with the channel constriction situation shown in Fig. 5, I pmax is represented as I pmax ¼ W g V s qN s1 ;
ð3Þ
where Wg is gate width and Ns1, the sheet carrier density of the extended depletion region. Also, resistivity at the gateto-drain recessed region in pulsed I–V characteristics (Rpgdr ) is represented as Rpgdr ¼
L1 Lgdr L1 þ ; qN s1 le W g qN s0 le W g
ð4Þ
where le is the electron mobility at the GaAs channel layer, L1, the length of the extended depletion region, and Ns0, the initial sheet carrier concentration at the recessed region. In the model (see Fig. 5), the increase in on-resistance (Rpon Rdc on ) equals Rpon Rdc on ¼ Rgdr Rgdr0 ;
ð5Þ
where Rgdr0 is the initial gate-to-drain resistance at the recessed region, i.e., Rgdr0 = Lgdr/q Ns0 leWg. Using Eqs. (3)– (5), L1 and Ns1 are given by L1 ¼
Rpon Rdc N s1 on Lgdr Rgdr0 N s0 N s1
ð6Þ
and N s1 ¼
I pmax . W gV sq
ð7Þ
Fig. 6(a) and (b) shows L1 and Ns1 calculated using Eqs. (6) and (7) as a function of Vd1. Ns0 used Hall measurement results of 1.9 · 1012 cm2 for the SiO2-encapsulated GaAs– FET structure without a GaAs Ohmic contact layer, and a Vs of 1.3 · 107 cm/s was obtained from DC I–V characteristics with Eq. (3). From Fig. 6(a) and (b), it is found that the extension of L1 and the corresponding degradation in Ns1 are enhanced, especially for the conventional FET as Vd1 is increased. In Fig. 6(a), for example, the L1 for conventional and FP-FETs are about 0.24 and 0.08 lm, respectively. In Fig. 6(b), Ns1 for the conventional FET under Vd1 = 24 V degrades by about 45% comparing to Ns1 under DC biasing conditions. Moreover, from comparisons between L1 for the conventional FET and Lgdr
(a)
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(=2.5 lm) and between Ns1 and Ns0 (=1.9 · 1012 cm2), it is found that the very high density of the trapped electrons is localized at the gate edge on the drain side under high drain voltage conditions. In other words, the channel constriction phenomenon results from deep vertical extension of the depletion region under the gate edge on the drain side rather than shallow horizontal extension. 5. Relation between RF output power and pulsed I–V characteristics As well as pulsed I–V characteristics, RF output power performance is known to be significantly affected by channel constriction effects [2,6,7,12,15]. To compare RF output power performance with pulsed I–V characteristics, continuous wave RF output power was measured at 1.5 GHz for FP- and conventional FETs at an operation voltage (Vdd) up to 20 V. The total gate width of the measured devices was 4.8 mm with a unit gate width of 600 lm. A quiescent current of 25 mA was set with a Vg of about 0.2 V, which was similar to the gate voltage in the above pulsed I–V measurements. All devices were tuned for maximum output power under each operation using external input and output matching circuits. The measured saturation power density (Pmeas) was defined at a 1 dB gain compression point. When the device is tuned for maximum output power, saturated output power density (Pcalc) is approximately given by 1 P calc ¼ ðV dd V knee ÞI max ; 4
ð8Þ
where Vknee is the knee voltage of I–V characteristics defined as the voltage at the intersection of the following two lines: Id = Vd/Ron and Id = Imax. Pulsed I–V characteristics at Vd1 = Vdd can be applied to Eq. (8) because the average drain voltage under RF operation equals Vdd. Therefore, Pcalc is expressed by 1 P calc ¼ ðV dd I pmax Rpon ÞI pmax ; 4
ð9Þ
where I pmax and Rpon are measured values at Vd1 = Vdd. Fig. 7 plots Pmeas for the FP-FET with Lw = 1.5 lm and
(b)
Fig. 6. (a) L1 and (b) Ns1 calculated using Eqs. (6) and (7) as a function of Vd1. Results for FP- and conventional FETs are indicated by s and 4, respectively.
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Fig. 7. Measured saturation power density (Pmeas) of the FP-FET with Lw = 1.5 lm (s) and the conventional FET (4) as a function of Vdd. For comparison, Pcalc for FP- and conventional FETs is also plotted by solid and dotted lines, respectively.
depletion region of GaAs–FETs with and without a fieldmodulating plate, which is quantitatively evaluated using drain pulsed I–V characteristics, was investigated. Degradation in the maximum drain current (Imax) and the onresistance (Ron) for the conventional FET (without a field-modulating plate) occurred by very high density (1012 cm2) surface-trap-induced gate depletion localized at the gate edge on the drain side. On the other hand, in the FET with a field-modulating plate, this detrimental phenomenon is significantly suppressed. Based on these analyses, RF saturated output power measured and calculated using pulsed I–V characteristics are reasonably consistent. Furthermore, the horizontal length of the extended depletion region is in good agreement with the length of the field-modulating plate that dramatically improves the saturated RF output power of GaAs–FETs. Acknowledgment The authors would like to thank I. Takenaka, K. Ishikura, H. Takahashi, Y. Okamoto, Y. Ando, M. Mizuta, M. Kuzuhara, and H. Shimawaki for their helpful comments and discussion. References
Fig. 8. Comparison between Pmeas (s) and Pcalc (—) as a function of Lw.
the conventional FET as a function of Vd. For comparison, Pcalc for FP- and conventional FETs is also plotted by the solid and dotted lines, respectively. The FP-FET exhibits almost linear increase in Pmeas when Vdd is increased to 20 V. On the other hand, the conventional FET exhibits a very small Pmeas increase. As a result, the difference in Pmeas between FP- and conventional FETs becomes larger with an elevated operation voltage. Moreover, Pmeas is consistent with Pcalc for both FETs, which indicates that the suppressed degradation in Ron and Imax of the FP-FET leads to superior RF output power performance. Fig. 8 compares Pcalc (solid line) with Pmeas (circles) for the four types of FETs (Lw = 0, 0.5, 1.0, and 1.5 lm) under 20 V operation. Drastic improvement in both Pmeas and Pcalc is observed when Lw is increased from 0 to 0.5 lm. This improvement indicates that even a shorter Lw of 0.5 lm causes significant suppression of degradation in Imax and Ron because L1 for the conventional FET is about 0.18 lm at Vd1 = 20 V (see Fig. 6(a)). 6. Summary To investigate the cause of the superior RF output power performance of the GaAs–FET with a field-modulating plate, an extension of the surface-trap-induced gate
[1] Wemple SH, Niehaus WC, Cox HM, Dilorenzo JV, Schlosser WO. Control of gate–drain avalanche in GaAs MESFET’s. IEEE Trans Electron Dev 1980;ED-27:1013–8. [2] Asano K, Miyoshi Y, Ishikura K, Nashimoto Y, Kuzuhara M, Mizuta M. Novel high power AlGaAs/GaAs HFET with a fieldmodulating plate operated at 35 V drain voltage. IEEE IEDM Tech Dig 1998:59–62. [3] Sakura N, Matsunaga K, Ishikura K, Takenaka I, Asano K, Iwata N, et al. 100 W L-band GaAs power FP-HFET operated at 30 V. IEEE MTT-S Int Microwave Symp 2000:1715–8. [4] Matsunaga K, Ishikura K, Takenaka I, Contrata W, Wakejima A, Ota K, et al. A low-distortion 230 W GaAs power FP-HFET operated at 22 V for cellular base station. IEEE IEDM Tech 2000:393–6. [5] Hori Y, Kuzuhara M, Ando Y, Mizuta M. Analysis of electric field distribution in GaAs metal-semiconductor field effect transistor with a field-modulating plate. J Appl Phys 2001;87:3483–7. [6] Ito K, Mochizuki Y, Asano K, Miyoshi Y, Nashimoto Y, Kuzuhara M, et al. The mechanism for suppression of gate lag in the novel GaAs power FET with the field-modulating plate. Inst Phys Conf Ser 1999;166:335–8. [7] Wakejima A, Ota K, Matsunaga K, Kuzuhara M. A GaAs-based field-modulating plate HFET with improved WCDMA peak–output– power characteristics. IEEE Trans Electron Dev 2003;ED-50:1983–7. [8] Ota K, Wakejima A, Matsunaga K, Kuzuhara M. 2.2 W/mm GaAs HFET with field-modulating plate operated at 32 V. Int Conf Solid State Dev Mater 2002;SSDM-2002:300–1. [9] Ohno Y, Francis P, Nagome M, Takahashi Y. Surface-state effects on GaAs–FET electrical performance. IEEE Trans Electron Dev 1999;ED-46:214–9. [10] Barton TM, Ladbrooke PH. The role of the device surface in the high voltage behaviour of the GaAs MESFET. Solid-State Electron 1986;29:807–13. [11] Kunihiro K, Takahashi Y, Ohno Y. Physical modeling of off-state breakdown in power GaAs MESFETs. Solid-State Electron 2002;47:621–31.
A. Wakejima et al. / Solid-State Electronics 50 (2006) 372–377 [12] Verzellesi G, Mazzanti A, Basile AF, Boni A, Zanoni E, Canali C. Experimental and numerical assessment of gate-lag phenomena in AlGaAs–GaAs heterostructure field-effect transistors (FETs). IEEE Trans Electron Dev 2003;ED-50:1733–40. [13] Mizuta M, Yamaguchi Y, Takahashi S. Surface potential effect on gate–drain avalanche breakdown in GaAs MESFET. IEEE Trans Electron Dev 1987;ED-34:2027–33. [14] Li CL, Barton TM, Miles RE. Avalanche breakdown and surface deep-level trap effects in GaAs MESFET’s. IEEE Trans Electron Dev 1993;ED-40:811–6. [15] Huang JC, Jackson GS, Shanfield S, Platzker A, Saledas PK, Weichert C. An AlGaAs/InGaAs pseudomorphic high electron mobility transistor with improved breakdown voltage for X- and Ku-band power applications. IEEE Trans Microwave Theory Tech 1993;MTT-41:752–9.
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[16] Malle-Guy B, Ouarch Z, Prigent M, Quere R, Obregon J. Direct extraction of a distributed nonlinear FET model from pulsed I–V/ pulsed S-parameter measurements. IEEE Microwave Guided Wave Lett 1998;8:102–4. [17] Koh K, Park H, Hong S. A spline large-signal FET model based on bias-dependent pulsed I–V measurement. IEEE Trans Microwave Theory Tech 2002;MTT-50:2598–603. [18] Kohno Y, Matsubayashi H, Komaru M, Takano H, Ishihara O, Mitsui S. Modeling and suppression of the surface trap effect on drain current frequency dispersions in GaAs MESFETs. IEEE GaAs IC Symp 1994;16:263–6. [19] Statz H, Haus HA, Pucel RA. Noise characteristics of gallium– arsenide field-effect transistors. IEEE Trans Electron Dev 1974;ED21:549–62.
Study of surface-trap-induced gate depletion region of field-modulating plate GaAs–FETs Akio Wakejima *, Kazuki Ota, Kohji Matsunaga System Devices Research Laboratories, NEC Corporation, 2-9-1 Seiran, Otsu, Shiga 520-0833, Japan Received 7 June 2005; received in revised form 10 January 2006; accepted 10 January 2006 Available online 21 February 2006
The review of this paper was arranged by Prof. C. Tu
Abstract To investigate the cause of the superior RF output power performance of GaAs–FETs with a field-modulating plate, the impact of a field-modulating plate on the surface-trap-induced gate depletion region is evaluated using pulsed I–V characteristics of GaAs–FETs with and without a field-modulating plate. In conventional FETs (without a field-modulating plate), the very high density of the trapped electrons (1012 cm2), which are localized at the gate edge on the drain side, generates a surface depletion region extending deeply in the vertical direction. In FETs with a field-modulating plate, on the other hand, this detrimental phenomenon is significantly suppressed. Finally, this investigation shows that both RF saturated output power measured and that calculated using pulsed I–V characteristics are reasonably consistent. 2006 Elsevier Ltd. All rights reserved. Keywords: GaAs; FET; High power amplifier; Surface trap; Field-modulating plate
1. Introduction Wireless communication continues to grow rapidly, and there is strong demand for high output power amplifiers with high efficiency. It is well-recognized that a GaAsbased power device is inherently suited for high frequency and high power operation because of its excellent electron transport characteristics. However, GaAs-based FETs have serious operation voltage limitations. A common technique to obtain high gate breakdown voltages for a GaAs power FET has been the optimization of gate-todrain recess parameters. However, such attempts have resulted in very limited success since there is commonly a trade-off between breakdown voltage and RF output power [1]. To overcome this trade-off, a GaAs–FET with a field-modulating plate (FP-FET) has been developed [2–8]. It is comprised of an additional MIS-type electrode *
Corresponding author. Tel.: +81 77 537 7688; fax: +81 77 537 7689. E-mail address: [email protected] (A. Wakejima).
0038-1101/$ - see front matter 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2006.01.002
located on the surface passivation layer between the gate and the drain that is modulated in-phase with the gate voltage. Such GaAs-based FP-FETs demonstrated superior RF output power under high voltage operation [4,8]. Two explanations for superior RF output power performance of FP-FETs have been proposed. One, a field-modulating plate can reduce the high electric field between the gate and the drain, so that RF operation at higher drain voltage is enabled [2,5]. This phenomenon is directly evaluated by comparing the gate-to-drain breakdown voltage between FP-FETs and conventional FETs [2]. The other explanation for the superior RF output power performance of FP-FETs is that the field-modulating plate suppresses drain current frequency dispersion caused by surfacetrapped charges [2,6]. So far, for the surface trapping effect between gate and drain, several analyses have been reported based on device simulation results [9–12]. Also, some papers have discussed the trapping effect from the point of view of gate breakdown characteristics [10,11, 13,14]. However, there has been no report of the superior
A. Wakejima et al. / Solid-State Electronics 50 (2006) 372–377
RF power performance of field-modulating plate GaAs– FETs relating to surface-trapped charges. In this paper, we investigate the surface-trap-induced gate depletion region of GaAs–FETs with and without a field-modulating plate using pulsed I–V characteristics [15–17]. We also discuss the relationship between the surface-trap-induced gate depletion region and RF output power. 2. FP-FET structure Fig. 1 illustrates a cross-sectional view of the fabricated FP-FET with an overhanging gate configuration. The epitaxial layers, grown by metal organic chemical vapor deposition (MOCVD), consist of a buffer layer, a 30-nm-thick Si-doped (1 · 1018 cm3) GaAs channel layer, a 20-nmthick Al0.3Ga0.7As Schottky contact layer, a 20-nm-thick GaAs gate buried layer, and a 150-nm-thick Si-doped (5 · 1017 cm3) GaAs Ohmic contact layer. After defining a wide recess region by selective dry etching, a 200-nmthick SiO2 film was deposited on the surface by conventional low-pressure chemical vapor deposition at 320 C. WSi/Au metals were then sputter-deposited in the recessed region to form a buried gate electrode. The eaves of the Tshaped gate overhang on the SiO2 film toward the drain electrode so that the MIS region functions as a field-modulating plate. The gate and gate-to-drain recess lengths (Lg and Lgdr) were 0.8 and 2.5 lm, respectively. The length of the field-modulating plate (Lw), defined as the overhanging length of eaves from the gate edge to the edge on the drain side, was determined to be 1.5 lm for a FP-FET. For comparison, a conventional FET (Lw = 0 lm) was also fabricated. These FETs exhibited almost identical DC drain I–V characteristics with a maximum drain current (I dc max ) of about 190 mA/mm, defined at a drain voltage (Vd) of 4 V, and a gate voltage (Vg) of +1 V, and a threshold voltage (Vth) of 0.43 V. The gate-to-drain breakdown voltage, defined at a gate current of 1 mA/mm, was about 55 V for the FP-FET and about 50 V for the conventional FET.
Fig. 1. Schematic cross section of the fabricated FP-FET structure.
373
3. Pulsed I–V characteristics It has often been discussed that drain pulsed I–V measurements [16,17] effectively obtain realistic I–V characteristics of FETs under RF operation. Fig. 2 shows a schematic of gate and drain voltage distributions as a function of time and the transient response of the drain current in pulsed I–V measurements in this paper. During transient from an initial biasing condition of Vd = Vd1 and Vg = Vg1 to a final biasing condition of Vd = Vd2 and Vg = Vg2, Vd was first changed from Vd1 to Vd2 at time (t) of 0. Then Vg was changed from Vg1 to Vg2 at t = 0.1 ls. After that, the final biasing condition continued for 4.0 ls. Then Vg was changed from Vg2 to Vg1 at t = 4.1 ls, and Vd was changed from Vd2 to Vd1 at t = 4.5 ls. The pulse period was 103 ls. The drain current (I pd ) was measured at t = 3.4 ls. Vg1 was determined to be fixed at 0.2 V, which is a comparable gate voltage for class AB RF operation for the fabricated FETs. Fig. 3 shows pulsed I–V characteristics (solid lines) for (a) the FP-FET with Lw = 1.5 lm and (b) the conventional FET (Lw = 0 lm) at Vd1 = 20 V. DC I–V characteristics are also plotted by dotted lines for reference. Fig. 3(b) indicates that pulsed I–V characteristics for the conventional FET are seriously degraded from the DC I–V characteristics. In the FP-FET (see Fig. 3(a)) on the other hand, degradation is significantly suppressed. To quantitatively evaluate differences in I–V characteristics for both FETs, channel constriction factors (DImax and DRon) are defined as DI max ¼
I pmax I dc max I dc max
ð1Þ
Rpon Rdc on ; Rdc on
ð2Þ
and DRon ¼
Fig. 2. Gate and drain voltage distributions as a function of time and transient response of drain current in pulsed I–V measurements. Pulse period and pulse duty were 103 ls and 0.4%, respectively. Pulsed drain current (I pd ) was measured at t = 3.4 ls.
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(a)
(b)
Fig. 3. Comparison between pulsed I–V characteristics (—) and DC I–V characteristics ( ) for (a) the FP-FET with Lw = 1.5 lm and (b) the conventional FET. Pulsed I–V characteristics were measured under initial biasing conditions of Vd1 = 20 V and Vg1 = 0.2 V.
(a)
(b)
Fig. 4. Channel constriction factors ((a) DImax and (b) DRon) as a function of Vd1. Results for FP- and conventional FETs are indicated by s and 4, respectively. p dc where I pmax (I dc max ) and Ron (Ron ) are the maximum drain current and the on-resistance obtained from pulsed (DC) I–V characteristics, respectively. DImax and DRon as a function of Vd1 are shown in Fig. 4(a) and (b), respectively. In pulsed I–V measurements, Vd1 ranged from 4 to 24 V. For the conventional FET, increased Vd1 leads to steep degradation in I pmax and Rpon . At Vd1 = 24 V, DImax and DRon for conventional FET are 44% and 120%, respectively. On the other hand, these detrimental effects of I–V characteristics, which have been discussed as current collapse or channel constriction, are significantly suppressed by employing a field-modulating plate. At Vd1 = 24 V, for example, DImax and DRon for the FP-FET are only 15% and 25%, respectively.
Fig. 5 illustrates such a situation, where the dotted line and the gray area indicate the depletion region under Vg = Vg1 (negative) and Vg = Vg2 (positive), respectively. To simplify the channel constriction situation, it is assumed that depletion depth is constant under the surface-trapped region and that it abruptly changes at the edge of the electron-trapped surface (see Fig. 5). Based on Statz’s model [19], the drain current (Id) is decided by saturated electron velocity (Vs) and sheet carrier density. Using this model
4. Evaluation of extended gate depletion region The above degradation in pulsed I–V characteristics is explained by the channel constriction effect caused by electron trapping at the gate edge on the drain side [2,6,7,12,15]. This is because the time constant of the electron detrapping process of the surface-trapped electrons is hundreds of ls to ms [12,15,18], and in pulsed I–V measurements trapped electrons are frozen at surface states under ls order pulsed biasing conditions, i.e., the depletion region underneath the trapped electrons cannot respond to the gate voltage.
Fig. 5. Schematic of channel constriction effect caused by trapped electrons at the surface. Dotted lines and gray area indicate depletion region under Vg = Vg1 (negative) and Vg = Vg2 (positive), respectively.
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with the channel constriction situation shown in Fig. 5, I pmax is represented as I pmax ¼ W g V s qN s1 ;
ð3Þ
where Wg is gate width and Ns1, the sheet carrier density of the extended depletion region. Also, resistivity at the gateto-drain recessed region in pulsed I–V characteristics (Rpgdr ) is represented as Rpgdr ¼
L1 Lgdr L1 þ ; qN s1 le W g qN s0 le W g
ð4Þ
where le is the electron mobility at the GaAs channel layer, L1, the length of the extended depletion region, and Ns0, the initial sheet carrier concentration at the recessed region. In the model (see Fig. 5), the increase in on-resistance (Rpon Rdc on ) equals Rpon Rdc on ¼ Rgdr Rgdr0 ;
ð5Þ
where Rgdr0 is the initial gate-to-drain resistance at the recessed region, i.e., Rgdr0 = Lgdr/q Ns0 leWg. Using Eqs. (3)– (5), L1 and Ns1 are given by L1 ¼
Rpon Rdc N s1 on Lgdr Rgdr0 N s0 N s1
ð6Þ
and N s1 ¼
I pmax . W gV sq
ð7Þ
Fig. 6(a) and (b) shows L1 and Ns1 calculated using Eqs. (6) and (7) as a function of Vd1. Ns0 used Hall measurement results of 1.9 · 1012 cm2 for the SiO2-encapsulated GaAs– FET structure without a GaAs Ohmic contact layer, and a Vs of 1.3 · 107 cm/s was obtained from DC I–V characteristics with Eq. (3). From Fig. 6(a) and (b), it is found that the extension of L1 and the corresponding degradation in Ns1 are enhanced, especially for the conventional FET as Vd1 is increased. In Fig. 6(a), for example, the L1 for conventional and FP-FETs are about 0.24 and 0.08 lm, respectively. In Fig. 6(b), Ns1 for the conventional FET under Vd1 = 24 V degrades by about 45% comparing to Ns1 under DC biasing conditions. Moreover, from comparisons between L1 for the conventional FET and Lgdr
(a)
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(=2.5 lm) and between Ns1 and Ns0 (=1.9 · 1012 cm2), it is found that the very high density of the trapped electrons is localized at the gate edge on the drain side under high drain voltage conditions. In other words, the channel constriction phenomenon results from deep vertical extension of the depletion region under the gate edge on the drain side rather than shallow horizontal extension. 5. Relation between RF output power and pulsed I–V characteristics As well as pulsed I–V characteristics, RF output power performance is known to be significantly affected by channel constriction effects [2,6,7,12,15]. To compare RF output power performance with pulsed I–V characteristics, continuous wave RF output power was measured at 1.5 GHz for FP- and conventional FETs at an operation voltage (Vdd) up to 20 V. The total gate width of the measured devices was 4.8 mm with a unit gate width of 600 lm. A quiescent current of 25 mA was set with a Vg of about 0.2 V, which was similar to the gate voltage in the above pulsed I–V measurements. All devices were tuned for maximum output power under each operation using external input and output matching circuits. The measured saturation power density (Pmeas) was defined at a 1 dB gain compression point. When the device is tuned for maximum output power, saturated output power density (Pcalc) is approximately given by 1 P calc ¼ ðV dd V knee ÞI max ; 4
ð8Þ
where Vknee is the knee voltage of I–V characteristics defined as the voltage at the intersection of the following two lines: Id = Vd/Ron and Id = Imax. Pulsed I–V characteristics at Vd1 = Vdd can be applied to Eq. (8) because the average drain voltage under RF operation equals Vdd. Therefore, Pcalc is expressed by 1 P calc ¼ ðV dd I pmax Rpon ÞI pmax ; 4
ð9Þ
where I pmax and Rpon are measured values at Vd1 = Vdd. Fig. 7 plots Pmeas for the FP-FET with Lw = 1.5 lm and
(b)
Fig. 6. (a) L1 and (b) Ns1 calculated using Eqs. (6) and (7) as a function of Vd1. Results for FP- and conventional FETs are indicated by s and 4, respectively.
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Fig. 7. Measured saturation power density (Pmeas) of the FP-FET with Lw = 1.5 lm (s) and the conventional FET (4) as a function of Vdd. For comparison, Pcalc for FP- and conventional FETs is also plotted by solid and dotted lines, respectively.
depletion region of GaAs–FETs with and without a fieldmodulating plate, which is quantitatively evaluated using drain pulsed I–V characteristics, was investigated. Degradation in the maximum drain current (Imax) and the onresistance (Ron) for the conventional FET (without a field-modulating plate) occurred by very high density (1012 cm2) surface-trap-induced gate depletion localized at the gate edge on the drain side. On the other hand, in the FET with a field-modulating plate, this detrimental phenomenon is significantly suppressed. Based on these analyses, RF saturated output power measured and calculated using pulsed I–V characteristics are reasonably consistent. Furthermore, the horizontal length of the extended depletion region is in good agreement with the length of the field-modulating plate that dramatically improves the saturated RF output power of GaAs–FETs. Acknowledgment The authors would like to thank I. Takenaka, K. Ishikura, H. Takahashi, Y. Okamoto, Y. Ando, M. Mizuta, M. Kuzuhara, and H. Shimawaki for their helpful comments and discussion. References
Fig. 8. Comparison between Pmeas (s) and Pcalc (—) as a function of Lw.
the conventional FET as a function of Vd. For comparison, Pcalc for FP- and conventional FETs is also plotted by the solid and dotted lines, respectively. The FP-FET exhibits almost linear increase in Pmeas when Vdd is increased to 20 V. On the other hand, the conventional FET exhibits a very small Pmeas increase. As a result, the difference in Pmeas between FP- and conventional FETs becomes larger with an elevated operation voltage. Moreover, Pmeas is consistent with Pcalc for both FETs, which indicates that the suppressed degradation in Ron and Imax of the FP-FET leads to superior RF output power performance. Fig. 8 compares Pcalc (solid line) with Pmeas (circles) for the four types of FETs (Lw = 0, 0.5, 1.0, and 1.5 lm) under 20 V operation. Drastic improvement in both Pmeas and Pcalc is observed when Lw is increased from 0 to 0.5 lm. This improvement indicates that even a shorter Lw of 0.5 lm causes significant suppression of degradation in Imax and Ron because L1 for the conventional FET is about 0.18 lm at Vd1 = 20 V (see Fig. 6(a)). 6. Summary To investigate the cause of the superior RF output power performance of the GaAs–FET with a field-modulating plate, an extension of the surface-trap-induced gate
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