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Study on SrTiO3 film for the application of power devices
Superlattices and Microstructures 130 (2019) 168–174
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Study on SrTiO3 film for the application of power devices Jingjie Lin a, Junji Cheng a, *, Ping Li b, Weizhen Chen a, Haimeng Huang a a
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, 610054, China b Chongqing Engineering Laboratory of High Performance Integrated Circuits, School of Microelectronics and Communication Engineering, Chongqing University (CQU), Chongqing, 400044, China
A R T I C L E I N F O
A B S T R A C T
Keywords: High-k (HK) SrTiO3 (STO) Power device Breakdown voltage (BV) Dose deviation
In this study, SrTiO3 (STO) film without cracks is directly deposited on the surface of silicon. Some key characteristics of the film are measured. By taking the measurement results into the simulation, it is verified that the STO film is able to improve the surface electric field distribution of the lateral power devices. Meanwhile, the film can expand the process window to resist dose deviation by more than twice, which promises enhanced product yield. This study provides a reference for the material selection of High-k (HK) insulators, which have been used to develop the power semiconductor devices.
1. Introduction The High-k (HK) insulator which features an extremely larger dielectric constant than silicon (Si) has been widely used in the power semiconductor devices [1–5]. LDMOS (laterally diffused metal oxide semiconductor), one of the most important transistor type in the power semiconductor devices, could be improved by depositing HK material on its surface. The electric field distribution of the drift region could be optimized, and thereby the breakdown voltage (BV) of the device could be increased [2]. Although the HK material presents an excellent potential to develop the power devices, the material selection is an intractable problem. JunHong Li et al. have used PZT (Lead zirconate titanate) as HK insulator to improve LDMOS [6]. However, PZT is a ferroelectric material and exhibits residual polarization in a changing electric field, which might seriously degrade the switching performance of the device [7]. In this study, we suggest SrTiO3 (STO) as a better candidate. The Curie point of STO is below 150 K, which means that it presents paraelectricity at the normal operating temperature of the power device (223 K - 423 K) [8,9]. The HK material is usually designed to be deposited on Si or SiO2 directly. Too thick STO film may crack due to the different thermal expansion between STO and Si. In this study, the STO film of varying thickness is deposited on Si substrates to find a suitable value of thickness. In addition, the thermal process and the film etching process are taken into account to meet the requirement of the power devices. Finally, by taking the experimental results into the simulation, the lateral power devices improved by the proposed STO film are studied as application examples. 2. Experiment and results Common methods for preparing the STO film include chemical vapor deposition (CVD), radio frequency (RF) magnetron
* Corresponding author. E-mail address: [email protected] (J. Cheng). https://doi.org/10.1016/j.spmi.2019.04.033 Received 6 January 2019; Received in revised form 9 March 2019; Accepted 19 April 2019 Available online 22 April 2019 0749-6036/© 2019 Elsevier Ltd. All rights reserved.
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sputtering, pulsed laser deposition (PLD), and sol-gel methods [10–13]. Because of the advantages of low substrate temperature, RF magnetron sputtering is selected in this paper. As shown in Fig. 1, using a multi-station RF magnetron sputtering system, six samples can be processed at one time. Each substrate rotates at a constant speed and simultaneously revolves around the central axis. With this system, the film could achieve better uniformity and less stress inside. The STO is sputtered on Si wafers and the Pt (Platinum) layer, in order to test the suitability of STO/Si and the dielectric constant of STO. The experiment uses N-type Si substrates with a crystal orientation of h100i, flatness (TIR) < 3 μm, a resistivity of 0.001–0.005 Ω/ cm and warpage (TTV) < 10 μm. All the substrates are cleaned by RCA steps and hydrophobic treatment. Under a gas atmosphere of Ar (Argon), the STO is sputtered on the 300 � C substrates with a power of 90 W. After sputtering, the film is annealed at 700 � C for 40 min, and the rate of heating and cooling is 10 � C/5 min. Fig. 2 shows the surface topography of the STO film of different thickness, obtained by an optical microscope. It can be seen that the annealed STO film on Si substrate is uniform when the thickness under 400 nm and it begins to be non-uniform or cracked when the thickness reaches 500 nm. Due to the different thermal expansion of STO and Si, the thicker the STO film, the greater the internal stress. The X-ray diffraction (XRD) test result of 400-nm-thick annealed film is shown in Fig. 3. All the peaks in the pattern are ascribed to STO and the Si substrate. Further analysis indicates that the STO film grows in different crystal orientation and exhibits polycrystalline. Fig. 4 shows the cross-section of the annealed STO film sputtered on the Pt layer, which is carried out by scanning electron mi croscope (SEM). The STO film is uniform without cracks, and the thickness could reach to 850 nm. Due to the buffer effect of the Pt layer, the difference of the thermal expansion between STO and silicon could be weakened. As a result, the maximum thickness of the uniform STO film sputtered on the Pt layer could be larger than that directly sputtered on Si substrate. The buffered Pt layer has also been used in some other reports [12,15]. As shown in Fig. 5, using a deposited copper layer and the Pt layer as the upper and lower electrodes of the STO film capacitor, the electrical properties of STO could be tested. Fig. 6 shows the capacitance-frequency characteristics. The capacitance of this structure is about 5 nF at a frequency up to 200 kHz. According to the calculation formula of a plate capacitor, relative dielectric constant εr can be expressed by capacitance C as
εr ¼
Cd
ε0 A
where ε0 is vacuum dielectric constant, A is the area of the plates (2.12 mm2 in this case), and d is the spacing between the two plates. It could be calculated that the relative dielectric constant of the STO film prepared in this paper is 213.4. This electrical test results are obtained at a temperature of 300 K. In order to meet the requirement of the electrode contact in power devices, wet etching experiments are performed on the 400-nmthick STO film. The Si wafers with the STO film are ultrasonically cleaned in acetone, alcohol and deionized water in turn. The etching solution is prepared by mixing HNO3, BHF solution and H2O in a volume ratio of 1 : 2: 5. The BHF solution is composed of 50% HF solution and 40% NH4F solution in a volume ratio of 1 : 5. Then, the photoresist is spin-coated on the film as a barrier layer. A sawtooth pattern mask with a feature size of 2 μm is used to expose and develop the photoresist. Finally, the STO film is etched by the etching solution in a 50 � C water bath for 12 s. Fig. 7 is the surface optical image of the etched film, and this clear profile indicates that the STO film could be successfully etched with 2-μm -feature, which is enough for electrode contact in power devices.
Fig. 1. Schematic of multi-station RF magnetron sputtering system. 169
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Fig. 2. Surface morphology of the STO film samples of different thickness: (a) 300 nm (b) 400 nm (c) 500 nm (d) 600 nm.
Fig. 3. XRD pattern of the 400-nm-thick STO film on Si substrate annealed at 700 � C.
Fig. 4. Cross-section of the STO film on Pt layer, carried out by SEM.
3. Application 3.1. HK-OPTVLD The OPTVLD (optimized variational doping) technology [16], as shown in Fig. 8(a), has been widely used in the lateral power semiconductor devices. In this technology, by introducing additional charges into the surface of the drift region, the device could sustain the BV as high as possible within a shortest width. These additional charges are realized by the optimized P-VLD (P-type variational doping) layer, which is usually one-time implanted through the finger strip mask [17]. Although the cost could be reduced by this implanting method, the actual dose of the P-VLD layer would be serious uneven on the surface of the device. Based on this, an extremely high-precision process is needed to limit the dose deviation. In our study, the process window of the device with OPTVLD could be expanded by the proposed STO film. The structure of OPTVLD with the proposed STO film (HK-OPTVLD) is shown in Fig. 8(b). The numerical simulation in MEDICI 170
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Fig. 5. Structure of the STO film capacitor.
Fig. 6. Capacitance at different applied electric field changing frequencies.
Fig. 7. Optical microscope image of the etched 400-nm-thick STO film.
software is performed to verify the advantage of HK-OPTVLD. Physical models for simulation include concentration and temperature dependent mobility model, mobility model using perpendicular and parallel electric field component, the Shockley-Read-Hall recombination model, the impact ionization model and Auger recombination model. Both the previous OPTVLD and HK-OPTVLD achieve the same BV of 680 V at room temperature (300 K). Based on the experimental results of the film, the relative dielectric constant of STO is set to 213, and the film thickness is under 400 nm. The main design parameters of the devices are shown in Table 1. Fig. 9 shows the variation of BV with the dose deviation of P-VLD. The distinguished curves indicate that the STO film could 171
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Fig. 8. Device structures of (a) the previous OPTVLD and (b) the proposed HK-OPTVLD. Table 1 Key parameters. Parameters
OPTVLD
OPTVLD LDMOS
Thickness of STO film (nm) Relative dielectric permittivity Length of drift region (μm) P-VLD P1 dose (cm 2) P-VLD P2 dose (cm 2) P-VLD P3 dose (cm 2) P-VLD P4 dose (cm 2) P-VLD P5 dose (cm 2) N substrate doping density (cm 3) P-well dose (cm 2) N-well dose (cm 2) P-top dose (cm 2) Pþ doping density (cm 3) Nþ doping density (cm 3)
0/200/300/400 213 130 2.0e16 1.9e16 1.8e16 / / 2.5e14 / / / 6e19 6e19
0/400 213 40 4.0e12 3.6e12 3.2e12 1.1e12 3.0e12 7.0e14 2.5e12 3.5e12 3.4e12 6e19 6e19
Fig. 9. Influence of P-VLD dose deviation on BV of the device (a) T ¼ 300 K (b) T ¼ 473 K.
effectively resist the influence from the dose deviation of P-VLD. The thicker the STO film, the better this effect. When the temperature is 300 K, to ensure that the previous OPTVLD has 90% of the maximum BV (0.9 BVmax) at least, the acceptable range of the P-VLD dose deviation is 14%, and that of HK-OPTVLD could be improved to 37%. When the temperature rises to 473 K, these two ranges of OPTVLD and HK-OPTVLD are 16% and 42%, respectively. The results show that the STO film could expand the process window of PVLD dose by more than 2.6 times. Considering the dielectric constant of the STO film may deviate with different deposition methods, film thicknesses and application temperatures [12,14,15], Fig. 10 shows the different improvement of HK-OPTVLD when the relative dielectric constant varies from 100 to 500. It indicates that the film with a larger dielectric constant could expand the process window more, and then the HK-OPTVLD get better improvement. 3.2. HK-OPTVLD LDMOS As shown in Fig. 11, the dual-channel conductive OPTVLD LDMOS [18] could also be improved by the STO film. The buried P-VLD layer and N-well are fabricated in the early stage of the whole process, and a lot of subsequent high-temperature diffusion time is 172
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Fig. 10. The different improvement when the dielectric constant of the HK film varies from 100 to 500.
Fig. 11. Device structures of (a) the previous OPTVLD and (b) the proposed HK-OPTVLD.
followed. Compared to the surface P-VLD in Sample 1, the actual dose of the buried P-VLD layer and N-well may be more difficult to control. As a consequence, the deviation may be greater and the impact on BV may be more serious. The main design parameters of the device are shown in Table 1. Both the previous and the improved OPTVLD LDMOS have the same BV of 300 V. Fig. 12(a) shows the variation of BV with the dose deviation of the buried P-VLD layer. Likewise, to ensure that the device has 0.9 BVmax at least, the process window of the previous structure is 11%, and that of HK-OPTVLD LDMOS could be improved to 20%. The result shows that the improved OPTVLD LDMOS could nearly double the process window of the buried P-VLD dose. Considering that the dose of N-well may also deviate simultaneously, there are two extremes in the device. The first is that the PVLD dose is too large when the N-well dose is too small, and the second is that the P-VLD dose is too small when the N-well dose is too large. After the impurity compensation, these two situations lead to more serious dose deviation. Fig. 12(b) shows the performance of BV in these two cases. It could be concluded that the previous structure is more seriously affected, and the STO film could effectively improve this performance. Another application of STO could be in the vertical double-diffused metal oxide semiconductor (VDMOS). By implementing interdigitated HK insulators in the drift region, the trade-off relationship between BV and specific on-resistance could be improved,
Fig. 12. BV curves of the device when (a) only the P-VLD dose deviates and (b) both N-well and P-VLD dose deviate. 173
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which even closes to that of the super-junction VDMOS (SJ-VDMOS) and breaks the well-known “Silicon limit” [19]. Although the STO process in our study cannot fill the deep trench yet, the test results could provide a reference to realize this high-performance device. 4. Conclusion According to the research in this paper, the properties of STO meet the requirements of power semiconductor devices with HK insulators. The 400-nm-thick STO film without cracks is successfully deposited on the silicon surface. The test result shows that the film has a stable dielectric constant of more than 200 at a frequency up to 200 kHz. The film could be etched with 2-μm-feature, which is enough for electrode contact in power devices. By taking the measurement results into the simulation, it is verified that the device with OPTVLD could be improved by the STO film. The process window of impurity dose could be expanded by more than twice, and this could effectively develop the yield rate and the reliability of the product. We also find that the STO film with a larger dielectric constant could bring better improvement. Moreover, this work could provide a reference for material selection of HK insulators in power devices. Acknowledgements The authors would like to thank Dr. J. Deng, Dr. H. Li, Prof. J. H. Zhang, Prof. H. W. Chen and Mr. Y. Zheng for their help in the experimental part of this paper. This work was supported in part by the Youth Fund of Natural Science Foundation of China under Grant 61604030and Grant 51607026. References [1] X.B. Chen, Super-junction Voltage Sustaining Layer with Alternating Semiconductor and High-K Dielectric Regions, 2002. [2] X.B. Chen, Lateral High-Voltage Semiconductor Devices with Surface Covered by Thin Film of Dielectric Material with High Permittivity, 2003. [3] J. Deng, M.H. Huang, J.J. Cheng, X.J. Lyu, X.B. Chen, A new low specific on-resistance Hk-LDMOS with N-poly diode, Superlattice. Microst. 101 (2017) 180–190, https://doi.org/10.1016/j.spmi.2016.11.049. [4] M.H. Huang, X.B. Chen, Vertical power Schottky barrier diodes using a high-k insulator, Semicond. Sci. Technol. 30 (2015), https://doi.org/10.1088/02681242/30/10/105021. [5] Q. Wang, P. Wang, Y.H. Jiang, K. Zhou, G.L. Yao, X.R. Luo, A new SJ VDMOS with an extended HK dielectric-filling trench, in: ICSICT 2012 - 2012 IEEE 11th Int. Conf. Solid-State Integr. Circuit Technol. Proc., 2012, pp. 5–7, https://doi.org/10.1109/ICSICT.2012.6467703. [6] J. Li, P. Li, W. Huo, G. Zhang, Y. Zhai, X. Chen, Analysis and fabrication of an LDMOS with high-permittivity dielectric, IEEE Electron. Device Lett. 32 (2011) 1266–1268, https://doi.org/10.1109/LED.2011.2158383. [7] H. Yan, F. Inam, G. Viola, H. Ning, H. Zhang, Q. Jiang, T. Zeng, Z. Gao, M.J. Reece, The contribution of electrical conductivity, dielectric permittivity and domain switching in ferroelectric hysteresis loops, J. Adv. Dielectr. 1 (2011) 107–118, https://doi.org/10.1142/S2010135X11000148. [8] M. Trainer, Ferroelectricity: measurement of the dielectric susceptibility of strontium titanate at low temperatures, Am. J. Phys. 69 (2001) 966–969, https://doi. org/10.1119/1.1374251. [9] A. Naugarhiya, P.N. Kondekar, High permittivity material selection for design of optimum Hk VDMOS, Superlattice. Microst. 83 (2015) 310–321, https://doi. org/10.1016/j.spmi.2015.02.045. [10] Z. Wang, V. Kugler, U. Helmersson, N. Konofaos, E.K. Evangelou, S. Nakao, P. Jin, Electrical properties of SrTiO3 thin films on Si deposited by magnetron sputtering at low temperature, Appl. Phys. Lett. 79 (2001) 1513–1515, https://doi.org/10.1063/1.1398321. [11] N.-K. Kim, S.-G. Yoon, W.-J. Lee, H.-G. Kim, Electrical and structural properties of SrTiO3 thin films deposited by plasma-enhanced metalorganic chemical vapor deposition, J. Mater. Res. (1997) 2–6, https://doi.org/10.1557/JMR.1997.0160. [12] F.M. Pontes, E.J.H. Lee, E.R. Leite, E. Longo, High dielectric constant of SrTiO3 thin films prepared by chemical process, J. Mater. Sci. 35 (2000) 4783–4787, https://doi.org/10.1023/A:1004816611050. [13] F.M. Pontes, E. Longo, E.R. Leite, J.A. Varela, Study of the dielectric and ferroelectric properties of chemically processed BaxSr1 xTiO3 thin films, Thin Solid Films 386 (2001) 91–98, https://doi.org/10.1016/S0040-6090(01)00781-7. [14] H.-C. Li, W. Si, A.D. West, X.X. Xi, Thickness dependence of dielectric loss in SrTiO3 thin films, Appl. Phys. Lett. 464 (1998), https://doi.org/10.1063/1.121901. [15] K. Abe, S. Komatsu, Measurement and thermodynamic analyses of the dielectric constant of epitaxially grown SrTiO 3 films, Jpn. J. Appl. Phys. 35 (1993) L1157–L1159, https://doi.org/10.1143/JJAP.32.L1157. [16] X.B. Chen, B. Zhang, Z.J. Li, Theory of optimum design of reverse-biased p-n junctions using resistive field plates and variation lateral doping, Solid State Electron. 35 (1992) 1365–1370. [17] X.B. Chen, Lateral high-voltage devices using an optimized variational lateral doping, Int. J. Electron. 80 (1996) 449–459, https://doi.org/10.1080/ 002072196137291. [18] J.J. Cheng, X.B. Chen, Low specific on-resistance p-type OPTVLDLDMOS with double hole-conductive paths for SPIC application, in: 24th Int. Symp. Power Semicond. Devices ICs, 2012, 2012, pp. 225–228, https://doi.org/10.1109/ISPSD.2012.6229064. [19] X.B. Chen, M.M. Huang, A vertical power MOSFET with an interdigitated drift region using high-k insulator, IEEE Trans. Electron Devices 59 (2012) 2430–2437, https://doi.org/10.1109/TED.2012.2204890.
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Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Study on SrTiO3 film for the application of power devices Jingjie Lin a, Junji Cheng a, *, Ping Li b, Weizhen Chen a, Haimeng Huang a a
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, 610054, China b Chongqing Engineering Laboratory of High Performance Integrated Circuits, School of Microelectronics and Communication Engineering, Chongqing University (CQU), Chongqing, 400044, China
A R T I C L E I N F O
A B S T R A C T
Keywords: High-k (HK) SrTiO3 (STO) Power device Breakdown voltage (BV) Dose deviation
In this study, SrTiO3 (STO) film without cracks is directly deposited on the surface of silicon. Some key characteristics of the film are measured. By taking the measurement results into the simulation, it is verified that the STO film is able to improve the surface electric field distribution of the lateral power devices. Meanwhile, the film can expand the process window to resist dose deviation by more than twice, which promises enhanced product yield. This study provides a reference for the material selection of High-k (HK) insulators, which have been used to develop the power semiconductor devices.
1. Introduction The High-k (HK) insulator which features an extremely larger dielectric constant than silicon (Si) has been widely used in the power semiconductor devices [1–5]. LDMOS (laterally diffused metal oxide semiconductor), one of the most important transistor type in the power semiconductor devices, could be improved by depositing HK material on its surface. The electric field distribution of the drift region could be optimized, and thereby the breakdown voltage (BV) of the device could be increased [2]. Although the HK material presents an excellent potential to develop the power devices, the material selection is an intractable problem. JunHong Li et al. have used PZT (Lead zirconate titanate) as HK insulator to improve LDMOS [6]. However, PZT is a ferroelectric material and exhibits residual polarization in a changing electric field, which might seriously degrade the switching performance of the device [7]. In this study, we suggest SrTiO3 (STO) as a better candidate. The Curie point of STO is below 150 K, which means that it presents paraelectricity at the normal operating temperature of the power device (223 K - 423 K) [8,9]. The HK material is usually designed to be deposited on Si or SiO2 directly. Too thick STO film may crack due to the different thermal expansion between STO and Si. In this study, the STO film of varying thickness is deposited on Si substrates to find a suitable value of thickness. In addition, the thermal process and the film etching process are taken into account to meet the requirement of the power devices. Finally, by taking the experimental results into the simulation, the lateral power devices improved by the proposed STO film are studied as application examples. 2. Experiment and results Common methods for preparing the STO film include chemical vapor deposition (CVD), radio frequency (RF) magnetron
* Corresponding author. E-mail address: [email protected] (J. Cheng). https://doi.org/10.1016/j.spmi.2019.04.033 Received 6 January 2019; Received in revised form 9 March 2019; Accepted 19 April 2019 Available online 22 April 2019 0749-6036/© 2019 Elsevier Ltd. All rights reserved.
Superlattices and Microstructures 130 (2019) 168–174
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sputtering, pulsed laser deposition (PLD), and sol-gel methods [10–13]. Because of the advantages of low substrate temperature, RF magnetron sputtering is selected in this paper. As shown in Fig. 1, using a multi-station RF magnetron sputtering system, six samples can be processed at one time. Each substrate rotates at a constant speed and simultaneously revolves around the central axis. With this system, the film could achieve better uniformity and less stress inside. The STO is sputtered on Si wafers and the Pt (Platinum) layer, in order to test the suitability of STO/Si and the dielectric constant of STO. The experiment uses N-type Si substrates with a crystal orientation of h100i, flatness (TIR) < 3 μm, a resistivity of 0.001–0.005 Ω/ cm and warpage (TTV) < 10 μm. All the substrates are cleaned by RCA steps and hydrophobic treatment. Under a gas atmosphere of Ar (Argon), the STO is sputtered on the 300 � C substrates with a power of 90 W. After sputtering, the film is annealed at 700 � C for 40 min, and the rate of heating and cooling is 10 � C/5 min. Fig. 2 shows the surface topography of the STO film of different thickness, obtained by an optical microscope. It can be seen that the annealed STO film on Si substrate is uniform when the thickness under 400 nm and it begins to be non-uniform or cracked when the thickness reaches 500 nm. Due to the different thermal expansion of STO and Si, the thicker the STO film, the greater the internal stress. The X-ray diffraction (XRD) test result of 400-nm-thick annealed film is shown in Fig. 3. All the peaks in the pattern are ascribed to STO and the Si substrate. Further analysis indicates that the STO film grows in different crystal orientation and exhibits polycrystalline. Fig. 4 shows the cross-section of the annealed STO film sputtered on the Pt layer, which is carried out by scanning electron mi croscope (SEM). The STO film is uniform without cracks, and the thickness could reach to 850 nm. Due to the buffer effect of the Pt layer, the difference of the thermal expansion between STO and silicon could be weakened. As a result, the maximum thickness of the uniform STO film sputtered on the Pt layer could be larger than that directly sputtered on Si substrate. The buffered Pt layer has also been used in some other reports [12,15]. As shown in Fig. 5, using a deposited copper layer and the Pt layer as the upper and lower electrodes of the STO film capacitor, the electrical properties of STO could be tested. Fig. 6 shows the capacitance-frequency characteristics. The capacitance of this structure is about 5 nF at a frequency up to 200 kHz. According to the calculation formula of a plate capacitor, relative dielectric constant εr can be expressed by capacitance C as
εr ¼
Cd
ε0 A
where ε0 is vacuum dielectric constant, A is the area of the plates (2.12 mm2 in this case), and d is the spacing between the two plates. It could be calculated that the relative dielectric constant of the STO film prepared in this paper is 213.4. This electrical test results are obtained at a temperature of 300 K. In order to meet the requirement of the electrode contact in power devices, wet etching experiments are performed on the 400-nmthick STO film. The Si wafers with the STO film are ultrasonically cleaned in acetone, alcohol and deionized water in turn. The etching solution is prepared by mixing HNO3, BHF solution and H2O in a volume ratio of 1 : 2: 5. The BHF solution is composed of 50% HF solution and 40% NH4F solution in a volume ratio of 1 : 5. Then, the photoresist is spin-coated on the film as a barrier layer. A sawtooth pattern mask with a feature size of 2 μm is used to expose and develop the photoresist. Finally, the STO film is etched by the etching solution in a 50 � C water bath for 12 s. Fig. 7 is the surface optical image of the etched film, and this clear profile indicates that the STO film could be successfully etched with 2-μm -feature, which is enough for electrode contact in power devices.
Fig. 1. Schematic of multi-station RF magnetron sputtering system. 169
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Fig. 2. Surface morphology of the STO film samples of different thickness: (a) 300 nm (b) 400 nm (c) 500 nm (d) 600 nm.
Fig. 3. XRD pattern of the 400-nm-thick STO film on Si substrate annealed at 700 � C.
Fig. 4. Cross-section of the STO film on Pt layer, carried out by SEM.
3. Application 3.1. HK-OPTVLD The OPTVLD (optimized variational doping) technology [16], as shown in Fig. 8(a), has been widely used in the lateral power semiconductor devices. In this technology, by introducing additional charges into the surface of the drift region, the device could sustain the BV as high as possible within a shortest width. These additional charges are realized by the optimized P-VLD (P-type variational doping) layer, which is usually one-time implanted through the finger strip mask [17]. Although the cost could be reduced by this implanting method, the actual dose of the P-VLD layer would be serious uneven on the surface of the device. Based on this, an extremely high-precision process is needed to limit the dose deviation. In our study, the process window of the device with OPTVLD could be expanded by the proposed STO film. The structure of OPTVLD with the proposed STO film (HK-OPTVLD) is shown in Fig. 8(b). The numerical simulation in MEDICI 170
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Fig. 5. Structure of the STO film capacitor.
Fig. 6. Capacitance at different applied electric field changing frequencies.
Fig. 7. Optical microscope image of the etched 400-nm-thick STO film.
software is performed to verify the advantage of HK-OPTVLD. Physical models for simulation include concentration and temperature dependent mobility model, mobility model using perpendicular and parallel electric field component, the Shockley-Read-Hall recombination model, the impact ionization model and Auger recombination model. Both the previous OPTVLD and HK-OPTVLD achieve the same BV of 680 V at room temperature (300 K). Based on the experimental results of the film, the relative dielectric constant of STO is set to 213, and the film thickness is under 400 nm. The main design parameters of the devices are shown in Table 1. Fig. 9 shows the variation of BV with the dose deviation of P-VLD. The distinguished curves indicate that the STO film could 171
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Fig. 8. Device structures of (a) the previous OPTVLD and (b) the proposed HK-OPTVLD. Table 1 Key parameters. Parameters
OPTVLD
OPTVLD LDMOS
Thickness of STO film (nm) Relative dielectric permittivity Length of drift region (μm) P-VLD P1 dose (cm 2) P-VLD P2 dose (cm 2) P-VLD P3 dose (cm 2) P-VLD P4 dose (cm 2) P-VLD P5 dose (cm 2) N substrate doping density (cm 3) P-well dose (cm 2) N-well dose (cm 2) P-top dose (cm 2) Pþ doping density (cm 3) Nþ doping density (cm 3)
0/200/300/400 213 130 2.0e16 1.9e16 1.8e16 / / 2.5e14 / / / 6e19 6e19
0/400 213 40 4.0e12 3.6e12 3.2e12 1.1e12 3.0e12 7.0e14 2.5e12 3.5e12 3.4e12 6e19 6e19
Fig. 9. Influence of P-VLD dose deviation on BV of the device (a) T ¼ 300 K (b) T ¼ 473 K.
effectively resist the influence from the dose deviation of P-VLD. The thicker the STO film, the better this effect. When the temperature is 300 K, to ensure that the previous OPTVLD has 90% of the maximum BV (0.9 BVmax) at least, the acceptable range of the P-VLD dose deviation is 14%, and that of HK-OPTVLD could be improved to 37%. When the temperature rises to 473 K, these two ranges of OPTVLD and HK-OPTVLD are 16% and 42%, respectively. The results show that the STO film could expand the process window of PVLD dose by more than 2.6 times. Considering the dielectric constant of the STO film may deviate with different deposition methods, film thicknesses and application temperatures [12,14,15], Fig. 10 shows the different improvement of HK-OPTVLD when the relative dielectric constant varies from 100 to 500. It indicates that the film with a larger dielectric constant could expand the process window more, and then the HK-OPTVLD get better improvement. 3.2. HK-OPTVLD LDMOS As shown in Fig. 11, the dual-channel conductive OPTVLD LDMOS [18] could also be improved by the STO film. The buried P-VLD layer and N-well are fabricated in the early stage of the whole process, and a lot of subsequent high-temperature diffusion time is 172
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Fig. 10. The different improvement when the dielectric constant of the HK film varies from 100 to 500.
Fig. 11. Device structures of (a) the previous OPTVLD and (b) the proposed HK-OPTVLD.
followed. Compared to the surface P-VLD in Sample 1, the actual dose of the buried P-VLD layer and N-well may be more difficult to control. As a consequence, the deviation may be greater and the impact on BV may be more serious. The main design parameters of the device are shown in Table 1. Both the previous and the improved OPTVLD LDMOS have the same BV of 300 V. Fig. 12(a) shows the variation of BV with the dose deviation of the buried P-VLD layer. Likewise, to ensure that the device has 0.9 BVmax at least, the process window of the previous structure is 11%, and that of HK-OPTVLD LDMOS could be improved to 20%. The result shows that the improved OPTVLD LDMOS could nearly double the process window of the buried P-VLD dose. Considering that the dose of N-well may also deviate simultaneously, there are two extremes in the device. The first is that the PVLD dose is too large when the N-well dose is too small, and the second is that the P-VLD dose is too small when the N-well dose is too large. After the impurity compensation, these two situations lead to more serious dose deviation. Fig. 12(b) shows the performance of BV in these two cases. It could be concluded that the previous structure is more seriously affected, and the STO film could effectively improve this performance. Another application of STO could be in the vertical double-diffused metal oxide semiconductor (VDMOS). By implementing interdigitated HK insulators in the drift region, the trade-off relationship between BV and specific on-resistance could be improved,
Fig. 12. BV curves of the device when (a) only the P-VLD dose deviates and (b) both N-well and P-VLD dose deviate. 173
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which even closes to that of the super-junction VDMOS (SJ-VDMOS) and breaks the well-known “Silicon limit” [19]. Although the STO process in our study cannot fill the deep trench yet, the test results could provide a reference to realize this high-performance device. 4. Conclusion According to the research in this paper, the properties of STO meet the requirements of power semiconductor devices with HK insulators. The 400-nm-thick STO film without cracks is successfully deposited on the silicon surface. The test result shows that the film has a stable dielectric constant of more than 200 at a frequency up to 200 kHz. The film could be etched with 2-μm-feature, which is enough for electrode contact in power devices. By taking the measurement results into the simulation, it is verified that the device with OPTVLD could be improved by the STO film. The process window of impurity dose could be expanded by more than twice, and this could effectively develop the yield rate and the reliability of the product. We also find that the STO film with a larger dielectric constant could bring better improvement. Moreover, this work could provide a reference for material selection of HK insulators in power devices. Acknowledgements The authors would like to thank Dr. J. Deng, Dr. H. Li, Prof. J. H. Zhang, Prof. H. W. Chen and Mr. Y. Zheng for their help in the experimental part of this paper. This work was supported in part by the Youth Fund of Natural Science Foundation of China under Grant 61604030and Grant 51607026. References [1] X.B. Chen, Super-junction Voltage Sustaining Layer with Alternating Semiconductor and High-K Dielectric Regions, 2002. [2] X.B. Chen, Lateral High-Voltage Semiconductor Devices with Surface Covered by Thin Film of Dielectric Material with High Permittivity, 2003. [3] J. Deng, M.H. Huang, J.J. Cheng, X.J. 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