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Submicron-meter polycrystalline-SiGe thin-film transistors with tunneling field-effect-transistor structure
Solid-State Electronics 54 (2010) 1686–1689
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Submicron-meter polycrystalline-SiGe thin-film transistors with tunneling field-effect-transistor structure M.H. Juang a,⇑, Y.S. Peng a, J.L. Wang b, D.C. Shye b, C.C. Hwang b, S.L. Jang a a b
Dept. of Electronic Engineering, National Taiwan University of Science and Technology, Kee-Lung Rd., 106 Taipei, Taiwan Dept. of Electronic Engineering, Ming-Chi University of Technology, Tai-Shan, Taipei, Taiwan
a r t i c l e
i n f o
Article history: Received 18 April 2010 Received in revised form 31 July 2010 Accepted 9 August 2010 The review of this paper was arranged by Prof. S. Cristoloveanu Keywords: Polycrystalline-SiGe thin-film transistors Tunneling field-effect-transistor Leakage current
a b s t r a c t Submicron-meter polycrystalline-SiGe thin-film transistor (TFT) device with tunneling field-effect-transistor (TFET) structure has been studied. With scaling the gate length down to 1 lm, the poly-SiGe TFT device with conventional metal–oxide–semiconductor-field-effect-transistor (MOSFET) structure would be considerably degraded, which exhibits an off-state leakage of about 0.4 nA/lm at a drain bias of 3 V. The short-channel effect would tend to cause the source/drain punch-through, and also increase the lateral electric field within the channel region, thus enhancing the carried field emission via trap states. The TFET structure can be employed to alleviate the short-channel effect in poly-SiGe TFT device. As a result, even for a gate length of only 0.5 lm, the resultant poly-SiGe TFT–TFET device can exhibit good electrical characteristics with an off-state leakage smaller than 0.1 pA/lm and an on/off current ratio of about 9 orders at a drain bias of 3.0 V. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction Polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) have been actively studied for its potential using in the static random-access memory and as the integrating peripheral driving circuits in high-resolution active matrix liquid crystal displays (AMLCD) due to their large mobility [1,2]. However, due to the presence of defects in poly-Si TFT, some issues have to be resolved in comparison with the single crystalline transistors. A leakage current is increased with the increase of gate and drain voltage due to the field emission via trap states (defects) in the depletion region near the drain [3–6]. TFTs with lower on/off current ratio used as pixel switching in AMLCD represent a limiting factor, which degrades the performance of the display. Various device drain structures were employed to effectively decrease the leakage current and the kink current in polysilicon TFTs, via the reduction of electric field intensity near the drain region [7–10]. However, as TFT devices are scaled down to the 1-lm regime, short-channel effects may further degrade the electrical characteristics of poly-Si TFT device. Previously, the band-to-band tunneling field-effect transistor (TFET) has been designed, which consists of n+ drain region, p channel region, p+ source region [11–14]. The conduction current is contributed from the electron–hole pairs generated by band-to-band tunneling near the p+ source side, which is associated with the electric field and the ⇑ Corresponding author. Fax: +886 2 27376424. E-mail address: [email protected] (M.H. Juang). 0038-1101/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2010.08.009
energy bandgap. In the off-state situation, the TFET device would work as a reverse-biased junction diode. Hence, the TFET devices do not suffer from the serious source/drain punch-through. However, for the negative gate bias voltages, the TFET device would show leakage current that is induced by the carrier band-to-band tunneling that occurs near the n+ drain side. In addition, since SiGe has a smaller bandgap than Si, the resultant band-to-band tunneling would be more obvious for the same drain and gate bias voltages. Hence, for the TFET device structure, SiGe channel layer may be employed to facilitate the band-to-band tunneling. In this study, for a gate length shorter than 1 lm, the poly-SiGe TFT devices with TFET structure have been proposed to result in much better electrical characteristics than the conventional polySi TFT devices with typical MOSFET structure. 2. Device scheme A 100 nm-thick amorphous silicon (a-SiGe) film was firstly deposited on standard glass substrate by low-pressure-chemicalvapor-deposition at 500 °C. A larger Ge mole fraction may lead to a smaller energy bandgap of SiGe channel region, which is supposed to cause a larger band-to-band tunneling current and thus a larger on-state current at the same bias voltage. However, the off-state leakage current would also be degraded with increasing the Ge mole fraction, due to the enhanced band-to-band tunneling and also the carrier field emission. In addition, a larger Ge mole fraction may adversely affect the interface between gate oxide (SiO2) and SiGe channel. Hence, the Ge mole fraction of about 0.3
M.H. Juang et al. / Solid-State Electronics 54 (2010) 1686–1689
is employed in the above SiGe layer, which may be an available choice while considering the electrical performance of this polySiGe TFT–TFET device. Then, the a-SiGe thin film was crystallized by 308 nm XeCl excimer-laser annealing. After defining the active device layer, a 40 nm-thick tetra-ethyl-ortho-silane (TEOS) gate oxide was deposited by plasma-enhanced-chemical-vapor-deposition (PECVD) at 400 °C, as a gate dielectric. A phosphorus-doped n+-poly-Si film of 300 nm thicknesses was then deposited, and delineated as gate electrode of 1000 lm channel width and various channel length. Subsequently, part of the samples was implanted with phosphorus 100 keV to a dose of 4 1015 cm2 to form the n+ source/drain (S/D) region, namely the poly-SiGe TFT device with conventional MOSFET structure. The implanted dopant impurities were activated by furnace annealing at 600 °C for 90 min. Fig. 1a schematically illustrates the resultant structure of the poly-SiGe TFT device with conventional MOSFET structure. On the other hand, using corresponding photo-mask steps, part of the post-gate-defined samples was selectively implanted with As+(10-keV, 4 1015-cm2) to form the n+ drain region on one side 15 of gate, and then selectively implanted with BFþ 2 (10-keV, 3 10 cm2) to form the p+ source region on the other side of gate. Fig. 1b schematically illustrates the resultant structure of the poly-SiGe TFT device with TFET structure. Then, an 800 nm-thick TEOS oxide was deposited by PECVD as a passivation layer. Contact holes were formed, and a 1200 nm-thick Al film was subsequently deposited and patterned. Finally, all the samples were sintered at 300 °C for 45 min in a forming gas ambient. All the resultant devices were electrically measured at different gate and drain voltages, with the source region being grounded. Hence, the applied drain and gate bias voltages are defined as the Vds and Vgs values, correspondingly. 3. Results and discussion Fig. 2 shows the drain currents at a drain voltage of 3 V as a function of gate voltage for the poly-SiGe TFT devices with conventional MOSFET structure and TFET structure, respectively, for a gate length of 5 lm. As for a gate length of 5 lm, the poly-SiGe TFT– MOSFET device exhibits a low off-state leakage of about 1 pA/ lm. However, the poly-SiGe TFT–TFET device can even significantly cause an off-state leakage smaller than 0.01 pA/lm. By further reducing the gate length to be as short as 1 lm, the poly-SiGe TFT–MOSFET device would exhibit a large off-state
Fig. 1. Schematic structures of poly-SiGe TFT devices with: (a) conventional MOSFET and (b) TFET structures.
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Fig. 2. The drain current at Vds of 3 V as a function of gate voltage for the poly-SiGe TFT devices with conventional MOSFET structure and TFET structure, respectively, for a channel length of 5 lm.
leakage. Fig. 3 shows the drain current at a drain voltage of 3 V as a function of gate voltage for the poly-SiGe TFT device with conventional MOSFET structure and TFET structure, respectively, for a gate length of 1 lm. The MOSFET structure causes an off-state leakage of about 0.4 nA/lm. As for the MOSFET structure, the short-channel effect can tend to cause the source/drain punchthrough, and also enhance the lateral electric field within the channel region. Hence, for the poly-SiGe TFT–MOSFET devices, the carried field emission via trap states may be further enhanced. As a result, for poly-SiGe TFT–MOSFET devices with a gate length as short as 1 lm, a considerably large leakage current may be caused. Hence, the usage of conventional MOSFET structure may severely limit the scaling down of poly-SiGe TFT devices. On the other hand, because of the reversibly biased pn junction structure, the TFET device would not suffer from source/drain punch-through. Even though the channel length is scaled down to 1 lm, the poly-SiGe TFT–TFET device can still lead to an off-state leakage significantly smaller than 0.1 pA/lm, which also yields an on/off current ratio
Fig. 3. The drain current at Vds of 3 V as a function of gate voltage for the poly-SiGe TFT devices with conventional MOSFET structure and TFET structure, respectively, for a channel length of 1 lm.
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larger than 9 orders. As a result, for a channel length as short as 1 lm, by using this TFET scheme, the large leakage current caused by the conventional poly-SiGe TFT–MOSFET devices may be significantly suppressed due to alleviation of the short-channel effect. Furthermore, Fig. 4a and b schematically illustrates the energy band diagrams for the SiGe TFET device biased at gate voltages of 0 and 10 V, correspondingly, for a gate length of 1 lm and a drain bias of 3.0 V. When the gate voltage of 10 V is applied to the device, the energy band of the channel region near the source region is considerably narrowed, thus facilitating the band-to-band tunneling, namely the on-state. However, when a gate bias of 0 V is applied, much less bending of the energy band is found over the channel region. Accordingly, the band-to-band tunneling current may be greatly alleviated, and thus a low off-state current can be achieved. By further scaling down the gate length to be 0.5 lm, even at a small drain bias of 1.5 V, the poly-SiGe TFT–MOSFET device causes a large off-state leakage of about 0.2 nA/lm. Fig. 5 shows the drain current at a drain bias of 1.5 V as a function of gate voltage for the poly-SiGe TFT device with MOSFET structure and TFET structure, respectively, for a gate length of 0.5 lm. For the TFET structure, it is found that an off-state leakage smaller than 0.01 pA/lm can be achieved. As a result, even for a gate length of only 0.5 lm, the resultant poly-SiGe TFT–TFET device can still exhibit good electrical characteristics, which shows good availability for imple-
Fig. 4. The schematic energy band diagrams for a 1-lm SiGe TFET device biased at gate voltages of: (a) 0 V and (b) 10 V, correspondingly, and at a drain voltage of 3 V.
Fig. 5. The drain current at Vds of 1.5 V as a function of gate voltage for the polySiGe TFT devices with conventional MOSFET structure and TFET structure, respectively, for a channel length of 0.5 lm.
menting high packing density of poly-SiGe TFT devices. The TFET structure is not symmetry, thus being not available for switching devices of bi-directional conduction. However, the highly scalable poly-SiGe TFT devices with TFET structure would be feasible for peripheral logic circuits such as inverter. With increasing the drain bias to 3 V, the poly-SiGe TFT device with TFET structure can still show good characteristics. Fig. 6 shows the drain current at a drain bias of 3 V as a function of gate voltage for the poly-SiGe TFT device with MOSFET structure and TFET structure, respectively, for a gate length of 0.5 lm. For the 0.5-lm polySiGe TFT device at a drain bias of 3 V, the MOSFET structure causes a large off-state leakage of about 4 nA/lm, but the TFET structure can still result in an off-state leakage smaller than 0.1 pA/lm. By this TFET scheme, an on/off current ratio of about 9 orders may still be achieved. Furthermore, from the above results, for the poly-SiGe TFT–MOSFET devices at a drain bias of 3 V, the subthreshold swing is increased with reducing the gate length, with the values being about 0.52, 0.45, and 0.42 V/decade for the gate length of 0.5, 1, and 5 lm, corresponding. However, for the poly-SiGe TFT–TFET devices at a drain bias of 3 V, the resultant subthreshold swing is not
Fig. 6. The drain current at Vds of 3 V as a function of gate voltage for the poly-SiGe TFT device with conventional MOSFET structure and TFET structure, respectively, for a channel length of 0.5 lm.
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device with a gate length of 5 lm, the off-state leakage would be only about 2 pA/lm at a drain bias of 3 V. However, with scaling the gate length down to 1 lm, the poly-SiGe TFT–MOSFET device would be considerably degraded, which exhibits a large off-state leakage of about 0.4 nA/lm at a drain bias of 3 V. The short-channel effect would tend to cause the source/drain punch-through and also increase the lateral electric field within the channel region, thus enhancing the carried field emission via trap states. The TFET structure can be employed to alleviate the short-channel effect. As a result, even for a gate length of 1 lm, the resultant poly-SiGe TFT–TFET device can significantly exhibit an off-state leakage smaller than 0.1 pA/lm and an on/off current ratio larger than 9 orders at a drain bias of 3 V. Furthermore, even for a gate length of only 0.5 lm, the resultant poly-SiGe TFT–TFET device can still exhibit good electrical characteristics with an off-state leakage smaller than 0.1 pA/lm and an on/off current ratio of about 9 order at a drain bias of 3 V, which shows good feasibility for implementing high packing density of poly-SiGe TFT devices. Fig. 7. The drain current as a function of drain voltage for the poly-SiGe TFT device with TFET structure biased at gate voltages of 3 and 4 V, respectively, for a channel length of 0.5 lm.
degraded with reducing the gate length, with the value being about 0.54 V/decade. In addition, for the 0.5 lm TFT–MOSFET devices, the subthreshold swing is improved from about 0.52 to 0.47 V/decade as the drain bias is reduced from 3 V to 1.5 V. The above results reflects that short-channel effects is obvious for the MOSFET structure, but is suppressed for the TFET structure. Moreover, for the 0.5 lm poly-SiGe TFT devices, the resultant threshold voltages are estimated to be about 0.2 and 4 V for the MOSFET and the TFET structures, correspondingly, with a comparable carrier mobility of about 180 cm2 V1 s1. In addition, Fig. 7 shows the drain current at a drain bias of 3 V as a function of drain voltage for the poly-SiGe TFT–TFET device biased at gate voltages of 3 and 4 V, respectively, for a gate length of 0.5 lm. The poly-SiGe TFT–TFET device can lead to an on-state current of the order of 1 lA/lm at such gate and drain bias voltages, which shows feasibility for providing sufficient driving current in circuit applications. 4. Conclusions Formation of submicron-meter poly-SiGe TFT devices with TFET structure has been studied. For a long channel poly-SiGe MOSFET
Acknowledgement This worked is supported in part by the National Science Council (NSC), Taiwan, under the Contract No. NSC 97-2221-E-011-136. References [1] Hayashi F, Ohkubo H, Takahashi T, Horiba S, Noda K, Uchida T, et al. Int Electron Dev Meet Tech Dig; 1996. p. 283. [2] Oshima H, Morozumi S. Int Electron Dev Meet Tech Dig; 1989. p. 157. [3] Colalongo L, Valdinoci M, Baccarani G, Migliorato P, Tallarida G, Reita C. Solid State Electron 1997;41:626. [4] Wu IW, Lewis AG, Huang TY, Jackson WB, Chiang A. Int Electron Dev Meet Tech Dig; 1990. p. 867. [5] Lack M, Wu IW, King TJ, Lewis AG. Int Electron Dev Meet Tech Dig; 1993. p. 385. [6] Yazaki M, Takenake S, Ohshima H. Jpn J Appl Phys 1992;31:206. [7] Hatano M, Akimoto H, Sakai T. Int Electron Dev Meet Tech Dig; 1997. p. 523. [8] Min BH, Kanicki J. IEEE Electron Dev Lett 1999;20:335. [9] Juang MH, Huang CW, Wu ML, Hwang CC, Wang JL, Shye DC, et al. Microelectron Eng 2010;87:620. [10] Juang MH, Chang CW, Wang JL, Shye DC, Hwang CC, Jang SL. Solid State Electron 2010;54:516. [11] Nirschl T, Henzler S, Fischer J, Fulde M, et al. Solid State Electron 2006;50:44. [12] Baba T. Jpn J Appl Phys 1992;31:455. [13] Reddick WM, Amaratunga GAJ. Appl Phys Lett 1995;67:494. [14] Takeda E, Matsuoka H, Igura Y, Asai S. Int Electron Dev Meet Tech Dig; 1988. p. 402.
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Submicron-meter polycrystalline-SiGe thin-film transistors with tunneling field-effect-transistor structure M.H. Juang a,⇑, Y.S. Peng a, J.L. Wang b, D.C. Shye b, C.C. Hwang b, S.L. Jang a a b
Dept. of Electronic Engineering, National Taiwan University of Science and Technology, Kee-Lung Rd., 106 Taipei, Taiwan Dept. of Electronic Engineering, Ming-Chi University of Technology, Tai-Shan, Taipei, Taiwan
a r t i c l e
i n f o
Article history: Received 18 April 2010 Received in revised form 31 July 2010 Accepted 9 August 2010 The review of this paper was arranged by Prof. S. Cristoloveanu Keywords: Polycrystalline-SiGe thin-film transistors Tunneling field-effect-transistor Leakage current
a b s t r a c t Submicron-meter polycrystalline-SiGe thin-film transistor (TFT) device with tunneling field-effect-transistor (TFET) structure has been studied. With scaling the gate length down to 1 lm, the poly-SiGe TFT device with conventional metal–oxide–semiconductor-field-effect-transistor (MOSFET) structure would be considerably degraded, which exhibits an off-state leakage of about 0.4 nA/lm at a drain bias of 3 V. The short-channel effect would tend to cause the source/drain punch-through, and also increase the lateral electric field within the channel region, thus enhancing the carried field emission via trap states. The TFET structure can be employed to alleviate the short-channel effect in poly-SiGe TFT device. As a result, even for a gate length of only 0.5 lm, the resultant poly-SiGe TFT–TFET device can exhibit good electrical characteristics with an off-state leakage smaller than 0.1 pA/lm and an on/off current ratio of about 9 orders at a drain bias of 3.0 V. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction Polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) have been actively studied for its potential using in the static random-access memory and as the integrating peripheral driving circuits in high-resolution active matrix liquid crystal displays (AMLCD) due to their large mobility [1,2]. However, due to the presence of defects in poly-Si TFT, some issues have to be resolved in comparison with the single crystalline transistors. A leakage current is increased with the increase of gate and drain voltage due to the field emission via trap states (defects) in the depletion region near the drain [3–6]. TFTs with lower on/off current ratio used as pixel switching in AMLCD represent a limiting factor, which degrades the performance of the display. Various device drain structures were employed to effectively decrease the leakage current and the kink current in polysilicon TFTs, via the reduction of electric field intensity near the drain region [7–10]. However, as TFT devices are scaled down to the 1-lm regime, short-channel effects may further degrade the electrical characteristics of poly-Si TFT device. Previously, the band-to-band tunneling field-effect transistor (TFET) has been designed, which consists of n+ drain region, p channel region, p+ source region [11–14]. The conduction current is contributed from the electron–hole pairs generated by band-to-band tunneling near the p+ source side, which is associated with the electric field and the ⇑ Corresponding author. Fax: +886 2 27376424. E-mail address: [email protected] (M.H. Juang). 0038-1101/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2010.08.009
energy bandgap. In the off-state situation, the TFET device would work as a reverse-biased junction diode. Hence, the TFET devices do not suffer from the serious source/drain punch-through. However, for the negative gate bias voltages, the TFET device would show leakage current that is induced by the carrier band-to-band tunneling that occurs near the n+ drain side. In addition, since SiGe has a smaller bandgap than Si, the resultant band-to-band tunneling would be more obvious for the same drain and gate bias voltages. Hence, for the TFET device structure, SiGe channel layer may be employed to facilitate the band-to-band tunneling. In this study, for a gate length shorter than 1 lm, the poly-SiGe TFT devices with TFET structure have been proposed to result in much better electrical characteristics than the conventional polySi TFT devices with typical MOSFET structure. 2. Device scheme A 100 nm-thick amorphous silicon (a-SiGe) film was firstly deposited on standard glass substrate by low-pressure-chemicalvapor-deposition at 500 °C. A larger Ge mole fraction may lead to a smaller energy bandgap of SiGe channel region, which is supposed to cause a larger band-to-band tunneling current and thus a larger on-state current at the same bias voltage. However, the off-state leakage current would also be degraded with increasing the Ge mole fraction, due to the enhanced band-to-band tunneling and also the carrier field emission. In addition, a larger Ge mole fraction may adversely affect the interface between gate oxide (SiO2) and SiGe channel. Hence, the Ge mole fraction of about 0.3
M.H. Juang et al. / Solid-State Electronics 54 (2010) 1686–1689
is employed in the above SiGe layer, which may be an available choice while considering the electrical performance of this polySiGe TFT–TFET device. Then, the a-SiGe thin film was crystallized by 308 nm XeCl excimer-laser annealing. After defining the active device layer, a 40 nm-thick tetra-ethyl-ortho-silane (TEOS) gate oxide was deposited by plasma-enhanced-chemical-vapor-deposition (PECVD) at 400 °C, as a gate dielectric. A phosphorus-doped n+-poly-Si film of 300 nm thicknesses was then deposited, and delineated as gate electrode of 1000 lm channel width and various channel length. Subsequently, part of the samples was implanted with phosphorus 100 keV to a dose of 4 1015 cm2 to form the n+ source/drain (S/D) region, namely the poly-SiGe TFT device with conventional MOSFET structure. The implanted dopant impurities were activated by furnace annealing at 600 °C for 90 min. Fig. 1a schematically illustrates the resultant structure of the poly-SiGe TFT device with conventional MOSFET structure. On the other hand, using corresponding photo-mask steps, part of the post-gate-defined samples was selectively implanted with As+(10-keV, 4 1015-cm2) to form the n+ drain region on one side 15 of gate, and then selectively implanted with BFþ 2 (10-keV, 3 10 cm2) to form the p+ source region on the other side of gate. Fig. 1b schematically illustrates the resultant structure of the poly-SiGe TFT device with TFET structure. Then, an 800 nm-thick TEOS oxide was deposited by PECVD as a passivation layer. Contact holes were formed, and a 1200 nm-thick Al film was subsequently deposited and patterned. Finally, all the samples were sintered at 300 °C for 45 min in a forming gas ambient. All the resultant devices were electrically measured at different gate and drain voltages, with the source region being grounded. Hence, the applied drain and gate bias voltages are defined as the Vds and Vgs values, correspondingly. 3. Results and discussion Fig. 2 shows the drain currents at a drain voltage of 3 V as a function of gate voltage for the poly-SiGe TFT devices with conventional MOSFET structure and TFET structure, respectively, for a gate length of 5 lm. As for a gate length of 5 lm, the poly-SiGe TFT– MOSFET device exhibits a low off-state leakage of about 1 pA/ lm. However, the poly-SiGe TFT–TFET device can even significantly cause an off-state leakage smaller than 0.01 pA/lm. By further reducing the gate length to be as short as 1 lm, the poly-SiGe TFT–MOSFET device would exhibit a large off-state
Fig. 1. Schematic structures of poly-SiGe TFT devices with: (a) conventional MOSFET and (b) TFET structures.
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Fig. 2. The drain current at Vds of 3 V as a function of gate voltage for the poly-SiGe TFT devices with conventional MOSFET structure and TFET structure, respectively, for a channel length of 5 lm.
leakage. Fig. 3 shows the drain current at a drain voltage of 3 V as a function of gate voltage for the poly-SiGe TFT device with conventional MOSFET structure and TFET structure, respectively, for a gate length of 1 lm. The MOSFET structure causes an off-state leakage of about 0.4 nA/lm. As for the MOSFET structure, the short-channel effect can tend to cause the source/drain punchthrough, and also enhance the lateral electric field within the channel region. Hence, for the poly-SiGe TFT–MOSFET devices, the carried field emission via trap states may be further enhanced. As a result, for poly-SiGe TFT–MOSFET devices with a gate length as short as 1 lm, a considerably large leakage current may be caused. Hence, the usage of conventional MOSFET structure may severely limit the scaling down of poly-SiGe TFT devices. On the other hand, because of the reversibly biased pn junction structure, the TFET device would not suffer from source/drain punch-through. Even though the channel length is scaled down to 1 lm, the poly-SiGe TFT–TFET device can still lead to an off-state leakage significantly smaller than 0.1 pA/lm, which also yields an on/off current ratio
Fig. 3. The drain current at Vds of 3 V as a function of gate voltage for the poly-SiGe TFT devices with conventional MOSFET structure and TFET structure, respectively, for a channel length of 1 lm.
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larger than 9 orders. As a result, for a channel length as short as 1 lm, by using this TFET scheme, the large leakage current caused by the conventional poly-SiGe TFT–MOSFET devices may be significantly suppressed due to alleviation of the short-channel effect. Furthermore, Fig. 4a and b schematically illustrates the energy band diagrams for the SiGe TFET device biased at gate voltages of 0 and 10 V, correspondingly, for a gate length of 1 lm and a drain bias of 3.0 V. When the gate voltage of 10 V is applied to the device, the energy band of the channel region near the source region is considerably narrowed, thus facilitating the band-to-band tunneling, namely the on-state. However, when a gate bias of 0 V is applied, much less bending of the energy band is found over the channel region. Accordingly, the band-to-band tunneling current may be greatly alleviated, and thus a low off-state current can be achieved. By further scaling down the gate length to be 0.5 lm, even at a small drain bias of 1.5 V, the poly-SiGe TFT–MOSFET device causes a large off-state leakage of about 0.2 nA/lm. Fig. 5 shows the drain current at a drain bias of 1.5 V as a function of gate voltage for the poly-SiGe TFT device with MOSFET structure and TFET structure, respectively, for a gate length of 0.5 lm. For the TFET structure, it is found that an off-state leakage smaller than 0.01 pA/lm can be achieved. As a result, even for a gate length of only 0.5 lm, the resultant poly-SiGe TFT–TFET device can still exhibit good electrical characteristics, which shows good availability for imple-
Fig. 4. The schematic energy band diagrams for a 1-lm SiGe TFET device biased at gate voltages of: (a) 0 V and (b) 10 V, correspondingly, and at a drain voltage of 3 V.
Fig. 5. The drain current at Vds of 1.5 V as a function of gate voltage for the polySiGe TFT devices with conventional MOSFET structure and TFET structure, respectively, for a channel length of 0.5 lm.
menting high packing density of poly-SiGe TFT devices. The TFET structure is not symmetry, thus being not available for switching devices of bi-directional conduction. However, the highly scalable poly-SiGe TFT devices with TFET structure would be feasible for peripheral logic circuits such as inverter. With increasing the drain bias to 3 V, the poly-SiGe TFT device with TFET structure can still show good characteristics. Fig. 6 shows the drain current at a drain bias of 3 V as a function of gate voltage for the poly-SiGe TFT device with MOSFET structure and TFET structure, respectively, for a gate length of 0.5 lm. For the 0.5-lm polySiGe TFT device at a drain bias of 3 V, the MOSFET structure causes a large off-state leakage of about 4 nA/lm, but the TFET structure can still result in an off-state leakage smaller than 0.1 pA/lm. By this TFET scheme, an on/off current ratio of about 9 orders may still be achieved. Furthermore, from the above results, for the poly-SiGe TFT–MOSFET devices at a drain bias of 3 V, the subthreshold swing is increased with reducing the gate length, with the values being about 0.52, 0.45, and 0.42 V/decade for the gate length of 0.5, 1, and 5 lm, corresponding. However, for the poly-SiGe TFT–TFET devices at a drain bias of 3 V, the resultant subthreshold swing is not
Fig. 6. The drain current at Vds of 3 V as a function of gate voltage for the poly-SiGe TFT device with conventional MOSFET structure and TFET structure, respectively, for a channel length of 0.5 lm.
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device with a gate length of 5 lm, the off-state leakage would be only about 2 pA/lm at a drain bias of 3 V. However, with scaling the gate length down to 1 lm, the poly-SiGe TFT–MOSFET device would be considerably degraded, which exhibits a large off-state leakage of about 0.4 nA/lm at a drain bias of 3 V. The short-channel effect would tend to cause the source/drain punch-through and also increase the lateral electric field within the channel region, thus enhancing the carried field emission via trap states. The TFET structure can be employed to alleviate the short-channel effect. As a result, even for a gate length of 1 lm, the resultant poly-SiGe TFT–TFET device can significantly exhibit an off-state leakage smaller than 0.1 pA/lm and an on/off current ratio larger than 9 orders at a drain bias of 3 V. Furthermore, even for a gate length of only 0.5 lm, the resultant poly-SiGe TFT–TFET device can still exhibit good electrical characteristics with an off-state leakage smaller than 0.1 pA/lm and an on/off current ratio of about 9 order at a drain bias of 3 V, which shows good feasibility for implementing high packing density of poly-SiGe TFT devices. Fig. 7. The drain current as a function of drain voltage for the poly-SiGe TFT device with TFET structure biased at gate voltages of 3 and 4 V, respectively, for a channel length of 0.5 lm.
degraded with reducing the gate length, with the value being about 0.54 V/decade. In addition, for the 0.5 lm TFT–MOSFET devices, the subthreshold swing is improved from about 0.52 to 0.47 V/decade as the drain bias is reduced from 3 V to 1.5 V. The above results reflects that short-channel effects is obvious for the MOSFET structure, but is suppressed for the TFET structure. Moreover, for the 0.5 lm poly-SiGe TFT devices, the resultant threshold voltages are estimated to be about 0.2 and 4 V for the MOSFET and the TFET structures, correspondingly, with a comparable carrier mobility of about 180 cm2 V1 s1. In addition, Fig. 7 shows the drain current at a drain bias of 3 V as a function of drain voltage for the poly-SiGe TFT–TFET device biased at gate voltages of 3 and 4 V, respectively, for a gate length of 0.5 lm. The poly-SiGe TFT–TFET device can lead to an on-state current of the order of 1 lA/lm at such gate and drain bias voltages, which shows feasibility for providing sufficient driving current in circuit applications. 4. Conclusions Formation of submicron-meter poly-SiGe TFT devices with TFET structure has been studied. For a long channel poly-SiGe MOSFET
Acknowledgement This worked is supported in part by the National Science Council (NSC), Taiwan, under the Contract No. NSC 97-2221-E-011-136. References [1] Hayashi F, Ohkubo H, Takahashi T, Horiba S, Noda K, Uchida T, et al. Int Electron Dev Meet Tech Dig; 1996. p. 283. [2] Oshima H, Morozumi S. Int Electron Dev Meet Tech Dig; 1989. p. 157. [3] Colalongo L, Valdinoci M, Baccarani G, Migliorato P, Tallarida G, Reita C. Solid State Electron 1997;41:626. [4] Wu IW, Lewis AG, Huang TY, Jackson WB, Chiang A. Int Electron Dev Meet Tech Dig; 1990. p. 867. [5] Lack M, Wu IW, King TJ, Lewis AG. Int Electron Dev Meet Tech Dig; 1993. p. 385. [6] Yazaki M, Takenake S, Ohshima H. Jpn J Appl Phys 1992;31:206. [7] Hatano M, Akimoto H, Sakai T. Int Electron Dev Meet Tech Dig; 1997. p. 523. [8] Min BH, Kanicki J. IEEE Electron Dev Lett 1999;20:335. [9] Juang MH, Huang CW, Wu ML, Hwang CC, Wang JL, Shye DC, et al. Microelectron Eng 2010;87:620. [10] Juang MH, Chang CW, Wang JL, Shye DC, Hwang CC, Jang SL. Solid State Electron 2010;54:516. [11] Nirschl T, Henzler S, Fischer J, Fulde M, et al. Solid State Electron 2006;50:44. [12] Baba T. Jpn J Appl Phys 1992;31:455. [13] Reddick WM, Amaratunga GAJ. Appl Phys Lett 1995;67:494. [14] Takeda E, Matsuoka H, Igura Y, Asai S. Int Electron Dev Meet Tech Dig; 1988. p. 402.