Superior performance and Hot Carrier reliability of strained FDSOI nMOSFETs for advanced CMOS technology nodes

Solid-State Electronics 113 (2015) 127–131

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Superior performance and Hot Carrier reliability of strained FDSOI nMOSFETs for advanced CMOS technology nodes G. Besnard b,a,c,⇑, X. Garros a, F. Andrieu a, P. Nguyen b, W. Van Den Daele b, P. Reynaud b, W. Schwarzenbach b, D. Delprat b, K.K. Bourdelle b, G. Reimbold a, S. Cristoloveanu c a b c

CEA-LETI, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble, France Soitec, Parc technologique des Fontaines, Bernin, 38926 Crolles, France IMEP-LAHC, Grenoble-INP/MINATEC, 3 parvis Louis Néel, 38016 Grenoble, France

a r t i c l e

i n f o

Article history: Available online 22 June 2015 Keywords: nMOSFET FDSOI Strained silicon sSOI Reliability Hot Carrier

a b s t r a c t The Hot Carrier (HC) reliability of NMOS transistors fabricated on biaxially tensile-strain SOI substrates (sSOI) is compared to that of devices fabricated on standard unstrained SOI substrates. It is shown that sSOI-based devices not only exhibit a 10% higher performance in term of ION/IOFF but also show superior HC reliability at same drive current. This reliability improvement may be explained by a better interface quality for sSOI films. Ó 2015 Published by Elsevier Ltd.

1. Introduction With the approaching end of conventional planar bulk CMOS scaling and the need to continue the roadmap below 20 nm, semiconductor industry is moving to new transistor architectures like FinFETs or FDSOI. Among these emerging technologies, FDSOI is a major option because it combines the simplicity of the planar integration scheme used for Bulk technology with the electrostatic efficiency of FinFET technology. Furthermore, SOI enables an efficient strain engineering of the channel and Source/Drain engineering to boost transistor performance. Particularly, strain SOI (sSOI) is a promising candidate for sub-10 nm nodes since it was demonstrated to significantly improve the drive current of nMOSFETs [1,2]. Nevertheless, this performance booster may affect the Hot Carrier (HC) reliability of the device. Indeed it was shown recently that, in deeply scaled technologies, the degradation due to Hot Carriers generated close to the drain is directly proportional to the drive current flowing through the transistor [3]. Therefore an improvement of the drain current combined to an increase of the lateral electric field in short channel devices might degrade the HC reliability of the strained SOI MOSFET compared to their unstrained SOI counterparts [4–6].

⇑ Corresponding author. http://dx.doi.org/10.1016/j.sse.2015.05.021 0038-1101/Ó 2015 Published by Elsevier Ltd.

In this paper, we investigate the impact of strained Si layer on the performance and the HC reliability of FDSOI transistors. First, we compare the performance of FDSOI devices fabricated on sSOI and SOI substrates. Then HC degradation is thoroughly investigated for both architectures. Drifts of all common MOSFET parameters affected by HC effects are carefully analyzed to identify the defects responsible for HC degradation in both cases i.e. interface states and/or oxide trapping. The change in the material bandgap and properties, induced by the strain technology is used to explain sSOI reliability improvement. Finally, HC lifetime of these two kinds of transistors is evaluated. 2. Technology and devices NMOSFETs were fabricated using a Gate First integration scheme on 300 mm SOI and sSOI substrates. In both cases, the silicon film is 7 nm thick and the buried oxide (BOX) is 145 nm thick. The dielectric stack consists of a thin HfSiON layer capped with a TiN metal gate. The Electrical Oxide Thickness (EOT) of the HK/MG stack is 1.2 nm. The channel length (LG) varies from 100 nm down to 30 nm length. The transistor width (W) is fixed to 10 lm. Both SOI and sSOI substrates were fabricated with Smart Cut™ technology. In the case of sSOI, the strain Si film (sSi) is grown on a relaxed Si0.8Ge0.2 buffer layer before being transferred on a handle substrate. The resulting tensile strain in the sSi film is evaluated to

G. Besnard et al. / Solid-State Electronics 113 (2015) 127–131

3. Tests conditions To evaluate the benefit of sSOI films, electron mobility was extracted on large and long channel transistors (LG = 10 lm, W = 10 lm) using the split CV technique. The standard ID(VG) measurements were performed on transistors with different gate length to evaluate the threshold voltage Vth at constant drain current ID = 107 ⁄ (W/LG) and the ION/IOFF ratio at VDD = 1 V. For Hot Carrier degradation, we used standard JEDEC specifications. Stress and measurement tests were performed at 125 °C unless otherwise specified. NMOSFETs with different LG are stressed at different voltages Vstress from 1.4 to 2 V during 1000 s, in worst case conditions Vstress = VG = VD (Figs. 2 and 3) [7]. Between each stress sequence, we recorded the drifts of the key MOSFET parameters i.e. the threshold voltage Vth, the transconductance peak gmmax in the linear regime (VD,meas = 50 mV) and the saturated drain current IDsat at VD,meas = VDD = 1 V. The corresponding criteria associated to each parameter for a 10 years device lifetime are 50 mV of Vth shift, 10% of gmmax degradation and 10% decrease of IDsat drift respectively. Finally, dedicated fast current measurements, where the whole ID(VG) characteristic is measured in 5 ls, were performed to monitor the degradation and relaxation of the same parameters in order to avoid any recovery effects. 4. Measurement results and discussion 4.1. Performance of SOI and sSOI transistors Fig. 4 shows a comparison of electron mobility in SOI and sSOI nMOSFETs extracted by split CV technique. As expected, strain strongly improves mobility ln in long channel devices in the whole range of vertical effective field. The maximum gain obtained around the mobility peak is remarkable, reaching 77%. The benefit of strain is reduced for short-channel devices as depicted in Fig. 5. This may result from several combined effects as (1) a difference in

1.2

Drain Current ID (mA/µm)

+1.36 GPa. After bonding and transfer, the residual SiGe buffer layer is removed by selective etch. sSOI is a single layered, completely Ge-free ‘‘on insulator’’ substrate (Fig. 1).

1.0 0.8

10

V stress = 1.6V SOI

10

-3

-4

0s

t stress

t stress 0s

0.6

10

0.4

1000s

0.2 0.0 0.0

0.4

10 10

0.8

1000s

-5

-6

VD=1V -7

L = 0.03µm

1.2 0.0 0.4 Gate Voltage VG (V)

0.8

1.2

Fig. 2. Degradation of the ID(VG) characteristic with stress time tstress for the shortest gate length transistor at high stress voltage (linear and logarithmic scale). This measure is used to extract the IDsat degradation required for the HC lifetime extrapolation.

2.0 Transconductance g m (mS/µm)

128

SOI

Vstress = 1.6V

1.6 1.2

t stress 0s

0.8 1000s

VD=1V

0.4

L = 0.03µm

0.0 0.0

0.2

0.4

0.6

0.8

1.0

Gate Voltage VG (V) Fig. 3. Degradation of the transconductance curve with stress time tstress for the shortest gate length NMOS transistor at VD,stress = VG,stress = +1.6 V. These curves are used to extract the g max degradation required for the HC lifetime extrapolation. m

Fig. 1. sSOI substrate fabricated by Smart Cut™. (a) Strain silicon (sSi) film grown on relaxed Si0.8Ge0.2 buffer leading to +1.36 GPa tensile strain. Hydrogen is implanted into SiGe buffer (dotted line) and buried oxide (BOX) is grown on handling substrate. (b) Donor substrate is bonded to handling substrate and separation at implantation depth, leaving the strained silicon layer and (c) etching of residual SiGe layer on final substrate and recycling of donor wafer.

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G. Besnard et al. / Solid-State Electronics 113 (2015) 127–131

600

500

Universal law

L=10µm

-7

Vth@ID=10 .W/L 400

VD=50mV

sSOI 400

+77%

Vth (mV)

Effective Mobility (cm²/Vs)

500

300

300

75mV

200

T=25°C

100

SOI

200

SOI

100

0 0.0

0 0.2

0.4

0.6

0.8

1.0

1.2

40

1.4

Fig. 4. Comparison of the electron mobility in long channel transistors for SOI and sSOI. ln is increased by 77% in sSOI devices and largely exceeds the universal mobility law of unstrained Si channel.

series resistance for SOI and sSOI, (2) a low sensitivity of the drive current to mobility in the saturated regime [8], (3) a possible partial strain relaxation in sSOI. Nevertheless, a +10% gain in drive current is maintained at same IOFF. This higher performance is obtained without any architecture optimization for sSOI devices. In addition to the drive current gain, Fig. 6 shows that sSOI allows a significant Vth reduction of 75 mV, due to strain-induced conduction band splitting [9]. This lower Vth is an interesting option for NMOS threshold voltage adjustment for the 10 nm CMOS node.

10

IOFF (A/µm)

10 10 10 10 10 10

-3 -4 -5 -6

LG=0.03µm LG=0.04µm LG=0.05µm LG=0.1µm

~10%

-7

SOI -8

sSOI

VD = 1V

-9

T=25°C

-10

300

600 900 ION (µA/µm)

1200

Fig. 5. Comparison of ION/IOFF characteristics for SOI and sSOI MOSFET. A 10% gain in the drive current is obtained on short-channel sSOI devices.

100

L = 50nm

NMOS

SOI

2.0V 1.8V

10% 10

50mV

1.6V

1.4V

1 sat

Fig. 7 shows a typical degradation induced by Hot Carriers in unstrained SOI transistors for different Vstress. Similar behavior is observed for sSOI devices. Contrary to BTI stress, not only Vth is degraded but also the transconductance gm and saturated drain current IDsat are reduced. This behavior is consistent with previous results on HC reliability for bulk and FDSOI devices [10,11]. The HC degradation is the sum of two components, (1) carrier trapping in bulk oxide defects and (2) generation of Si/oxide

80

Fig. 6. Threshold voltage Vth for SOI and sSOI for different gate lengths. Short Channel effect is observed for gate length below 100 nm. sSOI devices exhibit a constant 75 mV Vth reduction compared to unstrained SOI devices.

sat

ΔID /ID (0)

4.2. Hot Carrier degradation mechanisms in thin FDSOI films

60

Gate Length L G (nm)

Effective Field (MV/cm)

10

sSOI

NMOS

NMOS

10

1000

ΔVth

Δgm/gm(0)

10

1000

10

1000

Stress Time t stress (s) Fig. 7. Kinetics of SOI device degradation for all 3 parameters DVth, DIDsat, Dgmmax at various stress voltages. Each kinetic curve intercepts the lifetime criterion. Intercepted time values are used to estimate the Time-to-Failure at nominal voltage.

interface states. The predominance of one or the other component depends on the technology node (critical dimensions : LG, tOX) and the associate effective fields (applied voltages : VG, VD) [12]. Fig. 8(a and b) shows the HC degradation of Vth and IDsat measured with our ‘‘recovery free’’ fast measurements system at T = 25 °C [13]. After stress, no recovery of the HC degradation is observed, proving that this aging is permanent. Furthermore, PBTI degradation related to electron trapping in HK defects is negligible compared to HC degradation (Fig. 8c). Both results support the hypothesis that the HC degradation is related to the generation of interface states rather than electron trapping in oxide defects. In sub-100 nm technology nodes, interface states Dit are considered to be significant contributors to the degradation of the MOS parameters [3,12]. Their generation results from the depassivation of interface Si-H bonds close to the drain region. In standard hydrogen release model for HC, where carrier energy is sufficient to directly break the bonds, there is one ‘‘level’’ of bond excitation. This phenomenon is called Single Vibrational Excitation – SVE (Fig. 9a). Here, with an insufficient energy per single carrier, bond breaking/hydrogen release occurs after a total equivalent excitation by multiple carriers (Fig. 9b). Each carrier brings some energy

G. Besnard et al. / Solid-State Electronics 113 (2015) 127–131

(c)

(b)

T=25°C

VG=Vstress VD=Vstress

ΔVth (mV)

100

10

HCI

VG=Vstress VD=0V

L=40nm

10 sat

sat

ΔID /ID

(%)

filled - SOI open - sSOI

1 VG,stress=1.8V VD,stress=1.8V

VG,relax=0V VD,relax=0V

0.1 -6 -4 -2 0 2 -6 -4 -2 0 2 10 10 10 10 10 10 10 10 10 10

tstress (s)

trelax (s)

10 10 10 10 10 10

PBTI

10 -6

-4

-2

0

9

10 years

7 5 3

SOI

sat

(a)

TTF @ ΔVth=50mV (s)

1000

1

30nm 40nm 50nm 100nm

-1 -3 -5

0.8

2

1.2

10 10 10 10 10

1.6

2.0

0.8 1.2 1.6 2.0

Fig. 10. Time-to-Failure of unstrained SOI devices at different stress voltages for (left) a 50 mV Vth shift and (right) a 10% variation on IDsat. Extrapolation of data points leads to the maximum voltage 0.9 V for a 10 years lifetime of SOI devices.

10

10 10

sat

TTF @ ΔID @10% (s)

10 and provides growing bond excitation until it breaks. This mechanism is known as Multi Vibrational Excitation (MVE) [4,12]. As a result, the HC degradation, in deeply scaled technologies, is mainly driven by the flux of ‘‘cold’’ carriers flowing through the channel and no longer by the negligible number of single Hot Carriers. Fig. 10 illustrates the Time-to-Failure (TTF) for Vth and IDsat with respect to Vstress measured on unstrained SOI transistors with different gate lengths. Targeted lifetime at 10 years is nearly achieved with 0.88 V operation, close to VDD specification at 0.9 V for 28/20 nm technology node [14]. We notice that the TTFs at fixed Vstress decrease with transistor scaling. This reduction of TTFs can be explained either by the increase of the lateral field for short channel devices (Vstress/LG) or by the higher saturation current as discussed previously and for same devices. To discriminate these two hypotheses, we have plotted in Fig. 11 the same TTF results as the function of the total injected charge into the drain defined by (1) and the lateral electrical field:

VG=VD=Vstress

Stress Voltage Vstress (V)

tstress (s)

Fig. 8. (a) Vth shift DVth and drive current degradation DIDsat/IDsat (b) after HC stress evaluated with a fast measurement method. SOI and sSOI devices have similar degradation and relaxation. HC degradation is permanent (no relaxation after stress). (c) Comparison between HC induced Vth shift and PBTI degradation. The latter is negligible compared to HC degradation.

TTF @ ΔID @10% (s)

130

10 10 10 10

9

10 years

7

VG=VD=Vstress

5 3

SOI

1

30nm 40nm 50nm 100nm

-1 -3 -5

0

10m 20m D Qinj @t=1s (C)

0.0

0.4

0.8

ELat (MV/cm)

Fig. 11. DIDsat Time-to-Failure w.r.t (left) the drain injected charge at tstress = 1 s and (right) lateral effective field ELat. HC degradation is mainly controlled by the drain current and not by the effective field.

4.3. HC Reliability in SOI and sSOI devices

Q Dinj ¼

Z

t stress

ID ðuÞ du

ð1Þ

0

All the experimental data merge in a single dependence when plotted as a function of Q Dinj . This proves that the degradation is essentially controlled by the current level rather than by the lateral field ELat in the channel. Since the parameters degrade during interface states Dit generation, we conclude it is the number of carriers which increases the chance of H-bond breaking.

Like SOI-based devices, sSOI MOSFETs exhibit a good reliability at 10 years for all three MOS parameters. Fig. 12 shows TTF and current normalization of saturation current IDsat. Maximum voltage is extrapolated at 0.9 V, in line with VDD specifications [14]. Furthermore the same normalization of the data with the injected charge is observed for these sSOI devices. It proves that drive current is the main factor responsible for HC degradation in sSi channels.

Fig. 9. Single Vibrational Excitation (SVE) model (a) of past technologies (>100 nm) vs Multiple Vibrational Excitation (MVE) model (b) in deeply scaled technologies (<100 nm). In a 28 nm technology node, single carrier energy is not sufficient to trigger Hydrogen Release from HC degradation. Hydrogen Release occurs after a total equivalent excitation energy by multiple ‘‘cold’’ carriers which strongly depends on drive current in the channel.

G. Besnard et al. / Solid-State Electronics 113 (2015) 127–131

Finally, we compare all the figures of merit, namely the Vth, IDsat and gmmax degradations normalized at the same injected drain current for both strained and unstrained devices (Fig. 13). Strained MOSFETs exhibit longer lifetimes than unstrained ones, even the

10

10 10

sat

TTF @ ΔID @10% (s)

10

10 10 10 10

9

10 years

7 5 3 1

sSOI 30nm 40nm 50nm 100nm

-1 -3 -5

0.8

131

injected drain current is higher in sSOI. These results demonstrate a better trade off HC degradation vs IDsat and hence a superior HC reliability/performance for sSOI devices. This reliability improvement may be explained by a better quality of the interface between the interfacial SiOx layer (IL) and the sSi channel. Tensile strain allows an increase of the lattice parameter of +0.8% between unstrained Si and Si0.8Ge0.2 reducing the ‘‘lattice mismatch’’ between the sSi layer and the IL. It generally results in a lower initial t0-density of dangling bonds [15] and a lower interface state generation under HC stress in the case of sSOI. In our case, we observe in Fig. 14 an equivalent density of Dit once devices are passivated and a lower effective generation of interface states after HC degradation. 5. Conclusion

VG=VD=Vstress

1.2 1.6 2.0 Vstress (V)

0

10m 20m 30m D Qinj @t=1s (C)

Fig. 12. Time-to-failure of strained SOI devices at different stress voltages. The case of DIsat D with a 10% variation fail criterion is shown. Extrapolation of data points leads to the maximum voltage 0.9 V for a 10 years lifetime of sSOI devices.

In this work, we investigated HC degradations in NMOS FDSOI transistors with High-j/Metal Gate (HfSiON/TiN) stacks. We have compared the reliability of ultrathin SOI-based devices featuring Si and sSi channels. The drive current improvement for sSi devices was demonstrated. We also showed a better NMOS reliability of sSi transistors without any architecture optimization, which is explained by the improved quality of the channel/gate oxide interface.

Lifetime (s)

Acknowledgments

10

9

10

7

10

5

10

3

10

1

SOI

sSOI ΔVth@50mV

10 years

We are thankful to different teams of CEA-LETI for devices processing and electrical characterization expertise. Support from EXACT project was appreciated. References

10

-1

10

-3

sat

ΔID @10%

max

Δgm

@10%

10m 20m 10m 20m 10m 20m D Drain Injected Charge Qinj @t=1s (C) Fig. 13. SOI and sSOI device lifetimes compared at same injected charge into the drain Q Dinj (tstress = 1 s). sSOI exhibit a significant improvement of lifetime for all the parameters.

Fig. 14. Interface states density for both SOI and sSOI from initial (t0) up to 1000 s stress time. Interface degradation is monitored from conductance method. Strained silicon exhibits a lower Dit generation than their SOI counterparts due to gate oxide/ strained channel interface which has a lower lattice mismatch reducing the number and nature of Pb centers.

[1] Morvan S et al. Efficiency of mechanical stressors in Planar FDSOI n and p MOSFETs down to 14 nm gate length. In: Symposium on VLSI technology; June 2012. p. 111–2. [2] Fenouillet-Beranger C et al. Enhancement of devices performance of hybrid FDSOI/bulk technology by using UTBOX sSOI substrates. In: Symposium on VLSI technology; June 2012. p. 115–6. [3] Tyaginov S, Grasser T. Modeling of hot-carrier degradation: physics and controversial issues. Integrated reliability workshop final report; October 2012. p. 206–15. [4] Groeseneken G et al. Trends and perspectives for electrical characterization and reliability assessment in advanced CMOS technologies. Proc ESSDERC 2010:64–72. [5] Ouisse T et al. Hot-carrier-induced degradation of the back interface in shortchannel silicon-on-insulator MOSFETS. IEEE Electron Dev Lett 1991;12(6):290–2. [6] Cristoloveanu S et al. Hot-electron-induced degradation of front and back channels in partially and fully depleted SIMOX MOSFETs. IEEE Electron Dev Lett 1992;13(12):603–5. [7] Ang DS et al. High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer N-MOSFET. Electron Dev Lett Jul. 2003;24(7):469–71. [8] Diouf C et al. ‘‘Y function’’ method applied to saturation regime: Apparent saturation mobility and saturation velocity extraction. Solid-State Electron 2013;85:12–4. [9] Garros X et al. Modeling and direct extraction of band offset induced by stress engineering in silicon-on-insulator metal–oxide–semiconductor field effect transistors: implications for device reliability. J Appl Phys 2009;105. [10] Hu C et al. Hot-electron-induced MOSFET degradation – model, monitor, and improvement. J Solid-State Circuits 1985;20(1):295–305. Feb. [11] Angot D et al. Bias temperature instability and hot carrier circuit ageing simulations specificities in UTBB FDSOI 28 nm node. In: Reliability physics symposium; April 2013. p. 5D.2.1–5D.2.5. [12] Guérin C et al. The energy-driven hot-carrier degradation modes of nMOSFETs. IEEE Trans Dev Mater Rel 2007;7(2):225–35. [13] Subirats A et al. Impact of dynamic variability on SRAM functionality and performance in nano-scaled CMOS technologies. In: Reliability physics symposium; April 2013. p. 4A.6.1–4A.6.5. [14] ITRS, International Technology Roadmap for Semiconductors; 2011 [edition]. [15] Somers P et al. Paramagnetic point defects at interfacial layers in biaxial tensile strained (1 0International Technology Roadmap for Seminductors0)Si/ SiO2. J Appl Phys 2008;103:033703.