Surface roughness and electron backscattering in high aspect ratio silicon nanowires

Microelectronic Engineering 88 (2011) 2368–2371

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Surface roughness and electron backscattering in high aspect ratio silicon nanowires G. Pennelli ⇑, M. Totaro, P. Bruschi Dipartimento di Ingegneria della Informazione, Università di Pisa, Via G. Caruso, I-56122 Pisa, Italy

a r t i c l e

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Article history: Received 15 September 2010 Available online 22 February 2011 Keywords: Silicon nanowire Surface roughness Electrical conduction

a b s t r a c t Four contact current voltage characteristics of high aspect ratio, moderately doped silicon nanowires will be presented and discussed. A nonlinear behavior of the current as a function of the voltage drop has been detected, at room temperature, in small silicon nanowires: the current increases quadratically with respect to the voltage drop increasing. The dependency of this nonlinear behavior with temperature is reported. In this work it will be shown that a possible explanation of this effect can be given taking in account the silicon nanowire surface roughness, that drives the carrier backscattering. This hypothesis is supported by Monte Carlo simulations based on a simple model. The simulation results are in qualitative agreement with the experimental data. Ó 2011 Elsevier B.V. All rights reserved.

1. Introduction In last years, silicon nanostructures and nanowires [1] have been the subject of extensive research, due to their interesting properties which open the field to a large range of applications. In particular, silicon nanowires (SiNWs) field effect transistors [2–5] offer interesting prospectives for the future ‘‘beyond CMOS’’ era [6]. Moreover, devices based on silicon nanowires can be used as high sensibility biological [7] and chemical sensors [8]. A quite new and very promising field is the employment of SiNWs as high efficiency thermoelectric devices [9,10] for intriguing applications in energy harvesting. For all the possible applications, it is fundamental to have a full comprehension of the phenomena involved in the electrical transport of silicon nanowires. Very complex and complete modeling of silicon nanowire transport has been largely developed [11,12], and electrical measurements have been performed in order to investigate the modification of conduction with the reduction of the nanowire width [13]. The main target of the present work is to report nonlinear electrical conduction of silicon nanowires with triangular cross section, moderately doped and with an high aspect ratio L=w, where L and w are the nanowire length and width, respectively. Nonlinearities in silicon nanowire conductivity have been reported before [14], and they have been ascribed to Schottky barriers because measurements have been performed in two contact configuration, and moreover metal contacts have been placed directly on the SiNW with a very small contact area. However the four contact technique, ⇑ Corresponding author. Tel.: +39 050 2217 699; fax: +39 050 2217 522. E-mail address: [email protected] (G. Pennelli). 0167-9317/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.02.089

employed in the present work, allows to measure the SiNW conductivity avoiding any contact effect, such as Schottky barriers or other. In this case, nonohmic (nonlinear) conduction of SiNW, presented in this work, must be explained by conducting phenomena involved in the SiNW itself. 2. I  V four contact characteristics Devices, based on a single silicon nanowire, have been realized by exploiting a top down fabrication process, already developed and reported in previous works [15,16]. The process is based on high resolution electron beam lithography [17] and anisotropic etching; the resulting nanowire has a triangular section, whose width w (triangle side) can be reduced in a very well controllable way by means of stress controlled oxidation. Very uniform SiNWs with a length of several micrometers, and narrower than 10 nm, can be routinely fabricated. The flexibility of the top down approach is exploited for the simultaneous fabrication of contacts and other structures, necessary for the electrical characterization. A SEM image of a typical SiNW device is reported in Fig. 1. In the case of the figure, the SiNW is embedded in silicon dioxide, and it is 2.2 lm long. The top right image shows a detail of the SiNW: the silicon core is 25 nm, and it is surrounded by an SiO2 layer. As starting substrate, a SOI wafer with a n doped 5  1015 cm3 top silicon layer has been used. The effective doping of the silicon nanowire is still an open problem. It depends on activation energy of doping species in nanometric structures as also on self-doping due to interfacial states. In Fig. 1, on the left image, contacts for electrical characterization are also visible. The SiNW is fabricated between silicon leads, roughly 100 nm wide and 150 nm thick, necessary for routing the electrical signal to large silicon areas

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Fig. 1. A composition of SEM images of a typical nanowire device. On the left it is shown the SiNW placed between Si leads for electrical characterization. On the top right a detail of the device, showing the silicon core embedded in silicon dioxide, is shown. The measurement system is also schematically represented in the bottom right; electrical signal are routed from the SiNW by means of silicon leads, connected through aluminum pads and microbonding (not shown) to the measurement system.

100  100 lm2 (not shown) where metal contacts with a large surface are provided for external connections. Silicon leads have the same doping of the SiNW, so that their resistance is much smaller than the one of the SiNW owing to their larger cross section. In Fig. 1 a sketch of the measurement technique, performed in a four contact configuration, is also shown: a voltage generator, placed between the amperometric contacts, is employed for biasing the nanowire. The resulting current is measured by means of a picoamperometer. The voltage drop across the nanowire is measured between another couple of silicon leads (voltmetrics), placed very close to the SiNWs ends. Due to the very high impedance and ultra low bias current of the voltmeter, the current flowing into the voltmetric leads can be neglected. As a result, the measured voltage can be considered unaffected by any Schottky barrier. The measured voltage drop is driven only by phenomena involved in the nanowire electrical transport. The three graphs of Fig. 2 show the nanowire current, with respect to the voltage drop between the nanowire extremities (four contact I  V characteristics), for three SiNW with the same length of 2.2 lm and different width w: from left to right 80 nm, 40 nm, 25 nm. All these characteristics have been taken at room temperature. It can be noted that the I  V characteristic is linear for the 80 nm wide nanowire (graph on the left). In this case the electrical behavior of the nanowire is ohmic, and the nanowire behaves as a resistor of doped silicon. For the w ¼ 40 nm nanowire (middle

graph) the I  V characteristics is not linear any more, and the electrical current increases more than linearly with the voltage drop. The nonlinearity is stronger if the nanowire width is further reduced, as shown in the I  V characteristic of a SiNW with w ¼ 25 nm reported on the right of Fig. 2. Measurements of SiNW electrical conduction at different temperatures (higher than room temperature) have been performed, with the aim of giving an interpretation of nonlinearity of the current with respect to voltage drop (nonohmic behavior). In Fig. 3, I  V four contact characteristics for a nanowire with w = 40 nm and L = 2.2 lm, measured at 20 °C, 70 °C and 90 °C are reported (symbols). For each I  V characteristic a fit with the quadratic function: IðVÞ ¼ aV 2 þ bV þ c is also reported, in continuous line. It is clearly shown that the parabolic law gives an excellent fit on the whole investigated temperature range. As shown in Fig. 3, the nanowire current increases with temperature, differently from doped bulk silicon. Moreover, the I  V characteristic tends to become more linear as the temperature increases. In Table 1 the values of the fitting parameters a, b and c are reported for different temperatures. It can be noted that the linear parameter b shows a noticeable increase with temperature, passing from 19 ð109 X1 Þ at room temperature to 58 ð 109 X1 Þ at 90 °C. Conversely, the coefficient of the square term a is almost constant with the temperature. From these experimental results, it seems that the phenomena that cause the nonlinearity are almost temperature independent.

Fig. 2. Four contacts I  V characteristics (current versus voltmetric voltage drop) for nanowires with the same length of 2.2 lm and with different width w: from left to right w = 80 nm, w = 40 nm, w = 25 nm. The transport becomes nonohmic with the nanowire width reduction.

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Fig. 3. Four contacts I  V characteristics for a nanowire with w = 40 nm and L ¼ 2:2 lm, taken at different temperatures (20 °C, 70 °C, 90 °C): symbols are experimental measurements. Fits with the parabolic function IðVÞ ¼ aV 2 þ bV þ c are reported, in continuous lines, for each characteristic.

Table 1 Values of the fitting parameters a, b, c, as a function of the temperature. Temperature (°C)

aðnA=V 2 Þ

bðnA=VÞ

cðnAÞ

20 70 90

11.23 8.02 9.90

19.25 47.80 58.32

4.76 7.04 6.83

3. Discussion and possible interpretation of nonlinearities In order to give a first preliminary interpretation of these experimental results, barrier effects (due to Schottky contacts or others) have not be taken in account, because measurements have been performed with a four contact configuration through silicon leads and large area metal pads. A possible cause of nonlinearities can be related to the scattering on the nanowire walls, that increases as the nanowire cross section is scaled down. As it has been demonstrated, surface roughness affects both the electrical and thermal (phonon scattering) conductivity in small silicon nanowires [9]. Nonlinear electrical conduction is typical of nanostructures with reduced dimensionality. Nonohmic behavior has been observed at low temperature in quantum point contacts [18,19], and this has been related to weak localization [20]. A possible explanation of nonlinearities can be that the scattering from impurities and surface states in the nanowire cause the wire to behave as a string of nonidentical quantum point contacts. Complex models need to be developed for a quantitative agreement with experiments. In this paper a very preliminary study, that takes in account scattering on the SiNW walls, has been per-

formed. Even if preliminary, the considered model gives a qualitative agreement with experimental measurements. Since all the measurements have been performed at room temperature, or higher, quantum effects due to the discrete energy levels have not been considered in the model. For example, the first four eigenvalues of a triangular section with a base width w = 20 nm, evaluated by means of FreeFEM [21], are respectively 6 meV, 13 meV, 15 meV and 24 meV: their difference is smaller than the kT value at room temperature (26 meV). The model consists in standard semiclassical Monte Carlo simulations [22,23] of trajectories in nanowires with triangular cross section (see the pictorial sketch in the center of Fig. 4). A constant electric field has been considered in the z (longitudinal) direction. For the generation of the random path, the incident flux approach [23], has been used: a carrier (electron) is selected at random at one extremity of the nanowire. Its trajectory is then followed in the nanowire until it reached the other extremity of the nanowire, or until it is reflected back to the starting extremity. In this last case the electron is backscattered and it does not give any contribution to the nanowire current. Inside the nanowire, random scattering events are simulated as in conventional bulk silicon, following the standard Drude theory. An average time between bulk scatterings has been chosen in such a way that the electron mobility resulted 0:12 m2 =Vs. The effect of surface roughness [24,25] has been taken in account by means of a parameter a, defined as the ratio between specular and diffusive scattering on the nanowire walls ð0 < a 6 1Þ. Once a trajectory hits a nanowire wall, a specular reflection event is applied with probability a, while a diffusive event is applied with probability 1  a. In the case of a specular event the component of the momentum perpendicular to the surface wall is reversed, meanwhile the component parallel to the surface is maintained. In a diffusive event energy is maintained but the momentum direction is completely randomized. With the decreasing of the a parameter, the effect of diffusive scattering increases. It must be noted that an increase of diffusive scattering on the walls gives an higher probability that an electron trajectory is folded back with respect to the electric field direction: in this case backscattering increases. A very high number of trajectories (10,000) have been simulated for different voltage values (electric field intensity): the average drift velocity and nanowire current have been evaluated. In Fig. 4, the model is schematically represented. In the middle a pictorial image of a trajectory in a triangular nanowire is shown: the electric field is applied in the z direction. On the left and on the right a part of a simulated trajectory, consisting of 50 scattering events, is projected on the nanowire triangular cross section, for w ¼ 40 on the left and w ¼ 25 on the right. Fig. 5 shows simulated I  V characteristics for a nanowire with w = 25 nm and L ¼ 2:2 lm; several characteristics are reported for different values of the specular parameter a. The nonlinearity

Fig. 4. Simulations of scattering events in silicon nanowires. In the figure a limited number of 50 scattering has been reported, and the trajectory has been projected on the plane of the triangular cross section (see the sketch in the middle). Two sections with different width w = 40 nm and w = 25 nm are shown.

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Fig. 5. In the main graph simulated I  V characteristics for a nanowire with w = 25 nm and L ¼ 2:2 lm are reported. The three curves are related to three different values of the a parameter (see text). In the inset the backscattering coefficient is reported as a function of the a parameter, for different applied voltage values.

increases with the decreasing of the specular reflections on the nanowire walls. A possible explanation can be given as follows. The backscattering coefficient Br is defined as the number of trajectories that end on the starting point, with respect to the total number of trajectories. In the inset of Fig. 5, Br is reported as a function of the a parameter, for four different applied voltages. The inset shows that Br is higher for smaller a parameter (higher diffusive scattering). Diffusive scattering on the walls increases the probability that an electron trajectory is folded back with respect to the electric field direction, and backscattering is increased. The most noticeable fact is that Br decreases at higher voltages. For high drift velocities, produced by high fields, the electron trajectories become more orientated in the z direction, reducing the rate of surface scattering. In this way the current increases both for the increasing of average drift velocity (as in the standard Drude theory), and for the decreasing of total backscattering. This could give an interpretation of the fact that the current grows more than linearly with voltage. The model gives a qualitative agreement with experimental results. In particular it explains quite well nonlinearities detected in experimental I  V characteristics, establishing a relationship between nonlinearities and nanowire surface roughness. Further theoretical investigations, with more complex models, need to be performed in order to obtain a complete agreement with experimental results. Other phenomena may be involved in electrical conduction of small silicon nanowires. For example in this model, the scattering phenomena in the silicon core has been considered

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unmodified with the nanowire width, and similar to those of the bulk silicon. Conversely, the modification of phonon energy and distribution with nanowire dimensions can play an important role in these small structures, and should be taken in account. This would require a complete modeling of phonon, and of phonon/ electron scattering mechanisms, in structures of reduced dimensionality. In conclusion in this work experimental I  V characteristics of moderately doped, high aspect ratio, silicon nanowires are shown. A quadratic dependency of the nanowire current with respect to the voltage drop is reported. This behavior cannot be ascribed to barrier effects, because measurements have been performed in a four contact configuration. The proposed model, based on the hypothesis that conduction is dominated by the scattering on the nanowire walls, gives a qualitative agreement with the experimental results, providing a possible explanation of the observed nonlinearities. Further theoretical investigation, with more complex models, is required in order to obtain also a quantitative agreement with experimental results. References [1] Y. Cui, L.J. Lauhon, M.S. Gudiksen, J. Wang, C.M. Lieber, Appl. Phys. Lett. 78 (2001) 2214. [2] Y. Li1, C. Hwang, Sem. Sci. Technol. 24 (2009) 0268. [3] R. Wang, H. Liu, R. Huang, J . Zhuge, L. Zhang, D. Kim, X. Zhang, D. Park, Y. Wang, IEEE Trans. Electron Dev. 55 (2008) 2960. [4] J. Martinez, R.V. MartÃNnez, R. Garcia, Nano Lett. 8 (2008) 3636. [5] G. Pennelli, Microelectron. Eng. 86 (2009) 2139. [6] H. Iwai, Microel. Eng. 86 (2009) 1520. [7] E. Stern, J.F. Klemic, D.A. Routenberg, P.N. Wyrembak, D.B. Turner-Evans, A.D. Hamilton, D.A. LaVan, T.M. Fahmy, M.A. Reed, Nature Lett. 445 (2007) 05498. [8] O.H. Elibol, D. Morisette, D. Akin, J.P. Denton, R. Bashir, Appl. Phys. Lett. 83 (2003) 4613. [9] A.I. Boukai, Y. Bunimovich, J. Tahir-Kheli1, J. Yu1, W.A. Goddard III, J.R. Heath, Nature Lett. 451 (2008) 168. [10] A.I. Hochbaum, R. Chen, R.D. Delgado, W. Liang, E.C. Garnett1, M. Najarian, A. Majumdar, P. Yang, Nature Lett. 451 (2008) 163. [11] M. Lenzi, P. Palestri, E. Gnani, S. Reggiani, A. Gnudi, D. Esseni, L. Selmi, G. Baccarani, IEEE Trans. Electron. Devices 55 (2008) 2086. [12] S. Poli, M.G. Pala, IEEE Electron. Dev. Lett. 30 (11) (2009) 1212. [13] S.J. Lee, J. Kor. Phys. Soc. 55 (2009) 2491. [14] S-W. Chung, J-Y. Yu, J.R. Heath, Appl. Phys. Lett. 76 (2000) 2068. [15] G. Pennelli, M. Piotto, J. Appl. Phys. 100 (2006) 054507. [16] G. Pennelli, B. Pellegrini, J. Appl. Phys. 101 (2007) 104502. [17] G. Pennelli, F.D. Angelo, M. Piotto, G. Barillaro, B. Pellegrini, Rew. Sci. Instrum. 74 (2003) 3579. [18] J.P. Bird, R. Akis, D.K. Ferry, D. Vasileska, J. Cooper, Y. Aoyagi, T. Sugano, Phys. Rew. Lett 82 (1999) 4691. [19] J.P. Bird, A. Shailos, M. Elhassan, C. Prasad, K.M. Indlekofer, L. Shifren, R. Akis, D.K. Ferry, L.H. Lin, N. Aoki, Y. Ochiai, K. Ishibashi, Y. Aoyagi, Microelectron. Eng. 63 (2003) 277. [20] R. Akis, D.K. Ferry, J.P. Bird, D. Vasileska, Phys. Rew. B 60 (1999) 2680. [21] See the FreeFEM internet site . [22] C. Jacoboni, M. Reggiani, Rew. Modern Phys. 55 (1983) 645. [23] M. Lundstrom, Fundamentals of Carrier Transport, Cambridge University Press, 2000. [24] S. Jin, M.V. Fischetti, T. Tang, J. Appl. Phys. 102 (2007) 083715. [25] F.M. Bufler, A. Schenk, W. Fichtner, IEEE Trans. Electron Dev. 47 (2000) 1891.