Switched-loop filter for automatically frequency-calibrated phase-locked loops

Microelectronics Journal 44 (2013) 468–471

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Switched-loop filter for automatically frequency-calibrated phase-locked loops Yan Han, Dongdong Zhong, Xiaoxia Han n, Xiao Liang, Weiwei Yang, Qian Zhou Institute of Microelectronics and Optoelectronics, Zhejiang University, Hangzhou 310027, PR China

a r t i c l e i n f o

a b s t r a c t

Article history: Received 22 September 2011 Received in revised form 7 January 2013 Accepted 8 January 2013 Available online 6 March 2013

A novel switched-loop filter, which can significantly reduce ripples on voltage controlled oscillator (VCO) control line, is proposed for phase-locked loops (PLL) with an automatic frequency calibration technique. Complementary bootstrapped transmission gates are utilized and rearranged clocks are generated to improve the performance of loop filter. Based on the SMIC 65 nm RF CMOS process, the proposed switched-loop filter applicable to 0.8 V to 6 GHz PLL with automatic frequency calibration technique is designed. Transistor level simulation results in SPECTRE show that using the proposed switched-loop filter, ripples at VCO control line are reduced down to 2 mV and the phase noise of PLL is  136.4 dBc/Hz at 1 MHz offset. Compared with the PLL using conventional loop filter, the control voltage ripples and the phase noise are improved by 98.8% and 29.7 dB, respectively. Crown Copyright & 2013 Published by Elsevier Ltd. All rights reserved.

Keywords: PLL Switched-loop filter Ripples

1. Introduction In modern wireless communication and broadcasting systems, phase-locked loops (PLL) are widely used as local oscillators (LO) to generate periodic signals. As an essential component in RF transceivers, PLL is required to be with low phase noise and low power consumption, wide-tuned, and fast-locked. In order to cover a wide tuning range, a large VCO gain is necessary. However, since a high VCO gain is susceptible to in-band noise contributions, a low VCO gain is preferred to ensure the low phase noise in the PLL. The most common approach to resolve this issue for simultaneously achieving a low phase noise and a wide tuning range is to employ a switched capacitor bank as well as fixed capacitors and varactors to combine discrete and continuous tuning in LC-tuned VCO [1,2]. This topology requires an automatic frequency calibration (AFC) circuit to decide the optimum control bits of switched capacitors to obtain a continuous tuning range. However, the introduction of the AFC technique brings about the problem of longer acquisition time. And the operation of the switches can also create larger ripples on the voltage control terminal of VCO. In contrast to previous work, which focused on the fast acquisition [3,4], this work focuses on the control voltage ripple suppression and phase noise reduction by introducing a switched-loop filter (LF) circuitry. This paper is organized as follows. Section 2 introduces the automatic frequency calibration techniques briefly. Section 3 discusses the problems existed in the previous calibration

n

Corresponding author. Tel./fax: þ 86 571 87953116. E-mail address: [email protected] (X. Han).

structure. Section 4 describes the proposed switched-LF and its improvement measures. Section 5 gives simulation results and comparison results. Finally, conclusions are drawn in Section 6.

2. Automatic frequency calibration techniques The locking process of AFC-based PLL is realized in two steps, a coarse tuning followed by a fine tuning (normal PLL locking process). According to whether the loop is open or closed during the coarse tuning process, the calibration can be grouped into open-loop and closed-loop method. Due to its modest calibration time and relatively simple structure, the open-loop AFC is widely used. Fig. 1 illustrates the conventional open-loop AFC-based PLL. Seen from the scheme, the extra auxiliary circuit in the gray area of Fig. 1 is introduced to set the capacitor array bits and generate clock S, and its complementary clock S0 to control loop switches SW1 and SW2 during calibration. At the beginning of the locking process, the auxiliary circuit generates clock to make SW1 disconnect the loop at LF and SW2 connect Vctrl (control port of the VCO) to the reference voltage, which is usually half the supply voltage. Then, it counts the cycles of divider0 s output signal and reference signal separately and adjusts the switched capacitor array bits according to the binary search algorithm [5] until an optimal band which covers the target frequency is selected. After that, switch SW2 is opened and SW1 is closed to the output of the loop filter, fine-tuning takes over and consequently adjusts the VCO frequency as close as possible to a target frequency and finalizes the tuning voltage Vctrl.

0026-2692/$ - see front matter Crown Copyright & 2013 Published by Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2013.01.007

Y. Han et al. / Microelectronics Journal 44 (2013) 468–471

Auxiliary Circuit Counter Counter

Cap Bank Control Logical

Digital Comparator

C S

…

VDD

f REF

PFD

R3

CP C1

R2

2

SW2 Vctrl SW1 C3

fVCO

C2

Switched-LF

N Fig. 1. Open-loop AFC-based PLL.

Vctrl Vx

469

difference in the instantaneous capacitance of varactors. Such an unbalance generates the even harmonics at the control line of VCO, which moderates the output of LF forming the voltage ripples at Vctrl, shown in Fig. 3. For the even harmonics contain many components (mainly secondary harmonic) so that the amplitude of the ripples cannot remain unchanged, it seems like that the frequency of the even harmonic is not 12 GHz as expected in Fig. 3. But it actually oscillates at about 12 GHz if seen carefully. As we know, the even harmonics work like common mode signals. The on-resistance of the introduced TG which is in series with the varactors forms a low impedance path at the common node Vctrl, which makes it possible for the even harmonics to modulate the output of LF and induce apparent voltage ripples. The ripples then flow through the varactors to AC ground in turn, degrading the Q factor and increasing the phase noise at the output. To suppress the ripples, an extra capacitor is exploited parallel with varactors to provide high impedance to even harmonics, so the voltage ripples can be suppressed significantly. The additional capacitor together with the onresistance of TG forms an additional high frequency pole to make the loop fourth-order. The problem with fourth-order loop design is maintaining the required loop bandwidth and phase margin [6].

Vy 3.2. Non-ideal effects Neglecting the substrate biasing effect, the on-resistance of a MOS switch when it conducts can be written as: Ron ¼

Fig. 2. NMOS-only LC-tuned VCO.

3. Circuit analysis and design Considering the structure described previously, the proposed open-loop AFC PLL is different from the conventional PLL in the introduction of the loop switch. A transmission gate (TG) which is comprised of a PMOS and a NMOS driven by complementary signals is connected in series with the output of LF and Vctrl in order to transmit the voltage from rail-to-rail, which is a demand for wide tuning range. But the introduction of TG increases the voltage ripples at VCO control line (Vctrl) thus deteriorates the PLL phase noise. The following will discuss the cause of voltage ripples and non-ideal effects due to the introduction of the switches in depth. A LC-tuned VCO of differential NMOS-only topology is taken as an example to analyze the phenomenon mentioned.

1

mn C ox ðW=LÞðV g V in V th Þ

where Vg is the gate voltage of the switch, Vin is the input signal voltage and Vth is the threshold voltage. Seen from Eq. (1), the on-resistance of a MOS switch varies nonlinearity with the change of Vin and Vth while Vg is often to be 0 or VDD, which keeps unchanged when it conducts. Taken the substrate biasing effect into consideration, the threshold voltage is given as: pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffi V th ¼ V th0 þ gð j2FF þV SB j j2FF jÞ ð2Þ where g is the body factor and usually to be set from 0.3 V1/2 to 0.4 V1/2. It is apparent from Eq. (2), when the voltage between source and bulk changes with the source voltage, the threshold voltage changes, resulting in the on-resistance changing with the source voltage. This can be resolved by bulk potential modulation using feedback MOS transistors [6]. The nonlinearity of the TG on-resistance not only generates thermal noise voltage at Vctrl that modulates the phase of the VCO, which finally amounts to a contribution to the phase noise spectrum of the PLL output signal(especially significant in large tuning sensitive VCO), but also makes the additional pole change

3.1. Cause of voltage ripples Non-ideality of phase-frequency detector (PFD) and charge pump (CP) such as dead zone, current mismatch and current leakage will cause spurious tones at multiples of reference frequency. Though a third-order loop filter is exploited at the output of CP to extract the DC level and further suppress noise level and spurious tones, the ripples still exist at LF output. The control voltages of varactors in LC-tuned VCO shown in Fig. 2 are Vx-Vctrl and Vy-Vctrl. They are different except at the zero-crossing time when Vx equals to Vy, resulting in the

ð1Þ

Fig. 3. Voltage ripples at Vctrl.

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Y. Han et al. / Microelectronics Journal 44 (2013) 468–471

MP 6

R2 C2

C3

Φ

MN6S

Vin Vout bootstrapped-TG S Ph1

=

fS

VDD

MP2

Φ

MN1

S

MP4

MN3

S

C1

Coffset1

Φ

Proposed switched-LF

Ph1

φ

Ph1

φ

clock-generator

MN6

MNT5 MN5

MNSW

V in

Vout

MPSW

MP 7 MP12S

MP12 MPT11 MP11

Φ MN12

Φ

MN8

MP9

Φ

Coffset 2

MN10

Fig. 4. Proposed switched-LF.

as the on-resistance changes. In order to significantly attenuate the spurs, the additional pole must be lower than the reference frequency, but must be at least 5 times higher than the loop bandwidth to assure the loop to be stable. If the on-resistance of TG varies a wide range which exceeds the range mentioned above, it will cause an unstable loop or a dissatisfactory spur attenuation. So a constant on-resistance TG is needed in the PLL. Moreover, when TG switches, it will lead to a non-ideal switching component superimposed on top of the output voltage of the loop filter, and the loop inevitably suffers from switching noise. A dummy switch may resolve dynamic errors, overcoming this problem [7].

rejection of spurs. In this paper, a CBTG is introduced in place of R3, which have low and almost constant on-resistance to switch the loop, realize an additional rejection of ripples and prevent even harmonics injecting into the loop filter. In order to significantly attenuate the ripples and assure the loop stability, the size of the CBTG should be elaborately optimized to make the additional pole lower than the reference frequency, but at least 5 times higher than the loop bandwidth. Switched-LF with only one bootstrapped-TG samples the LF voltage periodically, resulting in a discontinuous voltage at VCO control line. So CBTG is utilized in place of bootstrapped-TG. Control signal S generated by the auxiliary circuit is rearranged by the clock generator shown in Fig. 4 to fit for CBTG using. For the purpose that the bootstrap circuit can work in the suitable operating frequency, S is firstly sampled by a periodic clock with frequency of fS (often the reference frequency of PLL) through an AND gate, otherwise the capacitors in this circuit structure would not be able to keep their own voltages constant for a relatively long period of time. Then an out-phase clock f is generated using an inverter. In order to generate coincident complementary signals, A TG is placed before the inverter, and two stages of inverters are used to obtain an in-phase clock f. The f and f are used as the control signals of the bootstrap circuit, so that both the turning on or off of the transmission gates can be controlled in a constant Vgs by the signal S. It is important to keep them coincident and complementary for charge injection cancellation, where an extra inverter delay between f and f would cause a phase difference between the overlap charge packets delivered through the NMOS and PMOS devices in TG [8]. Coincident switching means that device overlap capacitance charge injection is in phase for NMOS and PMOS devices. Elaborate optimization of NMOS and PMOS sizes can minimize charge injection ulteriorly.

4. The proposed switched-LF for AFC To solve the problems mentioned above, a novel switched-LF is proposed. The proposed switched-LF is shown in gray area in Fig. 4. Rather than adds an additional capacitor at Vctrl to form a four-order LF, this approach replaces R3 and the switch SW1 with a complementary bootstrapped TG (CBTG) to form a three-order switched-LF. When the calibration is started, the CBTG is off and the loop is opened at LF, while the switch SW2 is connected to the reference voltage. The switch SW2 is then recognized as a resistor when it keeps on, together with C3, the branch acts as one order loop filter. The high frequency noise from the supply voltage can be alleviated effectively, while the DC level keeps unchanged, the voltage ripples caused by the even harmonics can be reduced as well. After adjusting the frequency band, SW2 is opened and the CBTG is on compared with SW1 being closed in the conventional loop filter, PLL then finalizes the tuning voltage with an equivalent three-order loop filter. R2, C1, and C2 form a standard second-order loop filter. The shunt capacitor C1 is recommended to avoid discrete voltage steps at Vctrl due to the instantaneous changes in the charge pump output current. R2 in series with C2 forms a low pass filter section to eliminate the high frequency noise. To attenuate more unwanted spurs, an additional filtering is necessary. As conventional method, a series resistor and a shunt capacitor prior to the VCO are often placed for an additional

Fig. 5. (a) On-resistance of TG and (b) on-resistance of CBTG.

Y. Han et al. / Microelectronics Journal 44 (2013) 468–471

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5. Simulation results

Fig. 6. Bode plot.

The proposed loop-filter is implemented in a 65 nm 0.8 V to 6 GHz PLL. Simulation verification was conducted in the SPECTRE. The on-resistance of the proposed CBTG varies 2.38% over the voltage range while the common TG varies 96%, as shown in Fig. 5. Here the X-axis is the Vin in Fig. 4, for its voltage range is 0–0.8 V. An additional loop filter pole is placed at 1.5 MHz formed by the on-resistance of CBTG and parallel capacitor. And the closed-loop response Bode plot is shown in Fig. 6. To compare the proposed LF to the original one (in Fig. 1) in terms of control voltage ripples, two PLLs are constructed. Both of them have been designed for the same parameters except for LF. The detailed structure of the PLL is not discussed here for the sake of brevity [9]. As can be seen from Fig. 7, the transient simulation results of a prototype PLL using the switched-LF demonstrate a reduction of the ripples from 171 mV to 2 mV when the loop is settled. Because the circuit is in the reset state at the beginning, the calibration starts after about 2 ms. Therefore, the half VDD of the transient time begins at 2 ms in Fig. 7. This 98.8% suppression clearly demonstrates the ability of the switched-LF to dramatically improve voltage ripples. For fair comparison, we focus on the phase noise of the PLL against a given PLL. The periodic noise simulation is carried out and the result is depicted in Fig. 8. The phase noise of the PLL with proposed LF is  136.4 dBc/Hz at 1 MHz offset, while that of conventional one is 106.7 dBc/Hz. It shows that the suppression of the ripples can significantly improve the noise performance of PLL. In our design, the loop P bandwidth is 200 kHz (taking the effects of the n  modulator in the F–N PLL into consideration), and the reference frequency is about 23 MHz. In the SPECTRE emulator, the simulation result of the PLL phase noise seems a bit like VCO phase noise.

6. Conclusions A switched-LF using CBTG is presented. The proposed switched-LF can be used to implement an AFC-based PLL. Simulation results show the validity and performance improvements of the proposed architecture compared with the conventional one. Furthermore, the proposed switched-LF also can be implemented in fractional-N PLL for further use [10]. References

Fig. 7. Transient response of control voltage of the VCO: (a) with proposed switched-LF and (b) with conventional switched-LF.

Fig. 8. Phase noise of the PLL.

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