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Symbolic fault modelling of MOS combinational circuits
~ ) Pergamon
Microelectron. Reliab., Vol. 37, No. 1, pp. 137-157, 1997 Copyright © 1996 Elsevier Science Ltd Printed in Great Britain. All rights reserved 0026-2714/97 $15.00+.00 PII: S0026-2714(95)00245-4
SYMBOLIC FAULT MODELLING OF MOS COMBINATIONAL CIRCUITS PREDRAG M. PETKOVI(~, DRAGISA P. MILOVANOVI~ and VAN~O B. LITOVSKI Faculty of Electronic Engineering, University of Ni~, 18000 NiL Beogradska 14, Yugoslavia (Received for publication 26 May 1996)
Abstract - This paper presents a new method for fault modelling of MOS
combinational circuits at the transistor level. Every transistor is replaced with a conductance controlled by the gate logic value. The specific advantage of the method is use of a symbolic simulator for circuit function extraction. This function is referred as Transistor Logic Conductance Function (TLCF). Starting from a known TLCF, a
simple set of rules is used for output state determination. The method is suitable for multiple fault model generation thanks to the fact that only one symbolic analysis of a circuit is sufficient for modelling different stuck-open, stuck-short and stuck-at faults of a logic gate, Moreover, the method can deal also with bridging and cut faults. Finally, the application of the TLCF for test pattern generation is considered. Copyright ~') 1996 Elsevier Science Ltd
I. INTRODUCTION It is known that the classical, stuck-at fault-model, operating at the gate level, is inadequate for testing MOS circuits because some physical failures tend to produce transistor stuck-open and stuck-short faults [1]. This is a major reason for modelling MOS circuits at the transistor logic-level. As a compromise between more realistic representation and computational tractability, one can use a simplified switch-level model. One of the methods for fault model generation is based on path algebra [2]. The algebraic solution of the path problems requires evaluation of higher powers (n-1, n being the number of circuit nodes) of the adjacency matrix. The fault model generation needs both path- and cut-sets to be determined. Another method of fault modelling at the transistor logic-level is based on the Logic Transistor Function (LTF) determination [3, 4]. The method uses the basic logic operations and four logic levels to describe the behaviour of the circuit. In this paper, we suggest a new method for modelling MOS combinational circuits at the transistor level. Each transistor is considered as a conductance 137
138
P.M. Petkovi6 et al. controlled with the gate logic state. Therefore, this new method differs from the previous ones in two important aspects. First, the output signal can be obtained with a simple symbolic simulator in the form of an algebraic expression as a function of transistor conductances. The conductances can take values either 1 or 0 to recognise conducting and nonconducting transistor channels, respectively. Having in mind that these values are controlled by logic states applied to the transistor gate, we shall call this function the transistor logic conductance function (TLCF). Such a function is a sum of two terms.
The first is a product of the supply voltage VDD and the equivalent conductance of all transistors connected between the output and VDD. The second is a product of the supply voltage VSS and the equivalent conductance between the output and VSS. Second, unlike previous methods, starting from a known TLCF a simple set of rules is used for output value determination. The application of the TLCF enables efficient fault modelling of MOS circuits. The method is very suitable for multiple fault model generation because only one symbolic analysis of a circuit is sufficient for modelling different stuck-open, stuckshort and stuck-at faults. The nature of the proposed approach allows direct transformation of the physical fault into logic function. Therefore, it is easy to perform path testing and test pattern generation of MOS circuits. The definition of the TLCF and different aspects of its application is discussed in the next section of this paper. Some examples will be presented illustrating the advantages of our method for combinational static CMOS, dynamic C2MOS and nMOS cells in the third section. Also, we consider how the method can be used in conjunction with the well-established D-algorithm for testing of larger assemblies. In the fourth section, our approach is contrasted with other switch-level methodologies with the aim of appraising its implications for design practice.
II. TRANSISTOR LOGIC CONDUCTANCE FUNCTION The output value of a digital MOS circuit depends on the actual connection path between the output and both bias voltages, VDD and VSS. Consequently, the circuit function which determines the output logic value can be found by one of several topological methods [3, 5]. Usually, switch-level logic simulators consider MOS transistors as switches. There is no doubt that switchqevel simulation can be useful for fault modelling of
Symbolic fault modelling
139
stuck-open and stuck-short defects. However, each new defect needs one more simulation. The same is true for numerical electrical analysis of the circuit using Spice-like programs [6], [7], or using an equivalent resistor net [8]. The repetitive circuit analysis for every fault can become very bothersome. It is well-known that a single symbolic analysis of an analogue circuit can replace repetitive numeric circuit analyses [9]. Here, we apply the same principle to digital circuits. We replace every transistor in a CMOS circuit with a single conductance whose value is controlled by the logic value on the gate. Although switchlevel transistor models have the same controlling mechanism, they are not suitable for symbolic analysis since individual transistors are not identified by symbolic variables. This is the crucial difference between our method and switch-level approaches. Let us consider a generalised topology of a MOS
primitive shown
in
Figure 1.a. Substituting every MOS transistor in the circuit with a transistor drainsource conductance, we get an equivalent circuit as presented in Figure 1.b. Now, we can find the output voltage as a function of the bias voltages. By the principle of superposition, it is obvious that the output voltage is the sum of two terms. Each represents the influence of the particular bias voltage on the output as equation (1) shows:
(1)
Vout = aDVss + aLVDD .
Here coefficients aD and a L are defined as:
a 0
=
-
•De -
GD,+G,~"
a L -
GLe GD,+GL,"
(2)
I rOD
Load net IF Driver net s'Out ~
! GDe
! ~F GLe Vc~t ~ __ VDD
a)
b)
Figure I.
a) Gcneralised MOS circuit and b) equivalent conductance circuit
P.M. Petkovi~:et al.
140
where GDe and GLe are the equivalent conductances of the MOS transistors in driver and load networks, respectively, looking from the output as shown in Fig l.b. Actually
GDe is the equivalent conductance of the conductive path between the output and VSS, and GLe is the equivalent conductance of the conductive path between output and VDD. Returning from the analogue to the logic level of abstraction, we can treat VDD as logic I and VSS as logic 0. Also, we assign the logic value 0 to every open transistor's conductance, and value 1 otherwise. Therefore, equation (1) becomes a logic function that we call Transistor Logic Conductance Function and denote with TLCF. (From now on we will use normal lettering for TLCFs instead of italic, to distinguish the logic variables from the analogue.) The general form of the TLCF for MOS logic circuits is: TLCF = TLCFD.VSS + TLCFL.VDD
(3)
where TLCFD and TLCFL are functions of GDe and GLe analogously to ctD and aL:
TLCFD -
GDe GD e + GL e ,
TLCE GLe L - GD e ÷ GL e •
(4)
Although this seems to be identical to the definition (2) for a D and aL, there is an important distinction. Namely, all the conductances in (4) take logic rather then the natural values. However, the symbolical identity between equations (2) and (4) enables implementation of symbolic simulators for TLCF generation. To avoid misunderstanding, it is worth emphasising that the conductances of all transistors have logic values that imply if the particular transistor is open or closed. The equivalent conductances have the same meaning - they indicate if the specific equivalent path is open or closed. Generally, an equivalent conductance has a non-zero value when any of the parallel conductances and all conductances in serial branches take non-zero values. The direct correlation between the equivalent conductances and the connected paths from the output to VDD and VSS is very important for efficient fault modelling. As already explained in [2], the connected paths (defined as the 'path-set') are widely used in conjunction with the D-algorithm for the testing of larger circuits [4]. More details on this subject are given in the fourth section of our paper. We want to emphasise, again, the direct correlation between equivalent conductance and logic function of a circuit, since it is to be used for the circuit function extraction.
Symbolic fault modelling
II. A. Circuit function extraction Once the TLCF is known, we can use it in logic function determination. First, we make a relationship between controlling logic values on gates and transistor conductances. The value T we assign to the conductances of all nMOS transistors with high logic value, and of all pMOS transistors with low logic value on their gates. With these values, TLCF D and TLCF L can then be evaluated. The TLCF i (i ~ {D, L}) value shows if there exists a conductive path from output to the appropriate power supply (TLCF i ~ 0) or such a path does not exist (TLCF i = 0). Now it is easy to see that the output logic value depends on values of TLCF i. Namely, if output value is denoted with F, then the following mapping can be used: TLCF D ~ 0, TLCF L = 0 ~ F='0' TLCF D = O, TLCF L ;~ 0 ~ F = T TLCF D = 0, TLCF L = 0 ~ F='Z ' TLCF D ~ 0, TLCF L ;~ 0 ~ F='X ' where 'Z' denotes high impedance and 'X' refers to an indeterminate logic value. The high impedance arises with open conductive paths (i.e. no paths) between output and both power supplies. (This 'floating' state holds the previous logic state that was stored in the parasitic capacitance of the gate). Oppositely, when both paths from the output to the power supplies exist, the output takes indeterminate ('don't know') logic value. The exact values of TLCF D and TLCF L can be evaluated directly from the algebraic expression (3) when appropriate logic values (0 or 1) are assigned to each transistor conductance. However, at the logic level of abstraction it is necessary just to recognise if the particular TLCF i is equal to zero, or not. Therefore, it is sufficient to monitor only values of GDe or GLe since they strictly determine the appropriate TLCF i. Moreover we remark that, particularly, only the numerators of the equivalent conductances define the TLCF i logic value. We assign logic value T to TLCF i whenever Gie (ie ~ {De, Le}) takes non-zero value, and logic zero otherwise. Like in other application of symbolic analysis, the described procedure shows real benefits for all applications that require repetitive logic simulations. Therefore, we will show that it is very suitable for fault modelling of MOS logic circuits.
II. B. Fault m o d e l l i n g o f M O S circuits The two TLCF i functions enable simulation of stuck-open and stuck-short faults simply by fixing any transistor conductance at high (logic 1, short transistor) or
141
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P.M. Petkovi6 et al. low (logic 0, open transistor) values. The complete set of single faults in a circuit requires 2 n t analyses, where n t is the number of transistors in the circuit. With a known TLCF this is an easy task, because we just have to evaluate two algebraic expressions 2n t
times without running any new simulation. Application of the symbolic approach to fault modelling of complex
combinational circuits emphasises its advantages. Namely, one may look to the complex combinational circuit as a cascade connection of simpler ones [ 10]. Moreover, this approach can deal with any other part of a circuit by modelling it as a conductance. This means that all bridging and break faults may be considered efficiently. As an illustration, we will consider bridging and break faults in subsection III.C
II. C. Test pattern generation At last, we expose the application of the TLCF for test pattern generation. The goal of test pattern generation is to give a reduced set of input combinations (patterns of zeros and ones at the inputs) but still sufficient to detect all possibly single stuckopen or stuck-short faults. Topological methods are very useful for this purpose. They give information about connection of the output with VDD and VSS. Recall that Gie implies the existence of conductive paths from the output to power supplies VSS and/or VDD. If Gie is not zero, there is at least one conductive path. The numerator of Gie indicates the order of a path, i.e. precisely how many elementary paths exist. An elementary path is one visiting no node more then once. For the fault-free circuit, every connected path to VSS drives the output to logic zero, while every connected path to VDD drives the output to logic one. If any driver transistor at the elementary path is stuck-open, the connection to VSS is cut and the output can not be low. On the other hand, if any stuck-open transistor in the load circuit exists, the output not can be high. This implies that the path-set (set of elementary paths) for the driver circuit can be determined by the analysis of terms in the numerator of GDe. Analogously, the analysis of the terms in the numerator of GLe can allow the path-set determination in the load circuit. Opposite to the path-set, the set of unconnected paths can be used for stuckshort fault detection. This set is called the cut-set [2]. Every element of the cut-set contains at least one open transistor in a fault-free circuit. For the driver circuit, the input pattern that activates a cut-set suppresses the output of a fault-free circuit to become low. Simultaneously, the input pattern that activates a cut-set for the load
Symbolic fault modelling
143
circuit suppresses the output of a fault-free circuit to take the high logic level. If we want to detect a stuck-short fault, we have to search the cut-set. When there is no connection, the resistance on a path towards the power supply is high (conductance is zero). Therefore, we look for the cut-set candidates among patterns with Gie=0/N, where N shows order of 'disconnection'. (Looking for N is analogously to observing equivalent resistance.) Higher disconnection order means capability to detect more possible faults with a single pattern. If complex combinational circuits are seen as cascade connections of simpler sections, one may readily recognise that test generation for such circuits consists of three phases, Enabling observability that is to deal with the part of the circuit behind the faulty section; test synthesis for the faulty section; and enabling testability which has to deal with the part proceeding to the faulty section. Detailed study of test generation using symbolic analysis will be given in a subsequent paper.
III. EXAMPLES III. A. CMOS static cells The driver circuit in CMOS cells is made of nMOS transistors and the load circuit is made of pMOS transistors. The topology of the load circuit is the complement of the driver circuit. This means that parallel connection in one corresponds to serial connection in the other. The gates of complementary transistors in CMOS circuits are connected. Therefore, a high (low) logic value on the gate of a complementary pair turns the nMOS transistor on (off) and the pMOS transistor off (on). In this case the logic value 1 (0) is assigned to the equivalent nMOS conductance, and logic 0 (1) to the equivalent pMOS conductance. Let us consider, as an example, the two-input CMOS NOR circuit presented in Figure 2.a. The symbolic analysis of the equivalent conductance circuit presented in Figure 2.b. gives: GD e = Gn a +Gnb,
GLe = GpaGp b . Gpa +Gpb
(5)
Now, clearly, GDe has non-zero logic value when Gna OR Gnb are not 0, and GLe has non-zero logic value only when Gpa AND Gpb take non-zero values. To avoid any possibility that GLe takes an indeterminate value when the numerator is logic zero, we express it always as a rational symbolic function, X/Y (where X and Y are integers_>0). In particular, GLe takes value 0/0 for the circuit under consideration in the case when both Gpa and Gpb are zero.
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P.M. Petkovi(: et al.
roe ao
4
t-
be-
FI
- i v : "--°F ~b
a)
b)
Figure 2.
a) CMOS NOR gate and b) equivalent conductance circuit
The complete CMOS NOR logic function generation is shown in Table I which presents logic function extraction for the fault-free condition. As it was pointed out in part B of the previous section, because of the symbolic approach, the TLCF i can be used for the fault modelling. Specifically, this circuit contains four transistors and detection of the complete set of single faults requires
TABLEI :
CMOS NOR logic function generation under fault-free condition ab
00
01
10
11
G~
0
0
1
1
G~
0
1
0
1
G~
1
1
0
0
G~
1
0
1
0
ODe
0
1
1
GLe
1/2
0/1
0/1
0/0
TLCFD
1
!
TLCFL
0
0
Fff
0
0
Symbolic fault modelling
TABLEII :
145
Fault modelling of CMOS NOR circuit when transistor 'pa' is considered as stuckshort. O0
01
10
11
Gna
0
0
1
1
Gnb
0
1
0
1
1
1
1
1
Cpb
1
0
1
0
%e
0
1
1
2
C~
1/2
0/1
1/2
0/1
TLCFD
0
1
1
1
TLCFL
1
0
1
0
0
X
0
ab
F
eight analyses for all four input vectors. Knowing Gie and, hence, TLCF i in symbolic form, one can assign fixed logic values to the conductances that simulate open and/or short faults o f every transistor, and evaluate the expressions. Table II and Table III show results o f fault modelling when transistor 'pa' is
TABLEIII :
Fault modelling of CMOS NOR circuit when transistor 'na' is considered as stuckopen. i
ab
00
O1
10
11
1/2
0/1
0/1
0/0
Gila
C,De
TLCFD
TLCFL
146
P.M. Petkovi~: et al.
considered as stuck-short (Gpa=l) and transistor 'na' is considered as stuck-open (Gna=0), respectively. As we can see, in both cases the input vector 10 gives a faulty output. For short transistor 'pa' (Table II) it is reflected as indeterminate output, X, because conductive paths from output to both power supplies exist. In the second case (Table III), open transistor 'na', the fault is reflected at the output as high impedance, Z, because there is no path between output and either power supply. As we mentioned in part C of the previous section, the path- and cut-set can be determined from Gie given for the fault-free case. According to the rules for path-set determination, we are looking for the non-zero values of Gie. For the driver net, two input vectors activate elementary paths, 01 and 10, while 11 activates a double path. Hence, the input vectors 01 and 10 are sufficient to detect any stuck-open nMOS transistor in the driver network. We remind the reader that the logic value of nMOS transistor conductivity is equal to the logic value at the transistor's gate. Therefore Gna+Gnb in GDe can be treated as (a + b). Now when we compare this result with the terms in GDe in (5) we see that it corresponds directly to the path-set {a, b}. Oppositely, the cut-set candidates are among those where GDe is equal to '0', indicating that in fault-free circuit there is no path between output and VSS. The input vector 00 is the only one that satisfies this condition and therefore it can detect stuckshort fault in the driver net. The non-existing denominator in GDe implies that the cutset is a complement of {a.b}, rather than that it is the empty set. When we apply the same principles to the load net, one may observe that GLe is not zero only for the input vector 00, and therefore it represents the path-set. The stuck-open faults in the pMOS net can be detected with this input vector. The term GpaGpb in the numerator of GLe (5) implies that the cut-set should be {a.b}. However, having in mind that the logic conductance of pMOS transistors is equal to the complement of the gate logic value suggests to take the complement of that combination for the path-set. This fits with result obtained when the value of GLe was examined. Considering the cut-set, one should observe GLe with value 0/N, N ~ 0. According to the results from Table I, the input vectors 01 and 10 clearly determine the cut-set in the load-net. The same conclusion about the cut-set can be derived if we observe the terms in the nominator of DLe in (5) and take its complement, namely {a, b}. It is easy to see that, because of the topological complementary, the path-set in the driver-net is equal to the cut-set in the load-net and vice versa [5].
Symbolic fault modelling
147
HI. B. CMOS dynamic cells Dynamic CMOS circuits are characterised by having one or two additional inputs that act as clocks and/or clock complements, and an appropriate number of additional transistors that are stimulated by these inputs. The concept of TLCF is general enough to be used without restriction for dynamic logic cell analysis. Because of the additional transistors, the dynamic circuits are usually more complex than static circuits. However, the main disadvantage of symbolic analysis is exponential growth of computer time with the circuit complexity. Precisely, computer time is proportional to the number of different symbols, and this number grows rapidly with circuit complexity. Fortunately, TLCF definition is strictly dependent on GDe and GLe, and these conductivities may be extracted separately from the driver and load nets. This can significantly improve the execution time. Moreover, lumping of symbols is recommended. In lumping, we substitute a group of symbols by a single one. Here, we recall the fact that complex digital circuits are usually based on groups of serial or parallel connected transistors that realise AND/OR functions.
So, equivalent
conductance can be expressed as a sum for parallel, or a product for serial, connected transistors. Our symbolic simulator, SYMSIM [11] automatically treats all parallel connected conductors as a single symbol. Therefore, we lump only serial connected conductors together into a single symbol. If G i and Gj are connected in series, the equivalent conductance is denoted by a 'single' symbol Gi*Gj. As example, we will consider a clocked CMOS cell (C2MOS logic) presented in Figure 3.a. The two separated equivalent conductor circuits for driver and load nets are shown in Figure 3.b. All transistor conductances are denoted with the same label as those used to mark the appropriate transistors, i.e. Gti = ti, where t defines transistor type, t e {n, p}, and i ~ {a, b, c, clk}. The conductances 'na' and 'nc' are lumped in driver net as 'na*nc'. This circuit is interesting because clock and clock complement drive 'nclk' and 'pclk' transistors into the open state simultaneously, leading the output to high impedance whenever clock is set to 0. Two symbolic analyses, for the driver and the load net, give GDe and GLe as:
GDe =
(na * nc) * nclk + nb* nclk ( n a * n c ) + n b + nclk '
(6) pa * pb * polk + pb * pc *pclk GLe = pa * pb + pa * pclk + pb * pc + pb *pclk + pc * pclk " Now we can evaluate GDe and GLe for all combinations of the input vector, substituting every 'hi' and 'pclk' with logic 1, and every 'pi' except 'pclk' with logic 0, when the logic value at input i is T, and with complement values when the ith input
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P.M. Petkovi6 et al.
VDD r---
• .......~ F
nb l
I--no
ZI i
ncIk~-----o na-nc ~-- Lb-~[]
vs-s j a) Figure 3.
b) a) ClockedCMOS (C2MOS) cell and b) equivalentconductancecircuits
state is set to '0', i ~ {a, b, c, clk}. The obtained results are presented in Table IV together with the corresponding TLCFD, TLCFL and F. This table represents the circuit under the fault-free conditions. One can generate the full fault model of the C2MOS cell by substituting appropriate equivalent conductances and TLCFs considering each transistor as stuck-short and stuck-open separately. Test generation requires path- and cut-set determination for the driver and load net. To extract the path-set in the driver net, we look for the GDeS in Table IV with non-zero values. The input vectors 1010, 1011, 1101, 1110 give GDe=I/2 , and 1111 gives GDe = 2/3. As the numerator of GDe determines path order, the first four patterns clearly represent the path-set of the driver net. If any of the nMOS transistors is stuck-open, these input vectors will detect the fault. In this case, the output will take the 'Z' state instead of '0'. Detailed analysis can show that only two of the suggested four vectors are sufficient to cover all stuck-open nMOS transistors. Despite the lumping, the terms in the numerator of GDe in (6) represent the path-set as {a.c.clk, b.clk}.
Symbolic
TABLE IV :
fault m o d e l l i n g
149
C 2 M O S dynamic cell logic function generation under fault-free condition
elk a b c
TLCFD
GLe
TLCFL
0 000
0/0
0/2
0
Z
0 001
0/0
0/1
0
Z
0 010
0/1
0/0
0
Z
0 0 11
0/1
0/0
0
Z
0 100
0/0
0/1
0
Z
0 101
0/1
0/0
0
Z
0 1 10
0/l
0
0/0
0
Z
0 111
012
0
0/0
0
Z
1 000
0/1
0
215
1
1
1 001
0/1
0
1/3
1
1
1 010
1/2
1
0/2
0
0
1 011
1/2
1
0/1
0
0
1 100
0/1
0
1/3
1
1
1 101
1/2
1
0/1
0
0
1 1 10
1/2
1
0/1
0
0
I 11 1
2/3
1
0/0
0
0
The cut-set can help in detection of stuck-short transistors. We are looking for the members of the cut-set in the driver net among input vectors that provide GDe=0/N and N;~0. There are eight such vectors. Five of them are related to the low state at clock input ( 0010, 0011, 0101, 0110, 0111). Each of them can detect the stuck-short fault at transistor 'nclk'. This fault is reflected at the output as logic '0' instead of'Z'. However, the input vectors 1000,
1001 and 1100 can detect stuck-
short faults in other transistors of the driver net. If such faults occur, the output takes indeterminate state 'X' instead of '1'. Now, because of the lumping, we can find only three terms in the denominator of GDe and, therefore, we find only three elements of the cut-set {a-c, b, elk}. However, if the denominator of the expression (6) is expanded, the other five elements can be found.
150
P. M. Petkovi6 et al. When we search for the non-zero values among GLe, we get three input vectors; but only two of them, 1001, and 1100 detect elementary paths (ODe = 1/3), while 1000 (ODe = 2/5) shows that a path of higher order exists. Therefore, if there is any stuck-open pMOS transistor, input vectors 1001 and 1100 are sufficient to detect it. Then the fault-free output state '1' will be replaced with the faulty output 'Z'. When we compare these vectors with the terms in numerator of GLe in (6), we must have in mind that 'polk' is excited with the clock complement and hence, we must take the uninverted value of 'elk' for every 'polk' in the expression. With this fact, the load net path-set can be read from (6) as {a.clk, c.clk}. The cut-set of the load net can be extracted if we consider input vectors that give GLe = 0/N, N ;e 0. There are three patterns that can discover stuck-short fault of pMOS 'polk' (0000, 0001 and 0100). This fault makes the output state '1' instead of 'Z'. For the high clock input, there are four patterns that can cover stuck-short fault in other transistors of the load net (1010, 1011, 1101 and 1110). When 'pa', 'pb' or 'pc' are stuck-short, and these four input vectors are applied, the faulty output will take the value 'X' instead '0'. Although there are seven input vectors, five of them cover all stuck-short faults, and can be simply read from the terms in the denominator of expression (6), namely {a, c, a.b.clk, a-c.clk, b.c.clk}.
n l . C. nMOS cells In nMOS technology, the driver circuit determines logic function while the load circuit is made of a single transistor. Hence, it is clear that TLCF L is insignificant for circuit function determination under fault-free conditions. The condition where the load transistor is stuck-open is the classical output stuck-at-0 fault. Also, we note that for nMOS technology, the circuit function is defined as the complement of TLCF D Therefore, it is sufficient to take only the ODe for further study. Let us consider the nMOS logic cell presented in Figure 4.a. In this example we intend to show modelling of break-faults. Assume that there is a possibility for a breakfault to occur in wire 'w', that connects drains of transistors denoted by 'nb' and 'nd'. Following the conductance concept, this wire should be included in the expression for ODe. Therefore we introduce the wire 'w' in the equivalent conductance circuit from Figure 4.b. as a conductance G w . The logic value of a particular nMOS transistor conductance is equal to the input logic value. Therefore, we will denote each transistor conductance with the same label as those used to mark the appropriate input, i.e. Gi = i, for i E {a, b, c ,d}. The
Symbolic fault modelling
151
VDD
oF
oF na
q
ao
w F
c
,j
nb
1
bo
VSS
~Vss
a)
b) Figure 4.
a) nMOS logicprimitiveand b) equivalentconductancecircuit
expanded form of the obtained expression is: abe + abd + acd + bed + G w (ab + ad + bc + cd) GDe =
(7)
(ac+ad +be + b d ) + G w ( a + b + c + d )
For the fault-free analysis, G w tends to become infinite. Hence, all terms without G w in (7) are insignificant and GDe transforms into:
GDe=
G w (ab + ad + bc + cd) _ (a + c)(b + d) Gw(a+b+c+d ) a+b+c+d
The T L C F D is set to 'I' for non-zero value of G D e
(8)
and that happens
when
(a+c)(b+d)¢0. In that case, the circuit implements a logic function equal to the complement of TLCFD, i.e.F=NOT((a+c)(b+d)). However, for open 'w', G w -- 0, and (7) becomes * = abc+abd+acd+bcd GDe ac+ad + b c + b d
= ab(c+d)+cd(a+b) (a+b)(c+d)
=
a___.bb cd a + b c+d
(9)
As we expected, this TLCFD differs from the previous one. The new TLCFD has non-zero value when 'ab' or 'cd' are greater then zero. Now we have another logic function for the circuit as Ff=NOT(ab+cd) Note again that only one symbolic analysis of the circuit from Figure 4.b, is sufficient to obtain information about circuit behaviour for two quite different circuit topologies (the open 'w' fault changes the topology). Hence we can use the proposed method for modelling different break-faults.
152
P.M. Petkovi6
et al.
Repetitive evaluations of Gne for all sixteen input combinations give fault-free, Fff, and faulty, Ff, circuit functions as presented in Table V. The values of GDe for fault-free and faulty (GDe*) circuit are shown also. Considering break-faults, it seems that almost every 'wire' in a circuit should be tested for cuts. However, such an approach leads to numerous combinations of faults even for a simple logic primitive. Therefore, it is useful to study circuit layout first, and to extract only the 'wires' that probably will result in a break-fault. Figure 5 presents the layout of the nMOS circuit from Figure 4.a. It is obvious that there is serious reason to suspect that a break may occur just in the chosen 'wire'. As an example for bridging fault, let us consider the circuit from Figure 4.a again, but assuming that the fault-free topology does not include wire 'w'. Consequently, the logic function of the circuit equals to expression F*, and the
TABLE V:
n M O S logic function generation under fault-free and open 'w' fault conditions
abcd
GDc
Fff
CrDc*
Ff
0000
0/0
1
0/0+0/0
1
000 1
0/1
1
O/O+O/l
l
00 l 0
O/1
1
0/0+0/1
l
00 I 1
1/2
0
0/0+1/2
0
0 100
011
1
011+010
i
0 10 1
0/2
1
0/1+0/1
1
0 l 10
1/2
0
O/l+O/1
1
0 11I
2/3
0
O/l+l/2
0
I000
0/1
1
O/l+O/O
1
10 0 1
1/2
0
0/1+0/1
1
10 10
0/2
1
O/l+O/1
1
I0 l l
2/3
0
O/l+l/2
0
llO0
112
I12+010
II01
2/3
I/2+0/l
lll0
213
112+011
1111
4/4
112+I12
Symbolic fault modelling
153
II
II
II
II
II
metal
diffusion
poly
EMD
DMD
II poly-metal contact Figure 5.
diff.-metal contact
poly-diffusion c o n t a c t ("buffed")
Layout of the circuitshown in Fig. 4
equivalent conductance of the driver net (for the fault-free circuit) is equal to Gde* in expression (9). If we suppose that bridging fault can occur between drains of transistor nb and transistor nd, we simply connect the drain nodes with a conductor within the equivalent conductor net. Of course, that results, again, with the circuit as shown in Figure 4.b. Therefore the Gde expression will be the same as that presented in (7). Now, all explanations related to this bridging fault are similar to the previously discussed for the break fault, but considering that expression (8) corresponds to GDe under the fault condition, In the conclusion to the break and bridging faults we note that two additional steps are needed. First, it is necessary to extract from the layout only the 'wires' that presumably can be broken, or points that can be bridged during fabrication. Then, we
154
P.M. Petkovi~ et al. present that parts with conductors within the equivalent conductor net, and take them into account during equivalent conductance generation. Of course the values of these conductances are not controlled by the gate logic state. Depending on the particular type of fault they representing, they take values that tend to become infinite or are equal to zero. Considering the test pattern generation, one may observe that Table V shows nine input patterns that supply the low logic value at the output. However GDe numerator indicates only four elementary paths (number in the numerator = 1). If any transistor in the elementary path is stuck-open, the connection to VSS is cut and the output is high. One can find only four input vectors with paths of order '1': 0011, 0110, 1001 and 1100. Hence, if any stuck-open transistor in the circuit exists, these combinations can detect the fault. A comparison with the results for the path-set, presented for the same circuit in [2], implies that the terms in the numerator of GDe directly constitute the path-set (set of elementary paths) for the circuit. Namely, they are {a.b, a.d, b.c, c.d}. The four input vector combinations undoubtedly confirm this. According to the described procedure for the cut-set determination, one observes in Table V six combinations with GDe equal to '0/N', with N ~ 0. The input vectors 0001, 0010, 0100 and 1000, with N = 1 can detect single stuck-short faults, while the input vectors 0101 and 1010, with N = 2, are sufficient to cover any short transistor in the circuit. The four input vectors with the first order of 'disconnecton' agree with the cut-set elements that can be observed as terms in the denominator of expression (8) {a, b, c, d}. Hence, instead of sixteen combinations for circuit verification it is quite sufficient to use just six: four for the stuck-open and two for the stuck-short testing. If we assume that the circuit configuration with broken 'wire' represents a new circuit, we can use the results denoted with '*' in Table V to detect the path-set and cut-set for the new type of nMOS cell. The path-set can be found among the input vectors that gives F*=Ft~0. Actually, we search in Table V for GDe* ~ 0. There are only six values where GDe* indicates the existence of the elementary paths (GDe* = 1/2 ), while value GDe* = 1/2+1/2 suggests the existence of the higher order path. Therefore, the input vectors 0011, 0111, 1011, 1100, 1101, 1110 can detect any stuckopen transistor. Moreover, the detailed study of the GDe* value shows that only two input vectors are sufficient to detect stuck-open transistors, 0011 and 1100. It should be noticed that these two correspond to the terms in the numerator of the factorised GDe* in expression (9), giving the path-set as {a.b, c.d}. The other four input vectors correspond to the terms in expanded form of the numerator, namely {a.b.c, a-b.d, a.c.d,
Symbolic fault modelling b-c-d}. Actually, when one looks in Table V, it can be seen that the first three patterns of the six above are characterised by GDe* =
0/n + 1/2, while the second three
patterns give GDe* = 1/2 + 0/n ( n = 0, 1). Only one pattern from the first set and one from the second are enough to discover any stuck-open transistor in the driver net. The cut-set helps to determine input vectors that are able to detect stuck-short transistors. Searching Table V, one can find nine patterns that give F *= Ff = 1 because there is no connection between output and VSS (GDe* = 0). However, only four of them (0101, 0110, 1001, I010) are characterised with GDe* = 0/1 + 0/1, while the remainder (0001, 0010,
0100,
1000) have GDe* = 0/0 + 0/1, and (0000) has
GDe* --- 0/0 + 0/0. Although any of them can be used to detect stuck-short faults, efficiency in pattern generation requires us to use the input vectors with higher order of disconnection. So, the input vectors 0101, 0110, 1001, 1010 are sufficient to discover any stuck-short transistor in the driver net. Comparing terms in the denominator of (9) presented in expanded form, one finds that these input vectors correspond to the cut-set {a.c, a.d, b.c, b.d}.
IV. DISCUSSION In this section, we discuss TLCF testing in comparison with other known switch-level testing methodologies. A number of them, like [12] and [13], have already been related to the path- and cut-set technique in [5]. The main shortcoming of [12] is an absence of consideration of interconnection faults, while in [ 13] the memory effects are ignored. Since Damper and Burgess's method has shown considerable advantages, it was recently put in conjunction with the D-algorithm by Ismaeel in [3] and [4]. In the original paper, Damper and Burges generate the path- and cut-sets by successive multiplication of the adjacency matrices (which are computed using a path algebra), [2]. A path algebra is a set (having a zero and unit element) equipped with two binary operators: dot (a.b = {a concatenated b} for path-set generation, and a.b = r{a union b} for cut-set generation); and join (avb = r{a union b} for path-set generation avb = r{a concatenated b} for cut-set generation Here, r signifies the 'reduced' set. The number of circuit nodes, n, determines the number of successive matrix multiplies. The logic transistor function (LTF), a method to model CMOS circuits at the logic and transistor level, is described in [4]. LTFs of p- and n-MOS circuits are generated using the path algebra technique [5] with some slight modifications. The fault-free (LTFff) and the faulty (LTFf) representation of the output are used to obtain
155
156
P.M. Petkovi~ et al. the faulty D-cubes of the faulty gate. This procedure is based on the Boolean difference technique and so it requires several logic operations over LTFff and LTFf. The major difference between our and those techniques is that we use a classical symbolic simulator for path- and cut-set generation. Therefore, we avoid multiple adjacency matrix computation. Moreover, there is no need to code new, original software just for this purpose. Since there is straight correlation between TLCF and LTF, a similar procedure for the faulty D-cube generation can be used.
V. CONCLUSION
This paper proposes an original method for MOS logic circuit function extraction and fault modelling. The method is based on symbolic network analysis of a circuit equivalent to MOS logic primitives. Every transistor in the original circuit is replaced with an appropriate conductance in the equivalent network, The obtained linear conductive circuitry can be analysed with any classical symbolic simulator. The resulting equivalent output conductance in symbolic form (in terms of transistor conductances) has a direct relation to the connected paths from the output to both power supplies. Logic values 1 and 0 are assigned to each conductance for short and open transistor, respectively, and the Transistor Logic Conductance Function (TLCF) is introduced. Considering TLCFs, we can generate the circuit logic function. Since all relevant functions are in symbolic form, this approach is suitable for all applications where repetitive analyses are required. We have described the methodology for the fault modelling of MOS circuits (including interconnection faults) and for test pattern generation. We have illustrated the TLCF technique in the context of small MOS circuits. However, it can be used in combination with the D-algorithm for the testing of larger networks. We will direct future research toward the most efficient conjunction of these two algorithms.
ACKNOWLEDGMENT We are grateful to professor Robert J. Damper of the Department of Electronics and Computer Science, University of Southampton, UK, for many helpful suggestions and advices that encouragedus to proceed with our research in the field of electronic testing.
Symbolic fault modelling
REFERENCES [I] R. Wadsack, "FaultModeling and Logic Simulationof C M O S and M O S Integrated Circuits", The Bell System Technical Journal, vol. 57, no.5, pp. 1449-1474, MayJune, 1978. [2] R.I. Damper and N. Burgess "MOS Test Pattern Generation Using Path Algebra",
IEEE Trans. on Computers, vol. C-36, no. 9, pp. 1123-1128, September 1987. [3] A.A. Ismaeel, "A Transistor Fault Model for nMOS combinational Circuits",
Microelectronics Journal, vol. 22, no. 4, pp 15-26, 1991. [4] A.A. Ismaeel, "Stuck Fault Generation for Dynamic CMOS", Microelectron.
Reliab., vol. 34, no. 10, pp 1597-1613, 1994. [5] R. I. Damper and N. Burgess "Path Testing of MOS Circuits", in Design & Test
Techniquesfor I,rLS1 & WS1 Circuits, R.E. Massara, Ed., London: Peter Peregrinus Ltd., 1989, pp. 158-183. [6] DP. Miiovanovid and V.B. Litovski, "Fault models of CMOS transmission gate",
lnterna#onal Journal of Electronics, vol. 71, no. 4, pp 675-683, 1991. [7] D. P. Milovanovid and V. B. Litovski, "Fault Models of CMOS Circuits",
Microelectron. Reliab., vol. 34, no. 5, pp 883-896, 1994. [8] A. Herout and L. Szanto, "Logic Simulator Based on Resistor Nets", in Proc. 7th
European Conference on Circuit Theory and Design, Prague, Czechoslovakia, September 2-6, 1985, pp 149-152. [9] G. Gieielen and W. Sansen, Symbolic Analysis for Automated Design of Analog
Integrated Circuits, Kluwer Academic Publishers, Dordrecht, Netherlands, 1991. [10] Szanto, L., "LOMACH - a MOS circuit mask checking logic simulator",
Computer Aided Design, Vol. 14, No. 6, 1982, pp. 313-319. [11] P.Petkovi6, R, Stevanovid and V. Litovski, "Symbolic approach to linear circuit analysis", Proc. 2nd Serbian Conference on Microelectronics and Optoelectronics, NiL Yugoslavia, October 26-28, 1993, pp. 437-442. [12] S.K Jain and V.D. Agrawal, "Test generation for MOS circuits using Dalgorithm" in Proc. 20th Design Automated Conference, Miami Beach, FL, June 1983, pp. 64-70 [13] J.P. Roth, V.G. Oklobdzija and J.F. Beetem, "Test generation for FET switching circuits" in Proc. 1EEE Test Conference, Cherry Hill, PA, 1984, pp.59-62
157
Microelectron. Reliab., Vol. 37, No. 1, pp. 137-157, 1997 Copyright © 1996 Elsevier Science Ltd Printed in Great Britain. All rights reserved 0026-2714/97 $15.00+.00 PII: S0026-2714(95)00245-4
SYMBOLIC FAULT MODELLING OF MOS COMBINATIONAL CIRCUITS PREDRAG M. PETKOVI(~, DRAGISA P. MILOVANOVI~ and VAN~O B. LITOVSKI Faculty of Electronic Engineering, University of Ni~, 18000 NiL Beogradska 14, Yugoslavia (Received for publication 26 May 1996)
Abstract - This paper presents a new method for fault modelling of MOS
combinational circuits at the transistor level. Every transistor is replaced with a conductance controlled by the gate logic value. The specific advantage of the method is use of a symbolic simulator for circuit function extraction. This function is referred as Transistor Logic Conductance Function (TLCF). Starting from a known TLCF, a
simple set of rules is used for output state determination. The method is suitable for multiple fault model generation thanks to the fact that only one symbolic analysis of a circuit is sufficient for modelling different stuck-open, stuck-short and stuck-at faults of a logic gate, Moreover, the method can deal also with bridging and cut faults. Finally, the application of the TLCF for test pattern generation is considered. Copyright ~') 1996 Elsevier Science Ltd
I. INTRODUCTION It is known that the classical, stuck-at fault-model, operating at the gate level, is inadequate for testing MOS circuits because some physical failures tend to produce transistor stuck-open and stuck-short faults [1]. This is a major reason for modelling MOS circuits at the transistor logic-level. As a compromise between more realistic representation and computational tractability, one can use a simplified switch-level model. One of the methods for fault model generation is based on path algebra [2]. The algebraic solution of the path problems requires evaluation of higher powers (n-1, n being the number of circuit nodes) of the adjacency matrix. The fault model generation needs both path- and cut-sets to be determined. Another method of fault modelling at the transistor logic-level is based on the Logic Transistor Function (LTF) determination [3, 4]. The method uses the basic logic operations and four logic levels to describe the behaviour of the circuit. In this paper, we suggest a new method for modelling MOS combinational circuits at the transistor level. Each transistor is considered as a conductance 137
138
P.M. Petkovi6 et al. controlled with the gate logic state. Therefore, this new method differs from the previous ones in two important aspects. First, the output signal can be obtained with a simple symbolic simulator in the form of an algebraic expression as a function of transistor conductances. The conductances can take values either 1 or 0 to recognise conducting and nonconducting transistor channels, respectively. Having in mind that these values are controlled by logic states applied to the transistor gate, we shall call this function the transistor logic conductance function (TLCF). Such a function is a sum of two terms.
The first is a product of the supply voltage VDD and the equivalent conductance of all transistors connected between the output and VDD. The second is a product of the supply voltage VSS and the equivalent conductance between the output and VSS. Second, unlike previous methods, starting from a known TLCF a simple set of rules is used for output value determination. The application of the TLCF enables efficient fault modelling of MOS circuits. The method is very suitable for multiple fault model generation because only one symbolic analysis of a circuit is sufficient for modelling different stuck-open, stuckshort and stuck-at faults. The nature of the proposed approach allows direct transformation of the physical fault into logic function. Therefore, it is easy to perform path testing and test pattern generation of MOS circuits. The definition of the TLCF and different aspects of its application is discussed in the next section of this paper. Some examples will be presented illustrating the advantages of our method for combinational static CMOS, dynamic C2MOS and nMOS cells in the third section. Also, we consider how the method can be used in conjunction with the well-established D-algorithm for testing of larger assemblies. In the fourth section, our approach is contrasted with other switch-level methodologies with the aim of appraising its implications for design practice.
II. TRANSISTOR LOGIC CONDUCTANCE FUNCTION The output value of a digital MOS circuit depends on the actual connection path between the output and both bias voltages, VDD and VSS. Consequently, the circuit function which determines the output logic value can be found by one of several topological methods [3, 5]. Usually, switch-level logic simulators consider MOS transistors as switches. There is no doubt that switchqevel simulation can be useful for fault modelling of
Symbolic fault modelling
139
stuck-open and stuck-short defects. However, each new defect needs one more simulation. The same is true for numerical electrical analysis of the circuit using Spice-like programs [6], [7], or using an equivalent resistor net [8]. The repetitive circuit analysis for every fault can become very bothersome. It is well-known that a single symbolic analysis of an analogue circuit can replace repetitive numeric circuit analyses [9]. Here, we apply the same principle to digital circuits. We replace every transistor in a CMOS circuit with a single conductance whose value is controlled by the logic value on the gate. Although switchlevel transistor models have the same controlling mechanism, they are not suitable for symbolic analysis since individual transistors are not identified by symbolic variables. This is the crucial difference between our method and switch-level approaches. Let us consider a generalised topology of a MOS
primitive shown
in
Figure 1.a. Substituting every MOS transistor in the circuit with a transistor drainsource conductance, we get an equivalent circuit as presented in Figure 1.b. Now, we can find the output voltage as a function of the bias voltages. By the principle of superposition, it is obvious that the output voltage is the sum of two terms. Each represents the influence of the particular bias voltage on the output as equation (1) shows:
(1)
Vout = aDVss + aLVDD .
Here coefficients aD and a L are defined as:
a 0
=
-
•De -
GD,+G,~"
a L -
GLe GD,+GL,"
(2)
I rOD
Load net IF Driver net s'Out ~
! GDe
! ~F GLe Vc~t ~ __ VDD
a)
b)
Figure I.
a) Gcneralised MOS circuit and b) equivalent conductance circuit
P.M. Petkovi~:et al.
140
where GDe and GLe are the equivalent conductances of the MOS transistors in driver and load networks, respectively, looking from the output as shown in Fig l.b. Actually
GDe is the equivalent conductance of the conductive path between the output and VSS, and GLe is the equivalent conductance of the conductive path between output and VDD. Returning from the analogue to the logic level of abstraction, we can treat VDD as logic I and VSS as logic 0. Also, we assign the logic value 0 to every open transistor's conductance, and value 1 otherwise. Therefore, equation (1) becomes a logic function that we call Transistor Logic Conductance Function and denote with TLCF. (From now on we will use normal lettering for TLCFs instead of italic, to distinguish the logic variables from the analogue.) The general form of the TLCF for MOS logic circuits is: TLCF = TLCFD.VSS + TLCFL.VDD
(3)
where TLCFD and TLCFL are functions of GDe and GLe analogously to ctD and aL:
TLCFD -
GDe GD e + GL e ,
TLCE GLe L - GD e ÷ GL e •
(4)
Although this seems to be identical to the definition (2) for a D and aL, there is an important distinction. Namely, all the conductances in (4) take logic rather then the natural values. However, the symbolical identity between equations (2) and (4) enables implementation of symbolic simulators for TLCF generation. To avoid misunderstanding, it is worth emphasising that the conductances of all transistors have logic values that imply if the particular transistor is open or closed. The equivalent conductances have the same meaning - they indicate if the specific equivalent path is open or closed. Generally, an equivalent conductance has a non-zero value when any of the parallel conductances and all conductances in serial branches take non-zero values. The direct correlation between the equivalent conductances and the connected paths from the output to VDD and VSS is very important for efficient fault modelling. As already explained in [2], the connected paths (defined as the 'path-set') are widely used in conjunction with the D-algorithm for the testing of larger circuits [4]. More details on this subject are given in the fourth section of our paper. We want to emphasise, again, the direct correlation between equivalent conductance and logic function of a circuit, since it is to be used for the circuit function extraction.
Symbolic fault modelling
II. A. Circuit function extraction Once the TLCF is known, we can use it in logic function determination. First, we make a relationship between controlling logic values on gates and transistor conductances. The value T we assign to the conductances of all nMOS transistors with high logic value, and of all pMOS transistors with low logic value on their gates. With these values, TLCF D and TLCF L can then be evaluated. The TLCF i (i ~ {D, L}) value shows if there exists a conductive path from output to the appropriate power supply (TLCF i ~ 0) or such a path does not exist (TLCF i = 0). Now it is easy to see that the output logic value depends on values of TLCF i. Namely, if output value is denoted with F, then the following mapping can be used: TLCF D ~ 0, TLCF L = 0 ~ F='0' TLCF D = O, TLCF L ;~ 0 ~ F = T TLCF D = 0, TLCF L = 0 ~ F='Z ' TLCF D ~ 0, TLCF L ;~ 0 ~ F='X ' where 'Z' denotes high impedance and 'X' refers to an indeterminate logic value. The high impedance arises with open conductive paths (i.e. no paths) between output and both power supplies. (This 'floating' state holds the previous logic state that was stored in the parasitic capacitance of the gate). Oppositely, when both paths from the output to the power supplies exist, the output takes indeterminate ('don't know') logic value. The exact values of TLCF D and TLCF L can be evaluated directly from the algebraic expression (3) when appropriate logic values (0 or 1) are assigned to each transistor conductance. However, at the logic level of abstraction it is necessary just to recognise if the particular TLCF i is equal to zero, or not. Therefore, it is sufficient to monitor only values of GDe or GLe since they strictly determine the appropriate TLCF i. Moreover we remark that, particularly, only the numerators of the equivalent conductances define the TLCF i logic value. We assign logic value T to TLCF i whenever Gie (ie ~ {De, Le}) takes non-zero value, and logic zero otherwise. Like in other application of symbolic analysis, the described procedure shows real benefits for all applications that require repetitive logic simulations. Therefore, we will show that it is very suitable for fault modelling of MOS logic circuits.
II. B. Fault m o d e l l i n g o f M O S circuits The two TLCF i functions enable simulation of stuck-open and stuck-short faults simply by fixing any transistor conductance at high (logic 1, short transistor) or
141
142
P.M. Petkovi6 et al. low (logic 0, open transistor) values. The complete set of single faults in a circuit requires 2 n t analyses, where n t is the number of transistors in the circuit. With a known TLCF this is an easy task, because we just have to evaluate two algebraic expressions 2n t
times without running any new simulation. Application of the symbolic approach to fault modelling of complex
combinational circuits emphasises its advantages. Namely, one may look to the complex combinational circuit as a cascade connection of simpler ones [ 10]. Moreover, this approach can deal with any other part of a circuit by modelling it as a conductance. This means that all bridging and break faults may be considered efficiently. As an illustration, we will consider bridging and break faults in subsection III.C
II. C. Test pattern generation At last, we expose the application of the TLCF for test pattern generation. The goal of test pattern generation is to give a reduced set of input combinations (patterns of zeros and ones at the inputs) but still sufficient to detect all possibly single stuckopen or stuck-short faults. Topological methods are very useful for this purpose. They give information about connection of the output with VDD and VSS. Recall that Gie implies the existence of conductive paths from the output to power supplies VSS and/or VDD. If Gie is not zero, there is at least one conductive path. The numerator of Gie indicates the order of a path, i.e. precisely how many elementary paths exist. An elementary path is one visiting no node more then once. For the fault-free circuit, every connected path to VSS drives the output to logic zero, while every connected path to VDD drives the output to logic one. If any driver transistor at the elementary path is stuck-open, the connection to VSS is cut and the output can not be low. On the other hand, if any stuck-open transistor in the load circuit exists, the output not can be high. This implies that the path-set (set of elementary paths) for the driver circuit can be determined by the analysis of terms in the numerator of GDe. Analogously, the analysis of the terms in the numerator of GLe can allow the path-set determination in the load circuit. Opposite to the path-set, the set of unconnected paths can be used for stuckshort fault detection. This set is called the cut-set [2]. Every element of the cut-set contains at least one open transistor in a fault-free circuit. For the driver circuit, the input pattern that activates a cut-set suppresses the output of a fault-free circuit to become low. Simultaneously, the input pattern that activates a cut-set for the load
Symbolic fault modelling
143
circuit suppresses the output of a fault-free circuit to take the high logic level. If we want to detect a stuck-short fault, we have to search the cut-set. When there is no connection, the resistance on a path towards the power supply is high (conductance is zero). Therefore, we look for the cut-set candidates among patterns with Gie=0/N, where N shows order of 'disconnection'. (Looking for N is analogously to observing equivalent resistance.) Higher disconnection order means capability to detect more possible faults with a single pattern. If complex combinational circuits are seen as cascade connections of simpler sections, one may readily recognise that test generation for such circuits consists of three phases, Enabling observability that is to deal with the part of the circuit behind the faulty section; test synthesis for the faulty section; and enabling testability which has to deal with the part proceeding to the faulty section. Detailed study of test generation using symbolic analysis will be given in a subsequent paper.
III. EXAMPLES III. A. CMOS static cells The driver circuit in CMOS cells is made of nMOS transistors and the load circuit is made of pMOS transistors. The topology of the load circuit is the complement of the driver circuit. This means that parallel connection in one corresponds to serial connection in the other. The gates of complementary transistors in CMOS circuits are connected. Therefore, a high (low) logic value on the gate of a complementary pair turns the nMOS transistor on (off) and the pMOS transistor off (on). In this case the logic value 1 (0) is assigned to the equivalent nMOS conductance, and logic 0 (1) to the equivalent pMOS conductance. Let us consider, as an example, the two-input CMOS NOR circuit presented in Figure 2.a. The symbolic analysis of the equivalent conductance circuit presented in Figure 2.b. gives: GD e = Gn a +Gnb,
GLe = GpaGp b . Gpa +Gpb
(5)
Now, clearly, GDe has non-zero logic value when Gna OR Gnb are not 0, and GLe has non-zero logic value only when Gpa AND Gpb take non-zero values. To avoid any possibility that GLe takes an indeterminate value when the numerator is logic zero, we express it always as a rational symbolic function, X/Y (where X and Y are integers_>0). In particular, GLe takes value 0/0 for the circuit under consideration in the case when both Gpa and Gpb are zero.
144
P.M. Petkovi(: et al.
roe ao
4
t-
be-
FI
- i v : "--°F ~b
a)
b)
Figure 2.
a) CMOS NOR gate and b) equivalent conductance circuit
The complete CMOS NOR logic function generation is shown in Table I which presents logic function extraction for the fault-free condition. As it was pointed out in part B of the previous section, because of the symbolic approach, the TLCF i can be used for the fault modelling. Specifically, this circuit contains four transistors and detection of the complete set of single faults requires
TABLEI :
CMOS NOR logic function generation under fault-free condition ab
00
01
10
11
G~
0
0
1
1
G~
0
1
0
1
G~
1
1
0
0
G~
1
0
1
0
ODe
0
1
1
GLe
1/2
0/1
0/1
0/0
TLCFD
1
!
TLCFL
0
0
Fff
0
0
Symbolic fault modelling
TABLEII :
145
Fault modelling of CMOS NOR circuit when transistor 'pa' is considered as stuckshort. O0
01
10
11
Gna
0
0
1
1
Gnb
0
1
0
1
1
1
1
1
Cpb
1
0
1
0
%e
0
1
1
2
C~
1/2
0/1
1/2
0/1
TLCFD
0
1
1
1
TLCFL
1
0
1
0
0
X
0
ab
F
eight analyses for all four input vectors. Knowing Gie and, hence, TLCF i in symbolic form, one can assign fixed logic values to the conductances that simulate open and/or short faults o f every transistor, and evaluate the expressions. Table II and Table III show results o f fault modelling when transistor 'pa' is
TABLEIII :
Fault modelling of CMOS NOR circuit when transistor 'na' is considered as stuckopen. i
ab
00
O1
10
11
1/2
0/1
0/1
0/0
Gila
C,De
TLCFD
TLCFL
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P.M. Petkovi~: et al.
considered as stuck-short (Gpa=l) and transistor 'na' is considered as stuck-open (Gna=0), respectively. As we can see, in both cases the input vector 10 gives a faulty output. For short transistor 'pa' (Table II) it is reflected as indeterminate output, X, because conductive paths from output to both power supplies exist. In the second case (Table III), open transistor 'na', the fault is reflected at the output as high impedance, Z, because there is no path between output and either power supply. As we mentioned in part C of the previous section, the path- and cut-set can be determined from Gie given for the fault-free case. According to the rules for path-set determination, we are looking for the non-zero values of Gie. For the driver net, two input vectors activate elementary paths, 01 and 10, while 11 activates a double path. Hence, the input vectors 01 and 10 are sufficient to detect any stuck-open nMOS transistor in the driver network. We remind the reader that the logic value of nMOS transistor conductivity is equal to the logic value at the transistor's gate. Therefore Gna+Gnb in GDe can be treated as (a + b). Now when we compare this result with the terms in GDe in (5) we see that it corresponds directly to the path-set {a, b}. Oppositely, the cut-set candidates are among those where GDe is equal to '0', indicating that in fault-free circuit there is no path between output and VSS. The input vector 00 is the only one that satisfies this condition and therefore it can detect stuckshort fault in the driver net. The non-existing denominator in GDe implies that the cutset is a complement of {a.b}, rather than that it is the empty set. When we apply the same principles to the load net, one may observe that GLe is not zero only for the input vector 00, and therefore it represents the path-set. The stuck-open faults in the pMOS net can be detected with this input vector. The term GpaGpb in the numerator of GLe (5) implies that the cut-set should be {a.b}. However, having in mind that the logic conductance of pMOS transistors is equal to the complement of the gate logic value suggests to take the complement of that combination for the path-set. This fits with result obtained when the value of GLe was examined. Considering the cut-set, one should observe GLe with value 0/N, N ~ 0. According to the results from Table I, the input vectors 01 and 10 clearly determine the cut-set in the load-net. The same conclusion about the cut-set can be derived if we observe the terms in the nominator of DLe in (5) and take its complement, namely {a, b}. It is easy to see that, because of the topological complementary, the path-set in the driver-net is equal to the cut-set in the load-net and vice versa [5].
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HI. B. CMOS dynamic cells Dynamic CMOS circuits are characterised by having one or two additional inputs that act as clocks and/or clock complements, and an appropriate number of additional transistors that are stimulated by these inputs. The concept of TLCF is general enough to be used without restriction for dynamic logic cell analysis. Because of the additional transistors, the dynamic circuits are usually more complex than static circuits. However, the main disadvantage of symbolic analysis is exponential growth of computer time with the circuit complexity. Precisely, computer time is proportional to the number of different symbols, and this number grows rapidly with circuit complexity. Fortunately, TLCF definition is strictly dependent on GDe and GLe, and these conductivities may be extracted separately from the driver and load nets. This can significantly improve the execution time. Moreover, lumping of symbols is recommended. In lumping, we substitute a group of symbols by a single one. Here, we recall the fact that complex digital circuits are usually based on groups of serial or parallel connected transistors that realise AND/OR functions.
So, equivalent
conductance can be expressed as a sum for parallel, or a product for serial, connected transistors. Our symbolic simulator, SYMSIM [11] automatically treats all parallel connected conductors as a single symbol. Therefore, we lump only serial connected conductors together into a single symbol. If G i and Gj are connected in series, the equivalent conductance is denoted by a 'single' symbol Gi*Gj. As example, we will consider a clocked CMOS cell (C2MOS logic) presented in Figure 3.a. The two separated equivalent conductor circuits for driver and load nets are shown in Figure 3.b. All transistor conductances are denoted with the same label as those used to mark the appropriate transistors, i.e. Gti = ti, where t defines transistor type, t e {n, p}, and i ~ {a, b, c, clk}. The conductances 'na' and 'nc' are lumped in driver net as 'na*nc'. This circuit is interesting because clock and clock complement drive 'nclk' and 'pclk' transistors into the open state simultaneously, leading the output to high impedance whenever clock is set to 0. Two symbolic analyses, for the driver and the load net, give GDe and GLe as:
GDe =
(na * nc) * nclk + nb* nclk ( n a * n c ) + n b + nclk '
(6) pa * pb * polk + pb * pc *pclk GLe = pa * pb + pa * pclk + pb * pc + pb *pclk + pc * pclk " Now we can evaluate GDe and GLe for all combinations of the input vector, substituting every 'hi' and 'pclk' with logic 1, and every 'pi' except 'pclk' with logic 0, when the logic value at input i is T, and with complement values when the ith input
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VDD r---
• .......~ F
nb l
I--no
ZI i
ncIk~-----o na-nc ~-- Lb-~[]
vs-s j a) Figure 3.
b) a) ClockedCMOS (C2MOS) cell and b) equivalentconductancecircuits
state is set to '0', i ~ {a, b, c, clk}. The obtained results are presented in Table IV together with the corresponding TLCFD, TLCFL and F. This table represents the circuit under the fault-free conditions. One can generate the full fault model of the C2MOS cell by substituting appropriate equivalent conductances and TLCFs considering each transistor as stuck-short and stuck-open separately. Test generation requires path- and cut-set determination for the driver and load net. To extract the path-set in the driver net, we look for the GDeS in Table IV with non-zero values. The input vectors 1010, 1011, 1101, 1110 give GDe=I/2 , and 1111 gives GDe = 2/3. As the numerator of GDe determines path order, the first four patterns clearly represent the path-set of the driver net. If any of the nMOS transistors is stuck-open, these input vectors will detect the fault. In this case, the output will take the 'Z' state instead of '0'. Detailed analysis can show that only two of the suggested four vectors are sufficient to cover all stuck-open nMOS transistors. Despite the lumping, the terms in the numerator of GDe in (6) represent the path-set as {a.c.clk, b.clk}.
Symbolic
TABLE IV :
fault m o d e l l i n g
149
C 2 M O S dynamic cell logic function generation under fault-free condition
elk a b c
TLCFD
GLe
TLCFL
0 000
0/0
0/2
0
Z
0 001
0/0
0/1
0
Z
0 010
0/1
0/0
0
Z
0 0 11
0/1
0/0
0
Z
0 100
0/0
0/1
0
Z
0 101
0/1
0/0
0
Z
0 1 10
0/l
0
0/0
0
Z
0 111
012
0
0/0
0
Z
1 000
0/1
0
215
1
1
1 001
0/1
0
1/3
1
1
1 010
1/2
1
0/2
0
0
1 011
1/2
1
0/1
0
0
1 100
0/1
0
1/3
1
1
1 101
1/2
1
0/1
0
0
1 1 10
1/2
1
0/1
0
0
I 11 1
2/3
1
0/0
0
0
The cut-set can help in detection of stuck-short transistors. We are looking for the members of the cut-set in the driver net among input vectors that provide GDe=0/N and N;~0. There are eight such vectors. Five of them are related to the low state at clock input ( 0010, 0011, 0101, 0110, 0111). Each of them can detect the stuck-short fault at transistor 'nclk'. This fault is reflected at the output as logic '0' instead of'Z'. However, the input vectors 1000,
1001 and 1100 can detect stuck-
short faults in other transistors of the driver net. If such faults occur, the output takes indeterminate state 'X' instead of '1'. Now, because of the lumping, we can find only three terms in the denominator of GDe and, therefore, we find only three elements of the cut-set {a-c, b, elk}. However, if the denominator of the expression (6) is expanded, the other five elements can be found.
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P. M. Petkovi6 et al. When we search for the non-zero values among GLe, we get three input vectors; but only two of them, 1001, and 1100 detect elementary paths (ODe = 1/3), while 1000 (ODe = 2/5) shows that a path of higher order exists. Therefore, if there is any stuck-open pMOS transistor, input vectors 1001 and 1100 are sufficient to detect it. Then the fault-free output state '1' will be replaced with the faulty output 'Z'. When we compare these vectors with the terms in numerator of GLe in (6), we must have in mind that 'polk' is excited with the clock complement and hence, we must take the uninverted value of 'elk' for every 'polk' in the expression. With this fact, the load net path-set can be read from (6) as {a.clk, c.clk}. The cut-set of the load net can be extracted if we consider input vectors that give GLe = 0/N, N ;e 0. There are three patterns that can discover stuck-short fault of pMOS 'polk' (0000, 0001 and 0100). This fault makes the output state '1' instead of 'Z'. For the high clock input, there are four patterns that can cover stuck-short fault in other transistors of the load net (1010, 1011, 1101 and 1110). When 'pa', 'pb' or 'pc' are stuck-short, and these four input vectors are applied, the faulty output will take the value 'X' instead '0'. Although there are seven input vectors, five of them cover all stuck-short faults, and can be simply read from the terms in the denominator of expression (6), namely {a, c, a.b.clk, a-c.clk, b.c.clk}.
n l . C. nMOS cells In nMOS technology, the driver circuit determines logic function while the load circuit is made of a single transistor. Hence, it is clear that TLCF L is insignificant for circuit function determination under fault-free conditions. The condition where the load transistor is stuck-open is the classical output stuck-at-0 fault. Also, we note that for nMOS technology, the circuit function is defined as the complement of TLCF D Therefore, it is sufficient to take only the ODe for further study. Let us consider the nMOS logic cell presented in Figure 4.a. In this example we intend to show modelling of break-faults. Assume that there is a possibility for a breakfault to occur in wire 'w', that connects drains of transistors denoted by 'nb' and 'nd'. Following the conductance concept, this wire should be included in the expression for ODe. Therefore we introduce the wire 'w' in the equivalent conductance circuit from Figure 4.b. as a conductance G w . The logic value of a particular nMOS transistor conductance is equal to the input logic value. Therefore, we will denote each transistor conductance with the same label as those used to mark the appropriate input, i.e. Gi = i, for i E {a, b, c ,d}. The
Symbolic fault modelling
151
VDD
oF
oF na
q
ao
w F
c
,j
nb
1
bo
VSS
~Vss
a)
b) Figure 4.
a) nMOS logicprimitiveand b) equivalentconductancecircuit
expanded form of the obtained expression is: abe + abd + acd + bed + G w (ab + ad + bc + cd) GDe =
(7)
(ac+ad +be + b d ) + G w ( a + b + c + d )
For the fault-free analysis, G w tends to become infinite. Hence, all terms without G w in (7) are insignificant and GDe transforms into:
GDe=
G w (ab + ad + bc + cd) _ (a + c)(b + d) Gw(a+b+c+d ) a+b+c+d
The T L C F D is set to 'I' for non-zero value of G D e
(8)
and that happens
when
(a+c)(b+d)¢0. In that case, the circuit implements a logic function equal to the complement of TLCFD, i.e.F=NOT((a+c)(b+d)). However, for open 'w', G w -- 0, and (7) becomes * = abc+abd+acd+bcd GDe ac+ad + b c + b d
= ab(c+d)+cd(a+b) (a+b)(c+d)
=
a___.bb cd a + b c+d
(9)
As we expected, this TLCFD differs from the previous one. The new TLCFD has non-zero value when 'ab' or 'cd' are greater then zero. Now we have another logic function for the circuit as Ff=NOT(ab+cd) Note again that only one symbolic analysis of the circuit from Figure 4.b, is sufficient to obtain information about circuit behaviour for two quite different circuit topologies (the open 'w' fault changes the topology). Hence we can use the proposed method for modelling different break-faults.
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et al.
Repetitive evaluations of Gne for all sixteen input combinations give fault-free, Fff, and faulty, Ff, circuit functions as presented in Table V. The values of GDe for fault-free and faulty (GDe*) circuit are shown also. Considering break-faults, it seems that almost every 'wire' in a circuit should be tested for cuts. However, such an approach leads to numerous combinations of faults even for a simple logic primitive. Therefore, it is useful to study circuit layout first, and to extract only the 'wires' that probably will result in a break-fault. Figure 5 presents the layout of the nMOS circuit from Figure 4.a. It is obvious that there is serious reason to suspect that a break may occur just in the chosen 'wire'. As an example for bridging fault, let us consider the circuit from Figure 4.a again, but assuming that the fault-free topology does not include wire 'w'. Consequently, the logic function of the circuit equals to expression F*, and the
TABLE V:
n M O S logic function generation under fault-free and open 'w' fault conditions
abcd
GDc
Fff
CrDc*
Ff
0000
0/0
1
0/0+0/0
1
000 1
0/1
1
O/O+O/l
l
00 l 0
O/1
1
0/0+0/1
l
00 I 1
1/2
0
0/0+1/2
0
0 100
011
1
011+010
i
0 10 1
0/2
1
0/1+0/1
1
0 l 10
1/2
0
O/l+O/1
1
0 11I
2/3
0
O/l+l/2
0
I000
0/1
1
O/l+O/O
1
10 0 1
1/2
0
0/1+0/1
1
10 10
0/2
1
O/l+O/1
1
I0 l l
2/3
0
O/l+l/2
0
llO0
112
I12+010
II01
2/3
I/2+0/l
lll0
213
112+011
1111
4/4
112+I12
Symbolic fault modelling
153
II
II
II
II
II
metal
diffusion
poly
EMD
DMD
II poly-metal contact Figure 5.
diff.-metal contact
poly-diffusion c o n t a c t ("buffed")
Layout of the circuitshown in Fig. 4
equivalent conductance of the driver net (for the fault-free circuit) is equal to Gde* in expression (9). If we suppose that bridging fault can occur between drains of transistor nb and transistor nd, we simply connect the drain nodes with a conductor within the equivalent conductor net. Of course, that results, again, with the circuit as shown in Figure 4.b. Therefore the Gde expression will be the same as that presented in (7). Now, all explanations related to this bridging fault are similar to the previously discussed for the break fault, but considering that expression (8) corresponds to GDe under the fault condition, In the conclusion to the break and bridging faults we note that two additional steps are needed. First, it is necessary to extract from the layout only the 'wires' that presumably can be broken, or points that can be bridged during fabrication. Then, we
154
P.M. Petkovi~ et al. present that parts with conductors within the equivalent conductor net, and take them into account during equivalent conductance generation. Of course the values of these conductances are not controlled by the gate logic state. Depending on the particular type of fault they representing, they take values that tend to become infinite or are equal to zero. Considering the test pattern generation, one may observe that Table V shows nine input patterns that supply the low logic value at the output. However GDe numerator indicates only four elementary paths (number in the numerator = 1). If any transistor in the elementary path is stuck-open, the connection to VSS is cut and the output is high. One can find only four input vectors with paths of order '1': 0011, 0110, 1001 and 1100. Hence, if any stuck-open transistor in the circuit exists, these combinations can detect the fault. A comparison with the results for the path-set, presented for the same circuit in [2], implies that the terms in the numerator of GDe directly constitute the path-set (set of elementary paths) for the circuit. Namely, they are {a.b, a.d, b.c, c.d}. The four input vector combinations undoubtedly confirm this. According to the described procedure for the cut-set determination, one observes in Table V six combinations with GDe equal to '0/N', with N ~ 0. The input vectors 0001, 0010, 0100 and 1000, with N = 1 can detect single stuck-short faults, while the input vectors 0101 and 1010, with N = 2, are sufficient to cover any short transistor in the circuit. The four input vectors with the first order of 'disconnecton' agree with the cut-set elements that can be observed as terms in the denominator of expression (8) {a, b, c, d}. Hence, instead of sixteen combinations for circuit verification it is quite sufficient to use just six: four for the stuck-open and two for the stuck-short testing. If we assume that the circuit configuration with broken 'wire' represents a new circuit, we can use the results denoted with '*' in Table V to detect the path-set and cut-set for the new type of nMOS cell. The path-set can be found among the input vectors that gives F*=Ft~0. Actually, we search in Table V for GDe* ~ 0. There are only six values where GDe* indicates the existence of the elementary paths (GDe* = 1/2 ), while value GDe* = 1/2+1/2 suggests the existence of the higher order path. Therefore, the input vectors 0011, 0111, 1011, 1100, 1101, 1110 can detect any stuckopen transistor. Moreover, the detailed study of the GDe* value shows that only two input vectors are sufficient to detect stuck-open transistors, 0011 and 1100. It should be noticed that these two correspond to the terms in the numerator of the factorised GDe* in expression (9), giving the path-set as {a.b, c.d}. The other four input vectors correspond to the terms in expanded form of the numerator, namely {a.b.c, a-b.d, a.c.d,
Symbolic fault modelling b-c-d}. Actually, when one looks in Table V, it can be seen that the first three patterns of the six above are characterised by GDe* =
0/n + 1/2, while the second three
patterns give GDe* = 1/2 + 0/n ( n = 0, 1). Only one pattern from the first set and one from the second are enough to discover any stuck-open transistor in the driver net. The cut-set helps to determine input vectors that are able to detect stuck-short transistors. Searching Table V, one can find nine patterns that give F *= Ff = 1 because there is no connection between output and VSS (GDe* = 0). However, only four of them (0101, 0110, 1001, I010) are characterised with GDe* = 0/1 + 0/1, while the remainder (0001, 0010,
0100,
1000) have GDe* = 0/0 + 0/1, and (0000) has
GDe* --- 0/0 + 0/0. Although any of them can be used to detect stuck-short faults, efficiency in pattern generation requires us to use the input vectors with higher order of disconnection. So, the input vectors 0101, 0110, 1001, 1010 are sufficient to discover any stuck-short transistor in the driver net. Comparing terms in the denominator of (9) presented in expanded form, one finds that these input vectors correspond to the cut-set {a.c, a.d, b.c, b.d}.
IV. DISCUSSION In this section, we discuss TLCF testing in comparison with other known switch-level testing methodologies. A number of them, like [12] and [13], have already been related to the path- and cut-set technique in [5]. The main shortcoming of [12] is an absence of consideration of interconnection faults, while in [ 13] the memory effects are ignored. Since Damper and Burgess's method has shown considerable advantages, it was recently put in conjunction with the D-algorithm by Ismaeel in [3] and [4]. In the original paper, Damper and Burges generate the path- and cut-sets by successive multiplication of the adjacency matrices (which are computed using a path algebra), [2]. A path algebra is a set (having a zero and unit element) equipped with two binary operators: dot (a.b = {a concatenated b} for path-set generation, and a.b = r{a union b} for cut-set generation); and join (avb = r{a union b} for path-set generation avb = r{a concatenated b} for cut-set generation Here, r signifies the 'reduced' set. The number of circuit nodes, n, determines the number of successive matrix multiplies. The logic transistor function (LTF), a method to model CMOS circuits at the logic and transistor level, is described in [4]. LTFs of p- and n-MOS circuits are generated using the path algebra technique [5] with some slight modifications. The fault-free (LTFff) and the faulty (LTFf) representation of the output are used to obtain
155
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P.M. Petkovi~ et al. the faulty D-cubes of the faulty gate. This procedure is based on the Boolean difference technique and so it requires several logic operations over LTFff and LTFf. The major difference between our and those techniques is that we use a classical symbolic simulator for path- and cut-set generation. Therefore, we avoid multiple adjacency matrix computation. Moreover, there is no need to code new, original software just for this purpose. Since there is straight correlation between TLCF and LTF, a similar procedure for the faulty D-cube generation can be used.
V. CONCLUSION
This paper proposes an original method for MOS logic circuit function extraction and fault modelling. The method is based on symbolic network analysis of a circuit equivalent to MOS logic primitives. Every transistor in the original circuit is replaced with an appropriate conductance in the equivalent network, The obtained linear conductive circuitry can be analysed with any classical symbolic simulator. The resulting equivalent output conductance in symbolic form (in terms of transistor conductances) has a direct relation to the connected paths from the output to both power supplies. Logic values 1 and 0 are assigned to each conductance for short and open transistor, respectively, and the Transistor Logic Conductance Function (TLCF) is introduced. Considering TLCFs, we can generate the circuit logic function. Since all relevant functions are in symbolic form, this approach is suitable for all applications where repetitive analyses are required. We have described the methodology for the fault modelling of MOS circuits (including interconnection faults) and for test pattern generation. We have illustrated the TLCF technique in the context of small MOS circuits. However, it can be used in combination with the D-algorithm for the testing of larger networks. We will direct future research toward the most efficient conjunction of these two algorithms.
ACKNOWLEDGMENT We are grateful to professor Robert J. Damper of the Department of Electronics and Computer Science, University of Southampton, UK, for many helpful suggestions and advices that encouragedus to proceed with our research in the field of electronic testing.
Symbolic fault modelling
REFERENCES [I] R. Wadsack, "FaultModeling and Logic Simulationof C M O S and M O S Integrated Circuits", The Bell System Technical Journal, vol. 57, no.5, pp. 1449-1474, MayJune, 1978. [2] R.I. Damper and N. Burgess "MOS Test Pattern Generation Using Path Algebra",
IEEE Trans. on Computers, vol. C-36, no. 9, pp. 1123-1128, September 1987. [3] A.A. Ismaeel, "A Transistor Fault Model for nMOS combinational Circuits",
Microelectronics Journal, vol. 22, no. 4, pp 15-26, 1991. [4] A.A. Ismaeel, "Stuck Fault Generation for Dynamic CMOS", Microelectron.
Reliab., vol. 34, no. 10, pp 1597-1613, 1994. [5] R. I. Damper and N. Burgess "Path Testing of MOS Circuits", in Design & Test
Techniquesfor I,rLS1 & WS1 Circuits, R.E. Massara, Ed., London: Peter Peregrinus Ltd., 1989, pp. 158-183. [6] DP. Miiovanovid and V.B. Litovski, "Fault models of CMOS transmission gate",
lnterna#onal Journal of Electronics, vol. 71, no. 4, pp 675-683, 1991. [7] D. P. Milovanovid and V. B. Litovski, "Fault Models of CMOS Circuits",
Microelectron. Reliab., vol. 34, no. 5, pp 883-896, 1994. [8] A. Herout and L. Szanto, "Logic Simulator Based on Resistor Nets", in Proc. 7th
European Conference on Circuit Theory and Design, Prague, Czechoslovakia, September 2-6, 1985, pp 149-152. [9] G. Gieielen and W. Sansen, Symbolic Analysis for Automated Design of Analog
Integrated Circuits, Kluwer Academic Publishers, Dordrecht, Netherlands, 1991. [10] Szanto, L., "LOMACH - a MOS circuit mask checking logic simulator",
Computer Aided Design, Vol. 14, No. 6, 1982, pp. 313-319. [11] P.Petkovi6, R, Stevanovid and V. Litovski, "Symbolic approach to linear circuit analysis", Proc. 2nd Serbian Conference on Microelectronics and Optoelectronics, NiL Yugoslavia, October 26-28, 1993, pp. 437-442. [12] S.K Jain and V.D. Agrawal, "Test generation for MOS circuits using Dalgorithm" in Proc. 20th Design Automated Conference, Miami Beach, FL, June 1983, pp. 64-70 [13] J.P. Roth, V.G. Oklobdzija and J.F. Beetem, "Test generation for FET switching circuits" in Proc. 1EEE Test Conference, Cherry Hill, PA, 1984, pp.59-62
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