- Email: [email protected]
Synaptic behaviors of HfO2 ReRAM by pulse frequency modulation
Solid State Electronics 154 (2019) 31–35
Contents lists available at ScienceDirect
Solid State Electronics journal homepage: www.elsevier.com/locate/sse
Synaptic behaviors of HfO2 ReRAM by pulse frequency modulation a
a
a
a
T
a
Dong Keun Lee , Min-Hwi Kim , Tae-Hyeon Kim , Suhyun Bang , Yeon-Joon Choi , ⁎ Sungjun Kimb, Seongjae Choc, Byung-Gook Parka, a Inter-university Semiconductor Research Center (ISRC) and the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Republic of Korea b School of Electronics Engineering, Chungbuk National University, Cheongju 28644, Republic of Korea c Department of Electronics Engineering, Gachon University, 1342 Seongnamdaero, Sujeong-gu, Seongnam-si, Gyeonggi-do 13120, Republic of Korea
A R T I C LE I N FO
A B S T R A C T
Keywords: Tunneling barrier layer Resistive-switching random-access memory Potentiation Depression Synaptic plasticity Spike rate-dependent plasticity (SRDP)
A resistive switching random-access memory (ReRAM) device with TiN/HfO2/SiO2/p+-Si stack is analyzed for synaptic behavior. Fabricated RRAM device stack consists of heavily doped p-type silicon bottom electrode (BE), HfO2 as a switching layer, SiO2 as a tunneling barrier layer and TiN as a top electrode (TE). The RRAM cell successfully shows I-V curves including SET and RESET operations in DC sweep mode. By inserting a SiO2 tunneling barrier layer, gradual switching characteristics are obtained by pulse operation. By optimizing the pulse scheme applied to the device, biological synaptic plasticity of long-term potentiation and depression is demonstrated. Finally, spike rate-dependent plasticity (SRDP) learning rule is realized by applying pulses with different frequencies to both terminals of the ReRAM device.
1. Introduction Resistive-switching memory (ReRAM) devices have been regarded as one of next-generation memories due to its fast speed, CMOS compatibility and ultralow switching energy [1–6]. These superiorities make the ReRAM devices strong candidates to replace conventional non-volatile NAND Flash memories. Besides its possibility as a storage class memory, ReRAM device also receives great attention as a synaptic device that emulates biological functions due to its 2-terminal structure, feasibility of implementing cross-point array and gradual switching operation [7–9]. Possibility of massive data processing by parallelism using the ReRAM array give rise to an expectation to replace current von Neumann computing that utilize sequential process and consume lots of power [10]. By adopting numerous advantages of ReRAM devices including modulation of multiple conductance levels and low operation power, various bio-inspired learning rules including spike timing-dependent plasticity (STDP) and spike rate-dependent plasticity (SRDP) are under the extensive research to realize long-term potentiation (LTP) and depression (LTD) [11]. Another form of memristive device, conductive bridge RAM (CBRAM) is employed to realize paired-pulse facilitation/depression (PPF/PPD) by modulating the pulse stimulation [12]. It is reported that both PPF and PPD is a shortterm biological learning rules that are mimicked using a nanoparticlebased ReRAM [13].
⁎
Corresponding author. E-mail address: [email protected] (B.-G. Park).
https://doi.org/10.1016/j.sse.2019.02.008
Available online 19 February 2019 0038-1101/ © 2019 Published by Elsevier Ltd.
In this work, the spike rate-dependent plasticity (SRDP) is demonstrated by modulating a pulse frequency using fabricated TiN/HfO2/ SiO2/p+-Si stacked ReRAM device. Although recent trend of emulating the synaptic learning rule by ReRAM devices is STDP [14,15], there is a report that SRDP is more realistic way of mimicking a biological neural network compared to STDP because of its random input/output spike rates [16]. According to the literature, STDP can only sustain both LTP and LTD under a synchronous input spike which does not suit for a real neural network operation. Unlike other experiments where most of synaptic behavior measurement is carried out via metal-insulator-metal (MIM) structure [17,18], metal-insulator-silicon (MIS) structured ReRAM device was used in this experiment which is CMOS compatible. There are reports regarding tunneling barrier layer inserted ReRAM with low forming voltage and operation power that are essential to implement in neuromorphic system [19–21]. Compared to the device without tunneling barrier layer, the proposed device with TiN/HfO2/ SiO2/p+-Si stack allows nonlinear switching behavior by electron tunneling mechanism inside the SiO2 layer, thereby reducing the leakage current in low voltage regime. As a parallelism rises as one of essential issues for implementation of a neural network [22], the proposed device can reduce sneak path to increase pattern recognition accuracy. DC characteristics of the fabricated ReRAM devices showed I-V curves under different compliance current. Gradual reset process attributed to a tunneling barrier layer during the DC switching process was observed.
Solid State Electronics 154 (2019) 31–35
D.K. Lee, et al.
Pulse width and amplitude were optimized and adjusted to realize longterm potentiation and depression of the fabricated ReRAM cell. Furthermore, both pre- and post-spike frequencies were modulated to observe the spike rate-dependent plasticity (SRDP). From the measurement results, the change of conductance increased as the spike frequency becomes higher, which is contributed to strengthening of synaptic weight from the higher spike rates [23]. By splitting the conductance level of ReRAM device, it can be expected to open the era of massive parallel neural network by implementing cross-point array. 2. Experiments The fabricated ReRAM device structure consists of TiN/HfO2/SiO2/ p+-Si stack. Complete fabrication process is as follows. After three steps of cleaning process including SPM, SC1 & 2 for bare silicon wafers, HF cleaning is followed to eliminate a native oxide. Since the bottom electrode of ReRAM device is silicon, electrical activation is necessary to allow the device for current flow. Dry oxidation of silicon wafer is processed to form 10 nm screen oxide. This aims to prevent damage of the silicon atoms. Then, ion implantation process is carried out using BF2+ ions with condition of 40 keV energy and 5 × 1015 cm−2 dose amount. The wafer then passed through a drive-in process to activate the impurities within it. 2.4 nm SiO2 layer was deposited using Medium Temperature Oxidation (MTO) process which functions as a tunneling barrier layer. As a switching layer, 4.4 nm HfO2 was formed using Atomic Layer Deposition (ALD) equipment. 100 nm TiN top electrode was deposited by the sputtering system and patterned in size of 100 μm × 100 μm using the Nikon stepper. After developing and etching the wafer, ReRAM device is finally obtained and taken for Transmission Electron Microscopy (TEM) image as shown in Fig. 1(a). Fig. 1(b) shows the EDS analysis of the fabricated device in the direction of top to bottom electrode. All electrical measurements were carried out using Keithley 4200-SCS parameter analyzer. PMU ultrafast I-V module was employed to investigate the transient response of the device.
Fig. 2. Diagram showing the biological connection of pre/post neuron and synapse (above) and illustration of synaptic device operation where the memristor receive pre/post spike via outside circuit to mimic the biological plasticity (bottom).
inhibit the current overshoot within the ReRAM device and prevent a permanent breakdown. As depicted in Fig. 3(a), different Icc have been used to modulate the thickness of the conductive filament and thus the current level flowing through the ReRAM device. By applying the DC bias in opposite polarity, which indicate the bipolar operation of the ReRAM device, reset process is observed in Fig. 3(a). Positive voltage is applied again through the top electrode to turn the device on, where the set voltage (VSET) is lower than VFORMING due to partial recovery from the ruptured conductive filament. After repeating the I-V measurement for thirty times, distribution of VFORMING, VSET and VRESET is plotted in Fig. 3(b). It can be seen that VSET has lower values compared to VFORMING, and VRESET is around – 3 V. Next, pulse operation was performed and analyzed for the purpose of synaptic behavior measurement. From previous researches [26,27], an analog property of synaptic devices is essential in order to split the conductance levels in multiple states and improve the accuracy of an object recognition. Thus, we optimized the pulse condition where the set pulse width was 1 μs and pulse amplitude was 5 V (−5 V for reset pulse with equal pulse amplitude) to achieve the gradual switching. As
3. Results and discussion Fig. 2 includes an illustration of synaptic transmission occurring within the biological neural network and electrical signal transmission in the synaptic device. From Fig. 2, pre/post spike is simultaneously applied to top and bottom electrode of the ReRAM device, from which a change of conductance will determine the strength of the synaptic device [24]. DC characteristics are shown in Fig. 3(a), where the voltage sweep ranges from 0 to 6 V. At the initial state, there is no filament formed within the switching layer, thus DC bias is applied from the top electrode to attract the oxygen ions and create the oxygen vacancies [25]. After reaching around 6 V, abrupt set process occurs under the limit of 10 μA compliance current (Icc). The purpose of applying Icc is to
TiN
1600
(a)
(b)
1400 1200
SiO2
Count/s
HfO2
Si
1000 800 600
N O Hf Si Ti
400 200 0 0.00
0.01
0.02
0.03
0.04
Distance [μm] Fig. 1. TEM image of the fabricated TiN/HfO2/SiO2/p+-Si stacked cell (a) and EDS analysis from the surface (top electrode) to bottom electrode (b). 32
Solid State Electronics 154 (2019) 31–35
D.K. Lee, et al.
10-3
600
(a)
10-4
(a) Conductance [μS]
Current [A]
10-5 10-6 10-7 -8
10
10-9 10-10 10-11 10-12 -4
-2
0
2
4
400
200
6
0
(b) 105
-2
0
2
10
20
30
Pulse Number [#]
Resistance [Ω]
Current [A]
Voltage [V] 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 -4
Measurement Results
4
(b)
RHRS
104
RLRS VREAD= 1 V @ Room Temperature
103
6
Voltage [V]
100
101
102
103
104
Time [s] Fig. 4. (a): Change of conductance level as the number of pulses are increasing. First half of pulses are applied to realize long-term potentiation while second half of them is for long-term depression. (b): retention data showing the longterm potentiation and depression, shown as RLRS and RHRS, respectively.
Tr Fig. 3. DC I-V curve of the fabricated ReRAM device (a) & the device without the tunneling barrier layer (b), and distribution of VFORMING, VSET and VRESET (c).
Twidth
Td
depicted in Fig. 4(a), gradual change of conductance for the ReRAM device can be observed. For the initial set pulses, conductance is gradually increasing which corresponds to the long-term potentiation while the next set of pulses are applied to decrease the conductance level for long-term depression. This result demonstrates the possibility of the fabricated ReRAM’s application as the synaptic device and implementation into the cross-point array. Although DC measurement showed abrupt change in both set and reset process, it is verified that realization of gradual switching is possible when optimizing the AC pulse conditions. Fig. 4(b) shows the retention data for both LRS and HRS to demonstrate the long term potentiation and depression, respectively. AC pulse shape and operation condition is shown in Fig. 5 and Table 1 for SRDP demonstration. Each color in the Fig. 5 indicates the label of the pulse shape. When modulating the pulse frequency, only the stationary time (Tstat, depicted in blue color) was changed while keeping the pulse width, amplitude and rising/fall time constant. The reason is to minimize the side effect that might make the ReRAM device easily exposed to variabilities by changing the pulse width. Applied pulse period and corresponding frequencies are depicted in Table 1. As the period of single pulse decreases, the corresponding frequency is increasing considering the reciprocal relation between the period and the frequency. Demonstration of SRDP was carried out as follow: applying the pulse with different frequencies to one terminal of the fabricated ReRAM device while fix the pulse frequency to the other terminal. In this way, one of terminal receives higher spike rates
Tf
Pulse amplitude (5 V) Tstat
Td: Pulse delay (1 ȝs)
Twidth: Pulse width (10 ȝs)
Tr: Rising time (0.2 ȝs)
Tf: Falling time (0.2 ȝs)
Tstat: Stationary time (0.6 ȝs a .6 ȝs) Fig. 5. Pulse shape used in this experiment for the synaptic behavior analysis.
Table 1 Period of the single pulse (μs) and corresponding frequencies (kHz) used for pre- and post-spikes applied to both bottom and top electrode of the fabricated ReRAM device.
33
Period (μs)
Pulse frequency (kHz)
20 19 18 17 16 15 14 13 12
50 52.63 55.56 58.82 62.5 66.67 71.43 76.92 83.33
Solid State Electronics 154 (2019) 31–35
D.K. Lee, et al.
80
90
(a)
Measured Fitting
80
|Δ G| (%)
|ΔG| (%)
70
Fixed pre-spike @ 20 kHz
60
55
3500
60
65
70
75
80
0 50
85
(b) 3
2
1500
Fixed post-spike @ 20 kHz
500
2500
60
65
70
75
65
70
75
80
85
80
Fixed post-spike @ 20 kHz
(b)
2000 1500 1000 500 0
0 55
60
5V 4V 3V
3000
y = 0.0688x - 11.095x + 645.48x – 13058
1000
55
3500
|ΔG| (%)
|Δ G| (%)
Fixed pre-spike @ 20 kHz
Post spike (kHz)
Measured Fitting
3000
50
40
10
Post spike (kHz)
2000
50
20
40
2500
60
30
y = 90.51×ln(x) - 317.7
50
(a)
5V 4V 3V
50
85
55
60
65
70
75
80
85
Pre spike (kHz)
Pre spike (kHz)
Fig. 7. Change of conductance with respect to the post- and pre-spikes under different pulse amplitudes. As the voltage level increases, general pattern of the conductance levels also increase for both LTD (a) and LTP (b).
Fig. 6. (a) and (b) depict the demonstration of SRDP. The change of conductance with respect to the pre- and post-spike frequencies is shown. The measured (red dot) and fitted line (blue dot line) are plotted for long-term depression (LTD) and long-term potentiation (LTP), respectively. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
As the next stage of experiment, we investigated the impact of pulse amplitude modulation on the fabricated TiN/HfO2/SiO2/p+-Si stacked device. Fig. 7(a) and (b) depict the graphs plotted with data of conductance change with respect to the applied pulses to bottom and top electrodes, respectively. From the Fig. 7(a), the pulse amplitude with 3 V only contributes to a maximum 50% of the weight change for the highest post-spike frequency which is not significant. As the pulse amplitude rises from 3, 4 to 5 V, the change of conductance also increases in average rise rate of 20%. For the LTP which is depicted in Fig. 7(b), the weight changes among different pulse amplitudes are similar for the pre-spike rates below 65 kHz, but the difference becomes obvious above a specific frequency, which indicates there exists a threshold for LTP realization of the fabricated ReRAM device. For both cases of LTP and LTD, it was proven to show the gradual switching characteristics under the AC pulse operation and SRDP demonstration has been performed. From the result, it is expected to implement the fabricated ReRAM device into the massive array and apply as a neuromorphic computing system.
compared to the other terminal and thus these difference will cause the change of conductance of the device. Since both pre- and post-synapse receives spikes with different frequencies asynchronously [28], we modulated the pre- and post-spike with multiple frequencies to observe the degree of conductance change for LTD and LTP. Fig. 6(a) and (b) present the change of conductance levels with increasing pre- and postspike frequencies. For the Fig. 6(a), the post-spike frequency was modulated (as stated in the Table 1) while fixing the pre-spike to 50 kHz so that the bottom electrode of the ReRAM device always receives signals with lower frequencies compared to those applied to the top electrode. According to the literature [29], inhibition and excitation of the central neural system depends on spike rate difference applied to pre- and post-synapses. If the spike rates to the post-synapse is higher than those to the pre-synapse, then long-term depression (LTD) is realized as shown in the Fig. 6(a). Maximum conductance change is 80% when the post-spike frequency is above 85 kHz. Curve fitting of the measured data is plotted with a natural logarithmic equation. On the other hand, pre-spike frequencies were varied while fixing the postspike rates to 50 kHz to demonstrate the long-term potentiation (LTP). Fig. 6(b) shows the results of conductance change with respect to modulation of pre-spike frequencies. The measured data of the Fig. 6(b) is fitted with a cubic equation. Unlike LTD, change of conductance for realizing LTP is much larger. For the spike rate higher than 85 kHz, the weight change of the ReRAM device reaches 3500%, which is a dramatic difference compared to that of LTD realization. Similar to STDP mechanism [30], SRDP is one of essential mechanism that determines a strength of neuronal connection. It requires precise control of the relative frequency between input and output signals. For both LTP and LTD, the level of conductance change rose and permanent transition to higher and lower conductive state is clearly seen with repetitive application of pulses.
4. Conclusion In this work, we analyzed the synaptic behaviors of the fabricated TiN/HfO2/SiO2/p+-Si stacked cell. ReRAM device with the tunneling barrier layer (SiO2) and switching layer (HfO2) showed DC characteristics under different compliance current (Icc). By modulating the compliance current, the overshoot current level can be controlled to prevent the breakdown of the ReRAM device. To prevent the creation of variability to the ReRAM device, the stationary time of the applied pulse has been changed while keeping the pulse width constant. By doing so, different pulse frequencies were applied to both top and bottom electrode of the fabricated ReRAM device to demonstrate the SRDP function. Gradual switching phenomenon under the pulse operation seen from the measurement imply the future usage as a synaptic device for neuromorphic computing application. 34
Solid State Electronics 154 (2019) 31–35
D.K. Lee, et al.
Acknowledgements
[23] Milo V, et al. A 4-transistors/1-resistor hybrid synapse based on resistive switching memory (RRAM) capable of spike-rate-dependent plasticity (SRDP). IEEE T VLSI SYST 2018:1–10. [24] Maass W. Networks of spiking neurons: the third generation of neural network models. Neural networks 1997;10(9):1659–71. [25] Wong HSP, et al. Metal–oxide RRAM. Proc. IEEE 2012;100(6):1951–70. [26] Long B, Li Y, Jha R. Switching characteristics of Ru/HfO2/TiO2−x/Ru RRAM devices for digital and analog nonvolatile memory applications. IEEE Electron Dev Lett 2012;33(5):706–8. [27] Snider G. Spike-timing-dependent learning in memristive nanodevices. NANOARCH; 2008:85–92. [28] Jo S, et al. Nanoscale memristor device as synapse in neuromorphic systems. Nano Lett 2010;10(4):1297–301. [29] Galarreta M, Hestrin S. Frequency-dependent synaptic depression and the balance of excitation and inhibition in the neocortex. Nat Neurosci 1998;1(7):587–94. [30] Takeo O, et al. Short-term plasticity and long-term potentiation mimicked in single inorganic synapses. Nat Mater 2011:591–5.
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Ministry of Science, ICT & Future Planning (2018R1A2A1A05023517) and also supported in part by the Brain Korea 21 Plus Program in 2018. References [1] Waser R, Dittmann R, Staikov G, Szot K. Redox-based resistive switching memories – nanoionic mechanisms, prospects, and challenges. Adv Mater 2009;21:2632–63. [2] Waser R, Aono M. Nanoionics-based resistive switching memories. Nat Mater 2007;6:833–40. [3] Sawa A. Resistive switching in transition metal oxides. Materials Today 2008;11(6). 28-26. [4] Lin P, Pi S, Xia QF. 3D integration of planar crossbar memristive devices with CMOS substrate. Nanotechnology 2014;25:405202. [5] Chen FT, Chen Y-S, Wu T-Y, Ku T-K. Write scheme allowing reduced LRS nonlinearity requirement in a 3D-RRAM array with selector-less 1TNR architecture. IEEE Electron Dev Lett 2014;35(2):223–5. [6] Yang Y, Gao P, Gaba S, Chang T, Pan X, Lu W. Observation of conducting filament growth in nanoscale resistive memories. Nat Commu 2012;732(3):10.1038. [7] Garbin D, et al. HfO2-based OxRAM devices as synapses for convolutional neural networks. IEEE Trans Electron Dev 2015;62(8):2494–501. [8] Kuzum D, Yu SM, Wong HSP. Synaptic electronics: materials, devices and applications. Nanotechnology 2013;24(38):382001. [9] Park S, et al. RRAM-based synapse for neuromorphic system with pattern recognition function. IEEE IEDM Tech Dig 2012. P. 10.2.1-4. [10] Yu S, Gao B, Fang Z, Yu H, Kang J, Wong H. Stochastic learning in oxide binary synaptic device for neuromorphic computing. Front Neurosci 2013;7(10):3388. [11] Milo V, et al. Demonstration of hybrid CMOS/RRAM neural networks with spike time/rate-dependent plasticity. IEEE IEDM Tech Dig 2016. P. 16.8.1-4. [12] Wang Z, et al. Memristors with diffusive dynamics as synaptic emulators for neuromorphic computing. Nat Mater 2016;16(1):101–10. [13] Biological Zhou L, et al. Spiking synapse constructed from solution processed bimetal core-shell nanoparticle based composites. Small 2018. 1800288-11800288-10. [14] Barbera L, Vuillaume S, Ailbart F. Filamentary switching: synaptic plasticity through device volatility. ACS Nano 2015;9(1):941–9. [15] Ambrogio S, et al. Neuromorphic learning and recognition with one-transistor-oneresistor synapses and bistable metal oxide RRAM. IEEE Trans Electron Dev 2016;63(4):1508–15. [16] Rachmuth G, Shouval H, Bear M, Poon C-S. A biophysically-based neuromorphic model of spike rate- and timing-dependent plasticity. Proc Natl Acad Sci USA 2011;108(49):1266–74. [17] Yu S, et al. An electronic synapse device based on metal oxide resistive switching memory for neuromorphic computation. IEEE Trans Electron Dev 2011;58(8):2729–37. [18] Park S, et al. Nanoscale RRAM-based synaptic electronics: toward a neuromorphic computing device. Nanotechnology 2013;24(38). 380096-1-380096-6. [19] Masoud A, et al. Reproducible and reliable resistive switching behaviors of AlOX/ HfOX bilayer structures with Al electrode by atomic layer deposition. RSC Adv 2017;7:16704–8. [20] Dou C, et al. Resistive switching behavior of a CeO2 based ReRAM cell incorporated with Si buffer layer. Microrel 2011;52:688–91. [21] Umesh C, et al. Mechanism of nonlinear switching in HfO2-based crossbar RRAM with inserting large bandgap tunneling barrier layer. IEEE Trans Electron Dev 2015;62(11):3665–70. [22] Liu CC, et al. A memristor crossbar based computing engine optimized for high speed and accuracy. IEEE T VLSI SYST 2016:110–5.
Dong Keun Lee received his B.S. and M.S. degrees in Electronic Engineering from the Hong Kong University of Science and Technology, Kowloon Bay, Hong Kong, and the Seoul National University in 2014 and 2017, respectively, where he is currently pursuing the Ph.D. degree. His research interest includes resistive switching random access memory and its application to synaptic devices.
Byung-Gook Park received his B.S. and M.S. degrees in electronics engineering from Seoul National University (SNU) in 1982 and 1984, respectively, and his Ph. D. degree in electrical engineering from Stanford University in 1990. From 1990 to 1993, he worked at the AT&T Bell Laboratories, where he contributed to the development of 0.1 micron CMOS and its characterization. From 1993 to 1994, he was with Texas Instruments, developing 0.25 micron CMOS. In 1994, he joined SNU as an assistant professor in the School of Electrical Engineering (SoEE), where he is currently a professor. In 2002, he worked at Stanford University as a visiting professor, on his sabbatical leave from SNU. He led the Inter-university Semiconductor Research Center (ISRC) at SNU as the director from 2008 to 2010. His current research interests include the design and fabrication of nanoscale CMOS, flash memories, silicon quantum devices and organic thin film transistors. He has authored and co-authored over 1000 research papers in journals and conferences. Prof. Park has served as a committee member on several international conferences including Microprocesses and Nanotechnology, IEEE International Electron Devices Meeting, International Conference on Solid State Devices and Materials, and IEEE Silicon Nanoelectronics Workshop and served as an Editor of IEEE Electron Device Letters. He received “Best Teacher” Award from SoEE in 1997, Doyeon Award for Creative Research from ISRC in 2003, Haedong Parper Award from the Institude of Electronic Engineers of Korea (IEEK) in 2005, Educational Award from College of Engineering, SNU, in 2006, Haedong Research Award from IEEK in 2008, Nano Research Innovation Award from the Ministry of Science, ICT and Future Planning of Korea in 2013, and Research Excellence Award from Seoul National University in 2015.
35
Contents lists available at ScienceDirect
Solid State Electronics journal homepage: www.elsevier.com/locate/sse
Synaptic behaviors of HfO2 ReRAM by pulse frequency modulation a
a
a
a
T
a
Dong Keun Lee , Min-Hwi Kim , Tae-Hyeon Kim , Suhyun Bang , Yeon-Joon Choi , ⁎ Sungjun Kimb, Seongjae Choc, Byung-Gook Parka, a Inter-university Semiconductor Research Center (ISRC) and the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Republic of Korea b School of Electronics Engineering, Chungbuk National University, Cheongju 28644, Republic of Korea c Department of Electronics Engineering, Gachon University, 1342 Seongnamdaero, Sujeong-gu, Seongnam-si, Gyeonggi-do 13120, Republic of Korea
A R T I C LE I N FO
A B S T R A C T
Keywords: Tunneling barrier layer Resistive-switching random-access memory Potentiation Depression Synaptic plasticity Spike rate-dependent plasticity (SRDP)
A resistive switching random-access memory (ReRAM) device with TiN/HfO2/SiO2/p+-Si stack is analyzed for synaptic behavior. Fabricated RRAM device stack consists of heavily doped p-type silicon bottom electrode (BE), HfO2 as a switching layer, SiO2 as a tunneling barrier layer and TiN as a top electrode (TE). The RRAM cell successfully shows I-V curves including SET and RESET operations in DC sweep mode. By inserting a SiO2 tunneling barrier layer, gradual switching characteristics are obtained by pulse operation. By optimizing the pulse scheme applied to the device, biological synaptic plasticity of long-term potentiation and depression is demonstrated. Finally, spike rate-dependent plasticity (SRDP) learning rule is realized by applying pulses with different frequencies to both terminals of the ReRAM device.
1. Introduction Resistive-switching memory (ReRAM) devices have been regarded as one of next-generation memories due to its fast speed, CMOS compatibility and ultralow switching energy [1–6]. These superiorities make the ReRAM devices strong candidates to replace conventional non-volatile NAND Flash memories. Besides its possibility as a storage class memory, ReRAM device also receives great attention as a synaptic device that emulates biological functions due to its 2-terminal structure, feasibility of implementing cross-point array and gradual switching operation [7–9]. Possibility of massive data processing by parallelism using the ReRAM array give rise to an expectation to replace current von Neumann computing that utilize sequential process and consume lots of power [10]. By adopting numerous advantages of ReRAM devices including modulation of multiple conductance levels and low operation power, various bio-inspired learning rules including spike timing-dependent plasticity (STDP) and spike rate-dependent plasticity (SRDP) are under the extensive research to realize long-term potentiation (LTP) and depression (LTD) [11]. Another form of memristive device, conductive bridge RAM (CBRAM) is employed to realize paired-pulse facilitation/depression (PPF/PPD) by modulating the pulse stimulation [12]. It is reported that both PPF and PPD is a shortterm biological learning rules that are mimicked using a nanoparticlebased ReRAM [13].
⁎
Corresponding author. E-mail address: [email protected] (B.-G. Park).
https://doi.org/10.1016/j.sse.2019.02.008
Available online 19 February 2019 0038-1101/ © 2019 Published by Elsevier Ltd.
In this work, the spike rate-dependent plasticity (SRDP) is demonstrated by modulating a pulse frequency using fabricated TiN/HfO2/ SiO2/p+-Si stacked ReRAM device. Although recent trend of emulating the synaptic learning rule by ReRAM devices is STDP [14,15], there is a report that SRDP is more realistic way of mimicking a biological neural network compared to STDP because of its random input/output spike rates [16]. According to the literature, STDP can only sustain both LTP and LTD under a synchronous input spike which does not suit for a real neural network operation. Unlike other experiments where most of synaptic behavior measurement is carried out via metal-insulator-metal (MIM) structure [17,18], metal-insulator-silicon (MIS) structured ReRAM device was used in this experiment which is CMOS compatible. There are reports regarding tunneling barrier layer inserted ReRAM with low forming voltage and operation power that are essential to implement in neuromorphic system [19–21]. Compared to the device without tunneling barrier layer, the proposed device with TiN/HfO2/ SiO2/p+-Si stack allows nonlinear switching behavior by electron tunneling mechanism inside the SiO2 layer, thereby reducing the leakage current in low voltage regime. As a parallelism rises as one of essential issues for implementation of a neural network [22], the proposed device can reduce sneak path to increase pattern recognition accuracy. DC characteristics of the fabricated ReRAM devices showed I-V curves under different compliance current. Gradual reset process attributed to a tunneling barrier layer during the DC switching process was observed.
Solid State Electronics 154 (2019) 31–35
D.K. Lee, et al.
Pulse width and amplitude were optimized and adjusted to realize longterm potentiation and depression of the fabricated ReRAM cell. Furthermore, both pre- and post-spike frequencies were modulated to observe the spike rate-dependent plasticity (SRDP). From the measurement results, the change of conductance increased as the spike frequency becomes higher, which is contributed to strengthening of synaptic weight from the higher spike rates [23]. By splitting the conductance level of ReRAM device, it can be expected to open the era of massive parallel neural network by implementing cross-point array. 2. Experiments The fabricated ReRAM device structure consists of TiN/HfO2/SiO2/ p+-Si stack. Complete fabrication process is as follows. After three steps of cleaning process including SPM, SC1 & 2 for bare silicon wafers, HF cleaning is followed to eliminate a native oxide. Since the bottom electrode of ReRAM device is silicon, electrical activation is necessary to allow the device for current flow. Dry oxidation of silicon wafer is processed to form 10 nm screen oxide. This aims to prevent damage of the silicon atoms. Then, ion implantation process is carried out using BF2+ ions with condition of 40 keV energy and 5 × 1015 cm−2 dose amount. The wafer then passed through a drive-in process to activate the impurities within it. 2.4 nm SiO2 layer was deposited using Medium Temperature Oxidation (MTO) process which functions as a tunneling barrier layer. As a switching layer, 4.4 nm HfO2 was formed using Atomic Layer Deposition (ALD) equipment. 100 nm TiN top electrode was deposited by the sputtering system and patterned in size of 100 μm × 100 μm using the Nikon stepper. After developing and etching the wafer, ReRAM device is finally obtained and taken for Transmission Electron Microscopy (TEM) image as shown in Fig. 1(a). Fig. 1(b) shows the EDS analysis of the fabricated device in the direction of top to bottom electrode. All electrical measurements were carried out using Keithley 4200-SCS parameter analyzer. PMU ultrafast I-V module was employed to investigate the transient response of the device.
Fig. 2. Diagram showing the biological connection of pre/post neuron and synapse (above) and illustration of synaptic device operation where the memristor receive pre/post spike via outside circuit to mimic the biological plasticity (bottom).
inhibit the current overshoot within the ReRAM device and prevent a permanent breakdown. As depicted in Fig. 3(a), different Icc have been used to modulate the thickness of the conductive filament and thus the current level flowing through the ReRAM device. By applying the DC bias in opposite polarity, which indicate the bipolar operation of the ReRAM device, reset process is observed in Fig. 3(a). Positive voltage is applied again through the top electrode to turn the device on, where the set voltage (VSET) is lower than VFORMING due to partial recovery from the ruptured conductive filament. After repeating the I-V measurement for thirty times, distribution of VFORMING, VSET and VRESET is plotted in Fig. 3(b). It can be seen that VSET has lower values compared to VFORMING, and VRESET is around – 3 V. Next, pulse operation was performed and analyzed for the purpose of synaptic behavior measurement. From previous researches [26,27], an analog property of synaptic devices is essential in order to split the conductance levels in multiple states and improve the accuracy of an object recognition. Thus, we optimized the pulse condition where the set pulse width was 1 μs and pulse amplitude was 5 V (−5 V for reset pulse with equal pulse amplitude) to achieve the gradual switching. As
3. Results and discussion Fig. 2 includes an illustration of synaptic transmission occurring within the biological neural network and electrical signal transmission in the synaptic device. From Fig. 2, pre/post spike is simultaneously applied to top and bottom electrode of the ReRAM device, from which a change of conductance will determine the strength of the synaptic device [24]. DC characteristics are shown in Fig. 3(a), where the voltage sweep ranges from 0 to 6 V. At the initial state, there is no filament formed within the switching layer, thus DC bias is applied from the top electrode to attract the oxygen ions and create the oxygen vacancies [25]. After reaching around 6 V, abrupt set process occurs under the limit of 10 μA compliance current (Icc). The purpose of applying Icc is to
TiN
1600
(a)
(b)
1400 1200
SiO2
Count/s
HfO2
Si
1000 800 600
N O Hf Si Ti
400 200 0 0.00
0.01
0.02
0.03
0.04
Distance [μm] Fig. 1. TEM image of the fabricated TiN/HfO2/SiO2/p+-Si stacked cell (a) and EDS analysis from the surface (top electrode) to bottom electrode (b). 32
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10-3
600
(a)
10-4
(a) Conductance [μS]
Current [A]
10-5 10-6 10-7 -8
10
10-9 10-10 10-11 10-12 -4
-2
0
2
4
400
200
6
0
(b) 105
-2
0
2
10
20
30
Pulse Number [#]
Resistance [Ω]
Current [A]
Voltage [V] 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 -4
Measurement Results
4
(b)
RHRS
104
RLRS VREAD= 1 V @ Room Temperature
103
6
Voltage [V]
100
101
102
103
104
Time [s] Fig. 4. (a): Change of conductance level as the number of pulses are increasing. First half of pulses are applied to realize long-term potentiation while second half of them is for long-term depression. (b): retention data showing the longterm potentiation and depression, shown as RLRS and RHRS, respectively.
Tr Fig. 3. DC I-V curve of the fabricated ReRAM device (a) & the device without the tunneling barrier layer (b), and distribution of VFORMING, VSET and VRESET (c).
Twidth
Td
depicted in Fig. 4(a), gradual change of conductance for the ReRAM device can be observed. For the initial set pulses, conductance is gradually increasing which corresponds to the long-term potentiation while the next set of pulses are applied to decrease the conductance level for long-term depression. This result demonstrates the possibility of the fabricated ReRAM’s application as the synaptic device and implementation into the cross-point array. Although DC measurement showed abrupt change in both set and reset process, it is verified that realization of gradual switching is possible when optimizing the AC pulse conditions. Fig. 4(b) shows the retention data for both LRS and HRS to demonstrate the long term potentiation and depression, respectively. AC pulse shape and operation condition is shown in Fig. 5 and Table 1 for SRDP demonstration. Each color in the Fig. 5 indicates the label of the pulse shape. When modulating the pulse frequency, only the stationary time (Tstat, depicted in blue color) was changed while keeping the pulse width, amplitude and rising/fall time constant. The reason is to minimize the side effect that might make the ReRAM device easily exposed to variabilities by changing the pulse width. Applied pulse period and corresponding frequencies are depicted in Table 1. As the period of single pulse decreases, the corresponding frequency is increasing considering the reciprocal relation between the period and the frequency. Demonstration of SRDP was carried out as follow: applying the pulse with different frequencies to one terminal of the fabricated ReRAM device while fix the pulse frequency to the other terminal. In this way, one of terminal receives higher spike rates
Tf
Pulse amplitude (5 V) Tstat
Td: Pulse delay (1 ȝs)
Twidth: Pulse width (10 ȝs)
Tr: Rising time (0.2 ȝs)
Tf: Falling time (0.2 ȝs)
Tstat: Stationary time (0.6 ȝs a .6 ȝs) Fig. 5. Pulse shape used in this experiment for the synaptic behavior analysis.
Table 1 Period of the single pulse (μs) and corresponding frequencies (kHz) used for pre- and post-spikes applied to both bottom and top electrode of the fabricated ReRAM device.
33
Period (μs)
Pulse frequency (kHz)
20 19 18 17 16 15 14 13 12
50 52.63 55.56 58.82 62.5 66.67 71.43 76.92 83.33
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80
90
(a)
Measured Fitting
80
|Δ G| (%)
|ΔG| (%)
70
Fixed pre-spike @ 20 kHz
60
55
3500
60
65
70
75
80
0 50
85
(b) 3
2
1500
Fixed post-spike @ 20 kHz
500
2500
60
65
70
75
65
70
75
80
85
80
Fixed post-spike @ 20 kHz
(b)
2000 1500 1000 500 0
0 55
60
5V 4V 3V
3000
y = 0.0688x - 11.095x + 645.48x – 13058
1000
55
3500
|ΔG| (%)
|Δ G| (%)
Fixed pre-spike @ 20 kHz
Post spike (kHz)
Measured Fitting
3000
50
40
10
Post spike (kHz)
2000
50
20
40
2500
60
30
y = 90.51×ln(x) - 317.7
50
(a)
5V 4V 3V
50
85
55
60
65
70
75
80
85
Pre spike (kHz)
Pre spike (kHz)
Fig. 7. Change of conductance with respect to the post- and pre-spikes under different pulse amplitudes. As the voltage level increases, general pattern of the conductance levels also increase for both LTD (a) and LTP (b).
Fig. 6. (a) and (b) depict the demonstration of SRDP. The change of conductance with respect to the pre- and post-spike frequencies is shown. The measured (red dot) and fitted line (blue dot line) are plotted for long-term depression (LTD) and long-term potentiation (LTP), respectively. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
As the next stage of experiment, we investigated the impact of pulse amplitude modulation on the fabricated TiN/HfO2/SiO2/p+-Si stacked device. Fig. 7(a) and (b) depict the graphs plotted with data of conductance change with respect to the applied pulses to bottom and top electrodes, respectively. From the Fig. 7(a), the pulse amplitude with 3 V only contributes to a maximum 50% of the weight change for the highest post-spike frequency which is not significant. As the pulse amplitude rises from 3, 4 to 5 V, the change of conductance also increases in average rise rate of 20%. For the LTP which is depicted in Fig. 7(b), the weight changes among different pulse amplitudes are similar for the pre-spike rates below 65 kHz, but the difference becomes obvious above a specific frequency, which indicates there exists a threshold for LTP realization of the fabricated ReRAM device. For both cases of LTP and LTD, it was proven to show the gradual switching characteristics under the AC pulse operation and SRDP demonstration has been performed. From the result, it is expected to implement the fabricated ReRAM device into the massive array and apply as a neuromorphic computing system.
compared to the other terminal and thus these difference will cause the change of conductance of the device. Since both pre- and post-synapse receives spikes with different frequencies asynchronously [28], we modulated the pre- and post-spike with multiple frequencies to observe the degree of conductance change for LTD and LTP. Fig. 6(a) and (b) present the change of conductance levels with increasing pre- and postspike frequencies. For the Fig. 6(a), the post-spike frequency was modulated (as stated in the Table 1) while fixing the pre-spike to 50 kHz so that the bottom electrode of the ReRAM device always receives signals with lower frequencies compared to those applied to the top electrode. According to the literature [29], inhibition and excitation of the central neural system depends on spike rate difference applied to pre- and post-synapses. If the spike rates to the post-synapse is higher than those to the pre-synapse, then long-term depression (LTD) is realized as shown in the Fig. 6(a). Maximum conductance change is 80% when the post-spike frequency is above 85 kHz. Curve fitting of the measured data is plotted with a natural logarithmic equation. On the other hand, pre-spike frequencies were varied while fixing the postspike rates to 50 kHz to demonstrate the long-term potentiation (LTP). Fig. 6(b) shows the results of conductance change with respect to modulation of pre-spike frequencies. The measured data of the Fig. 6(b) is fitted with a cubic equation. Unlike LTD, change of conductance for realizing LTP is much larger. For the spike rate higher than 85 kHz, the weight change of the ReRAM device reaches 3500%, which is a dramatic difference compared to that of LTD realization. Similar to STDP mechanism [30], SRDP is one of essential mechanism that determines a strength of neuronal connection. It requires precise control of the relative frequency between input and output signals. For both LTP and LTD, the level of conductance change rose and permanent transition to higher and lower conductive state is clearly seen with repetitive application of pulses.
4. Conclusion In this work, we analyzed the synaptic behaviors of the fabricated TiN/HfO2/SiO2/p+-Si stacked cell. ReRAM device with the tunneling barrier layer (SiO2) and switching layer (HfO2) showed DC characteristics under different compliance current (Icc). By modulating the compliance current, the overshoot current level can be controlled to prevent the breakdown of the ReRAM device. To prevent the creation of variability to the ReRAM device, the stationary time of the applied pulse has been changed while keeping the pulse width constant. By doing so, different pulse frequencies were applied to both top and bottom electrode of the fabricated ReRAM device to demonstrate the SRDP function. Gradual switching phenomenon under the pulse operation seen from the measurement imply the future usage as a synaptic device for neuromorphic computing application. 34
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Acknowledgements
[23] Milo V, et al. A 4-transistors/1-resistor hybrid synapse based on resistive switching memory (RRAM) capable of spike-rate-dependent plasticity (SRDP). IEEE T VLSI SYST 2018:1–10. [24] Maass W. Networks of spiking neurons: the third generation of neural network models. Neural networks 1997;10(9):1659–71. [25] Wong HSP, et al. Metal–oxide RRAM. Proc. IEEE 2012;100(6):1951–70. [26] Long B, Li Y, Jha R. Switching characteristics of Ru/HfO2/TiO2−x/Ru RRAM devices for digital and analog nonvolatile memory applications. IEEE Electron Dev Lett 2012;33(5):706–8. [27] Snider G. Spike-timing-dependent learning in memristive nanodevices. NANOARCH; 2008:85–92. [28] Jo S, et al. Nanoscale memristor device as synapse in neuromorphic systems. Nano Lett 2010;10(4):1297–301. [29] Galarreta M, Hestrin S. Frequency-dependent synaptic depression and the balance of excitation and inhibition in the neocortex. Nat Neurosci 1998;1(7):587–94. [30] Takeo O, et al. Short-term plasticity and long-term potentiation mimicked in single inorganic synapses. Nat Mater 2011:591–5.
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Ministry of Science, ICT & Future Planning (2018R1A2A1A05023517) and also supported in part by the Brain Korea 21 Plus Program in 2018. References [1] Waser R, Dittmann R, Staikov G, Szot K. Redox-based resistive switching memories – nanoionic mechanisms, prospects, and challenges. Adv Mater 2009;21:2632–63. [2] Waser R, Aono M. Nanoionics-based resistive switching memories. Nat Mater 2007;6:833–40. [3] Sawa A. Resistive switching in transition metal oxides. Materials Today 2008;11(6). 28-26. [4] Lin P, Pi S, Xia QF. 3D integration of planar crossbar memristive devices with CMOS substrate. Nanotechnology 2014;25:405202. [5] Chen FT, Chen Y-S, Wu T-Y, Ku T-K. Write scheme allowing reduced LRS nonlinearity requirement in a 3D-RRAM array with selector-less 1TNR architecture. IEEE Electron Dev Lett 2014;35(2):223–5. [6] Yang Y, Gao P, Gaba S, Chang T, Pan X, Lu W. Observation of conducting filament growth in nanoscale resistive memories. Nat Commu 2012;732(3):10.1038. [7] Garbin D, et al. HfO2-based OxRAM devices as synapses for convolutional neural networks. IEEE Trans Electron Dev 2015;62(8):2494–501. [8] Kuzum D, Yu SM, Wong HSP. Synaptic electronics: materials, devices and applications. Nanotechnology 2013;24(38):382001. [9] Park S, et al. RRAM-based synapse for neuromorphic system with pattern recognition function. IEEE IEDM Tech Dig 2012. P. 10.2.1-4. [10] Yu S, Gao B, Fang Z, Yu H, Kang J, Wong H. Stochastic learning in oxide binary synaptic device for neuromorphic computing. Front Neurosci 2013;7(10):3388. [11] Milo V, et al. Demonstration of hybrid CMOS/RRAM neural networks with spike time/rate-dependent plasticity. IEEE IEDM Tech Dig 2016. P. 16.8.1-4. [12] Wang Z, et al. Memristors with diffusive dynamics as synaptic emulators for neuromorphic computing. Nat Mater 2016;16(1):101–10. [13] Biological Zhou L, et al. Spiking synapse constructed from solution processed bimetal core-shell nanoparticle based composites. Small 2018. 1800288-11800288-10. [14] Barbera L, Vuillaume S, Ailbart F. Filamentary switching: synaptic plasticity through device volatility. ACS Nano 2015;9(1):941–9. [15] Ambrogio S, et al. Neuromorphic learning and recognition with one-transistor-oneresistor synapses and bistable metal oxide RRAM. IEEE Trans Electron Dev 2016;63(4):1508–15. [16] Rachmuth G, Shouval H, Bear M, Poon C-S. A biophysically-based neuromorphic model of spike rate- and timing-dependent plasticity. Proc Natl Acad Sci USA 2011;108(49):1266–74. [17] Yu S, et al. An electronic synapse device based on metal oxide resistive switching memory for neuromorphic computation. IEEE Trans Electron Dev 2011;58(8):2729–37. [18] Park S, et al. Nanoscale RRAM-based synaptic electronics: toward a neuromorphic computing device. Nanotechnology 2013;24(38). 380096-1-380096-6. [19] Masoud A, et al. Reproducible and reliable resistive switching behaviors of AlOX/ HfOX bilayer structures with Al electrode by atomic layer deposition. RSC Adv 2017;7:16704–8. [20] Dou C, et al. Resistive switching behavior of a CeO2 based ReRAM cell incorporated with Si buffer layer. Microrel 2011;52:688–91. [21] Umesh C, et al. Mechanism of nonlinear switching in HfO2-based crossbar RRAM with inserting large bandgap tunneling barrier layer. IEEE Trans Electron Dev 2015;62(11):3665–70. [22] Liu CC, et al. A memristor crossbar based computing engine optimized for high speed and accuracy. IEEE T VLSI SYST 2016:110–5.
Dong Keun Lee received his B.S. and M.S. degrees in Electronic Engineering from the Hong Kong University of Science and Technology, Kowloon Bay, Hong Kong, and the Seoul National University in 2014 and 2017, respectively, where he is currently pursuing the Ph.D. degree. His research interest includes resistive switching random access memory and its application to synaptic devices.
Byung-Gook Park received his B.S. and M.S. degrees in electronics engineering from Seoul National University (SNU) in 1982 and 1984, respectively, and his Ph. D. degree in electrical engineering from Stanford University in 1990. From 1990 to 1993, he worked at the AT&T Bell Laboratories, where he contributed to the development of 0.1 micron CMOS and its characterization. From 1993 to 1994, he was with Texas Instruments, developing 0.25 micron CMOS. In 1994, he joined SNU as an assistant professor in the School of Electrical Engineering (SoEE), where he is currently a professor. In 2002, he worked at Stanford University as a visiting professor, on his sabbatical leave from SNU. He led the Inter-university Semiconductor Research Center (ISRC) at SNU as the director from 2008 to 2010. His current research interests include the design and fabrication of nanoscale CMOS, flash memories, silicon quantum devices and organic thin film transistors. He has authored and co-authored over 1000 research papers in journals and conferences. Prof. Park has served as a committee member on several international conferences including Microprocesses and Nanotechnology, IEEE International Electron Devices Meeting, International Conference on Solid State Devices and Materials, and IEEE Silicon Nanoelectronics Workshop and served as an Editor of IEEE Electron Device Letters. He received “Best Teacher” Award from SoEE in 1997, Doyeon Award for Creative Research from ISRC in 2003, Haedong Parper Award from the Institude of Electronic Engineers of Korea (IEEK) in 2005, Educational Award from College of Engineering, SNU, in 2006, Haedong Research Award from IEEK in 2008, Nano Research Innovation Award from the Ministry of Science, ICT and Future Planning of Korea in 2013, and Research Excellence Award from Seoul National University in 2015.
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