Synthesis of optimal TANT networks

Comp•t. & Elect. Engng Vol. 5, pp. 123-1M © Perlptmon Press Ltd.. 1978. Printed in Great Britain

SYNTHESIS

0045.-'/9~/7511M01-01231102.00/0

OF OPTIMAL TANT NETWORKS?

JAMES E. LAYTON Computer Products Department, Systems Research, Applied Automation, Bartlesville. OK 74004, U.S.A.

and JAMES R. ROWLAND and JOHN M. ACKEN School of Electrical Engineering and Center for Systems Science, Oklahoma State University, Stillwater, OK 74074, U.S.A.

(Received 21 October 1977; received/or publication 14 December 1977) Abstraet--A new synthesis algorithm is developed for TANT networks, i.e. three-level NAND-gate combinational switching networks having only uncomplemented inputs. Pertinent theorems are introduced at the outset to provide a firm theoretical basis for the developed procedure. Thereafter, a detailed discussion of the synthesis algorithm is given in flowchart form for step-by-step instructions. Three examples are provided to illustrate the basic design procedure. A computer-aided design (CAD) software package exists for this algorithm, and its extension for handling hazardless and/or multiple-output TANT networks is suggested. The need for extending the problem definition for sequential TANT network synthesis is identified. INTRODUCTION

A variety of design criteria must be considered in the design of logic switching circuits. The more important criteria are usually minimizing propagation time and minimizing the number of component packages in realizing the desired circuit. A restriction sometimes imposed is that only uncomplemented, i.e. true, variables are available as inputs. The logic devices to be used in the design procedure of this paper will be NAND gates, but a straightforward extension permits the use of all NOR gates as well [1-5]. Three-level NAND logic networks with true inputs have been referred to as TANT networks[l]. Since propagation time is directly related to the number of switching levels and, furthermore, since any switching function can be realized with three levels of switching logic, the procedure to be developed in this paper is restricted to three switching levels. However, the problem of achieving a minimum package count is not as straightforward. The packaging standards introduced by integrated circuit technology quite often dictate that a selective process be carried out between different realizations of the same switching function. This requirement can dictate in some cases the use of a less-than-minimal number of logic gates and/or inputs in order to achieve a minimum package count. For example, this problem occurs when several independent switching functions are to be located in close physical proximity. On the other hand, if an integrated circuit were being designed, then minimum-gate, minimum-input realizations would probably be the primary concern. Since cases where minimum-gate, minimum-input realizations do not achieve a minimum package count are likely to occur less frequently in practice, the objective here will be to generate minimum-gate, minimum-input realizations of TANT networks. Previous work on NAND and NOR network synthesis has been based on double complement technique, the transform method, and the map factoring approach[2, 3]. Gimpel[4] developed a double complement technique similar to the Quine-McCluskey algorithm for two-level AND/OR networks [5-7] with certain extensions involving a prime implicant cover and closure (CC) table. Decomposition solutions have been obtained by utilizing the double complement approach for networks having various constraints [8--l l]. Koh[12] developed a technique based on first obtaining essential prime implicants and then generating other useful prime implicants. Frackowiak [13] extended Gimpel's results to yield minimal hazardless TANT networks. Baugh et a/.[14] used integer programming[15-17] to obtain optimal NOR/OR networks for a large number of cases and made comparisons with earlier tabulated results[18]. ~'This research was supported, in part, by National Science Foundation Departmental Science Grant GU-3160. CAE~Vol.5. No. ~-8

123

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JAMES E. LAYTON et al.

Results by Hohulin and Muroga[19] and Vink[20] on extensions of Gimpel's algorithm were reported in late 1975. Several alternative methods for solving the CC-table in Gimpel's algorithm suitable for computer processing are presented in [19] and these methods are implemented as computer programs. Vink[20] extended Gimpel's algorithm to permit switching functions containing "don't care" entries and to yield NAND-gate networks with some complemented input variables. Lee and Davidson[2!] developed an interactive design transform approach for NAND networks which permits interchanging the interconnections between gates in an existing network to result in a more desirable network. Finally, Torng[22] utilized the map factoring results developed by Eisenberg[23] to yield a systematic realization procedure for NAND networks by alternately inhibiting 0 and 1 entries in the Karnaugh maps as the number of switching levels increases. After this primitive realization is obtained, a level-reduction procedure is applied to reduce the number of levels to at most three. A transform technique for gate-reduction is used to complete the design procedure. This paper describes a new algorithm based on the map factoring approach for the NAND-gate synthesis of optimal logic networks having only uncomplemented inputs. The resulting three-level combinational switching circuits have a minimum number of gates and a minimum number of inputs to those gates, i.e. minimum interconnections. In contrast to Eisenberg's technique[23], this new procedure yields a minimum-gate, minimum-input logic network directly in three levels without the utilization of subsequent level-reduction theorems. Following a presentation of important theorems, a detailed description of the synthesis procedure is provided. Three examples are given to demonstrate interesting cases which can occur in the use of the design algorithm. Extensions are suggested for obtaining hazardless and/or multiple output networks by this technique. BASIC THEOREMS This section presents fundamental theorems to be used as a basis for the TANT network synthesis procedure. Notationally, the first-level gate is defined as the gate from which the output is obtained. Second-level gates feed first-level gates and third-level gates feed secondlevel gates. Additionally, no feedback is allowed whereby lower-level gates feed higher-level gates. Theorems I-4 provide for second-level and third-level gate candidate generation. The completeness of an iterative procedure based on these first four theorems is guaranteed by Theorem 5. Theorems 6 and 7 describe a necessary selection of certain second-level gate candidates for the optimal network. A key network reduction is indicated by Theorem 8, and Theorems 9 and 10 minimize gate inputs. Finally, Theorem 11 shows that an optimal TANT network is obtained. Theorem 1

Each l-set containing the primary cube is a candidate for a second-level gate in a three-level NAND network having only true inputs. Prop[

Let F(xl, x2 . . . . . xn) be some Boolean switching function with n inputs defined as rn

F(xl, x2 . . . . . x,)= Q + ~

Sj

(I)

where m is the number of l-set terms containing only true inputs, Sj is the product of true inputs for the jth 1-set, and Q is some function covering the remaining l-sets. Using the standard involution theorem [2] gives F(xl, x2 . . . . . x,) = Q + ~, Sj.

(2)

i=l

Applying De Morgan's Theorem [2] yields tn

F(xl, x2 . . . . . x,) = (~. l " I ~ i=l

(3)

Synthesisof optimalTANTnetworks

125

which can be recognized as a two-level NAND network with Sj as inputs to the jth gate at the second level. Moreover, the m outputs from these second-level gates and (~ are inputs to the first level. The primary cube[22] is the 0-cube having the set of coordinates (111 ... 1), i.e. all of the true inputs. Thus, any N-cube with only true inputs must contain the primary cube. Theorem 2

Each 0-set containing the primary cube is a candidate for a third-level gate in a TANT network. Proof

Let F(x~, x2 . . . . . x . ) be defined as F ( x l , x2 . . . . . x.) = R "

x¢k

(4)

i=1

where there are/0-sets composed of the sums of p~ complemented inputs, ~ denotes the kth complemented input in the ith sum, and R is some function covering the remaining 0-sets. For example, one such function might be (.f~+ x2)(~m+ ~3)(~2+ x3 + ~4)-fs, where R = J/~ + x2. Invoking involution and De Morgan's theorems gives Ffx,,x2 .....

x.)=R.~ [~ea]

F ( x l , X2. . . . . Xn) = R " ~=

xe, .

(5)

(6)

Therefore, the inputs to the third-level gates are the p~ true inputs. Theorem 3

For a three-level NAND network, the input combinations to a third-level gate place "don't cares" in the 1-sets being considered as candidates for second-level gates. Proof

Let the input set to the combinational network be represented byt 2n

T3,~ = ~

ti

(7)

i=1

where n is the number of input variables, t~ is the ith combination of the input variables, and Y~ denotes the logical sum of the t~. The k applied input combinations which yield a " l " and 2"-k which yield a "0" at the output of the third-level gate may be expressed as k

2n

Since the output of this third-level gate can be an input to the second level, the total number of inputs to the second level is n + 1. The resulting 2n+mcombinations of inputs to the second level may be expressed as 2a+l

r2,~ = ~ t~.

(9)

tThe summation upper limit 2" indicates only that there are 2" distinct values which i can assume over the entire summation. No relation between the binary value of the particular input t~ and i is implied.

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JAMESE. LAYTONet aL

With Zua as the output of the third-level gate, (lO)

T2nd : Z3rd" T3ra+ Z3rd " T3ra.

Substituting (8) into (10) and simplifying yields k

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(11) k

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combinations. Therefore, the inputs corresponding to the first and fourth terms in (I 1) are never applied and may be considered as "don't cares" for any second-leveL gate into which Z3rj feeds. Theorem 4

If some second-level gate candidates in a three-level NAND network have been determined, then the corresponding l-set input combinations may be treated as "don't cares" in the 0-sets being considered as candidates for third-level gates. Proof

If q members of the l-set are covered by the second-level gate candidates already determined, then the output of the network will be "1" regardless of whether the remaining switching would result in an output of "1" or "0" for the q members of the 1-set previously covered. Theorem 5

If a necessary third-level gate candidate is determined but discarded in favor of another candidate (or candidates), then it will be regenerated subsequently for 0-set coverage at the third level. Proof

Suppose a third-level gate candidate is generated but not needed as a "don't care" (Theorem 3) for particular l-set input combinations being considered for second-level gate candidates. Even though discarded at this stage of generation, the third-level gate candidate may be required subsequently as a "don't care" to feed a second-level gate candidate covering yet another 1-set. Therefore, to cover this other 1-set with a second-level gate, it will be necessary to regenerate the given third-level gate candidate. Furthermore, it is entirely possible that an improved third-level gate candidate having fewer inputs (and containing as a subset the previously discarded gate candidate) will be generated. In the worst case, the discarded gate candidate itself will be regenerated. Theorem 6

The last second-level gate candidate generated must be selected for the TANT network. Proof

Since second-level gate candidates are generated to cover members of the l-set (Theorem i), each new candidate generated must cover at least one member of the l-set not covered by candidates generated previously. The generation of these second-level gate candidates ceases When all members of the l-set have been covered. Therefore. the last candidate generated must be selected because it covers at least one member of the 1-set not covered by any other candidate. Theorem 7

If the first stage of generation of second-level gate candidates yields only one candidate, then that candidate must be selected for the TANT network.

Synthesis of optimal TANT networks

127

Proof At least one member of the 1-set covered by the sole second-level gate candidate must be used as a "don't care" (Theorem 4) for the subsequent generation of one or more third-level gate candidates. By Theorem 2, the resulting third-level gate candidate(s) prevent any subsequent second-level gate candidates from covering the particular member(s) of the I-set being used in Theorem 4. Theorem 8

If a third-level gate candidate feeds only one second-level gate candidate as the sole input to that gate candidate, then both of these gate candidates may be discarded and the inputs to the original third-level gate candidate fed directly into the first-level gate.

Proof Let F ( x t , x2 . . . . . x.) be defined as F(xm, x2 . . . . . x.) = h,oP

(12)

where t3~ is the input combination to the third-level gate under consideration and P is some function that covers the remainder of the members of the 1-set. Using the involution theorem yields F ( x l , x 2 . . . . . x.) = t3~P (13) which corresponds to t3ra being fed directly into the first-level gate. Theorem 9

If any input x~ is fed to a particular third-level gate and to each of the second-level gates which that gate feeds, then x~ may be removed, as an unnecessary input, from the third-level gate.

Proof Let the switching function F(x~, x2 . . . . . x.) be represented by F ( x . x2 . . . . . x.) = [Rix~(x~x.)][ R2x~(x~x.)]

(14)

where x~ and xn are inputs to a third-level gate which feeds two second-levePgates. In addition to this input, R~ feeds one of the second-level gates, R2 feeds the other, and xc feeds them both directly, where Rt and R2 are arbitrary. Using De Morgan's theorem gives F ( x . x2 . . . . . x.) = R,x~(~ + Y,.) + R2x~(~ + Y,.)

(15)

which may further be expressed as F(xl, x2 . . . . . x.) = R~x~X~ + R~xd,, + R2xtX~ + R.x~.f,r

(16)

Observe that the first and third terms in (16) are zero and that the remaining terms are due to the appearance of x~ as a direct input to the second-level gates. Therefore, the x¢ input may be omitted from the third-level gate. Theorem 10

To obtain an optimal network, any inputs which do not affect the output must be removed. Proof

If an input is present in Network A and not in Network B with all gates and other inputs being the same, then Network B obviously has fewer inputs. Provided that the two networks have identical outputs under all input conditions, Network A cannot be the optimal network.

JAMES E. LAYTON et al.

128

Theorem I 1 Among the networks generated by using Theorems i-10, there exists an optimal network. Proof Theorems 5 and 6 guarantee that all of the necessary gate candidates have been generated. Using these candidates to cover the 1-set of the desired switching function and applying Theorem 8 yields a minimum number of gates. The fewest number of inputs to these gates are determined by Theorems 9 and 10. Therefore, these exhaustive searches on covering and input reduction yield an optimal network. THE N E T W O R K S Y N T H E S I S P R O C E D U R E

A detailed description of the TANT network synthesis procedure based upon the theorems of the previous section is presented here. A flow chart is given in Fig. l, and a detailed explanation of each step is given below. Step 1 Determine whether the primary cube contains a "1" or a "0". If the primary cube contains a " l " , then go to Step 2. If the primary cube contains a "0", go to Step 4. Step 2 Determine the prime implicants (largest l-sets) not requiring complemented inputs. This step uses Theorem l to generate second-level gate candidates by forming, with true inputs only, the largest groups of minterms (l-set members).t

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~

OETERMINE PRIME I IMPLICANTS STEP 2 ( ] - SETS )

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FORMAL£.POSSIBLE I TANT NETWORKS FROM GENERATED STEP 6 GATE CANDIDATES

t DETERMINE PRIME I IMPLICATES STEP 4 (O-SETS)

REMOVE GATES AND i MINIMIZE INPUTS ISTEP 7 SELECT HAVINGNETWORK FEWEST LTEP GATES AND FEWEST INPUTS TO THOSEGATES

CONSIDER ALL POSSIBLE COMBINATIONS O F J THIRD- i LEVEL GATE CANDIDATES I

/

Ij

'STEP 5

CHOOSE COMBINATION ALLOWING MOST NEW MINTERM COVERAGE

Fig. 1. Flow chart of the TANT network synthesis procedure. tParticularly for TANT networks having relatively few input variables, the Karnaugh map is a convenient tool for forming these largest groups by circling on the minterms in Step 2 and maxterms in Step 4. A computer program should be considered for handling networks with large numbers of input variables.

Synthesisof optimalTANTnetworks

129

Step 3 Test for coverage of the minterms for the desired switching function. If all of the minterms are covered, then go to Step 6; otherwise, more gate candidates must be generated, and, therefore, go to Step 4. Step 4 Using all minterms that have been covered previously as "don't cares" by Theorem 4, determine the prime implicates (largest 0-sets) not requiring complemented inputs. Thus, by Theorem 2, third-level gate candidates are generated from the largest groups of maxterms (0-set members). Step 5 This step determines which third-level gate candidates to retain. Test whether each gate candidate, considered singly, creates suitably placed "don't cares" (by Theorem 3) to allow additional second-level gate candidates to be generated that cover at least one minterm not already covered. If none allow another second-level gate candidate to be generated, try all possible combinations of two, then all combinations of three, etc. until at least one new second-level gate candidate can be generated. When at least one new minterm can be covered by this procedure, select the combination of third-level gate candidates that allows the most new minterms to be covered. For example, let third-level gate candidates considered singly or in combinations of two permit no new second-level gate generation. Furthermore, suppose two groups of these third-level gate candidates considered in combinations of three do allow new second-level gate generations. Therefore, the group consisting of a combination of three third-level gate candidates which yields the second level gate candidate(s) covering the most new minterms is retained. By Theorem 5, the discarded combination, if needed for the optimal network, will be generated subsequently. Consider all the implicates covered by these thirdlevel gate candidates to be "don't cares" for subsequent gate candidate 'generation. Return to Step 2. Step 6 Create all possible networks that cover the desired switching function by using the second-level and third-level gate candidates generated. Use Theorems 6 and 7, and then form a covering and closure table. Step 7 Use Theorem 8 to eliminate third-level gates which solely feed second-level gates by feeding the third-level gate inputs directly to the first-level gate. Use Theorems 9 and I0 to eliminate the unnecessary inputs for the remaining second-level and third-level gates. Step 8 Determine from among the several resulting networks the one(s) having a minimum number of gates and a minimum number of inputs to those gates. By Theorem 11, an optimal network is guaranteed. The optimality of the resulting TANT network is based upon the procedure's adherence to the theorems of the previous section. Although more efficient steps might possibly be appropriate in selected cases, the synthesis procedure presented here does yield an optimal TANT network. Specifically, the discarding of third-level gate candidates in Step 5 may be avoided by a parallel storage and the subsequent consideration of all possible candidates. The particular selections in the step of the procedure yield an effective solution without unduly large amounts of storage. The directness of this procedure is demonstrated in the following examples. EXAMPLES Three examples are presented in this section to illustrate the developed network synthesis procedure. The first example appeared in [22] and is included here for comparison as well as a detailed explanation of the steps of the present algorithm. Example 2 demonstrates the

130

JAMESE. LAYTONet

al.

regeneration principle of Step 5 (Theorem 5) and gate selection procedures of Step 6, and Example 3 shows the details of input reduction in Step 7 (Theorems 9 and I0).

Example I It is required that an optimal TANT network be designed to realize the combinational switching function given by F(x,, x2, x3, x4) = ~ m(O, 1, 2, 3, 4, 5, 6, 11, 13).

(17)

The minterms in (17) are indicated by rs in the Karnaugh map of Fig. 2(a), and O's are shown in all other map locations. In Step 1 of the synthesis procedure, the primary cube contains a 0, which directs the algorithm to Step 4. Two prime implicates are identified and labeled as Tt and T2 in Step 4. In Step 5, results are shown in Figs. 2(b) and (c) for Tt and /'2, respectively, by replacing the appropriate O's by d's, allowing the tentative formation of prime implicants. Since the new 1-set coverage for the prime implicants obtained by using T~ is greater than T2, only Tt is retained. Proceeding to Step 2, the two prime implicants of Fig. 2(b) become second-level gate candidates and are labeled St and $2. In Step 3, Minterms 0, 1, 2, 4 and 6 are not yet

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Synthesis of optimalTANT networks

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covered, and the procedure returns to Step 4. Additional "don't cares" (d's) due to S~ and $2 are shown in Fig. 2(d), along with the d's due to TI determined earlier. The prime implicate labeled T3 covers the remaining five O's (Step 4). Since only one prime implicate is generated, proceed past Step 5 directly to Step 2. Replacing the entries in T3 by d's in Fig. 2(e) yields the second-level gate candidate labeled $3, which is composed of the entire map. Since all minterms are covered (Step 3), proceed to Step 6 to form possible TANT networks. In the second-level, $3 must be selected, since it was the last second-level gate candidate. Minterms 0-6 are covered by $3, as indicated by checks (V') in Fig. 2(a). Third-level gates whose outputs feed into the NAND-gate with output $3 have outputs Tj and T3. T3 covers Maxterms 8, 9, 10, 12, 14 and 15. Maxterms 7 and 15 are covered by Tj. Additional second-level gates are needed to cover Minterms I 1 and 13. The gate candidate with output $1 covers Minterms 3 and II, and the gate candidate with output $2 covers Minterms 5 and 13. Both of these gate candidates require T~ as an input to cover Maxterms 7 and 15. Input variables needed for these second-level and third-level gate candidates are identified in the expressions for S~, $2, $3,/'1 and T3 in Figs. 2(a), (b), (d) and (e). No other possible TANT networks covering the desired minterms can be formed from these gate candidates. Furthermore, no gate or input reduction (Step 7) is possible. Therefore, the combinational switching circuit shown in Fig. 2(f) is the optimal TANT network (Step 8). This example was worked by Torng[22] using Eisenberg's method[23] as Example 8.5 on Pages 118-125. The result in Fig. 2(f) is identical to Torng's switching circuit realization in Fig. 8.20 on Page 125 of [22], which was obtained after applying a level-reduction technique to the primitive realization.

Example 2 As a second example, consider the switching function given by

F(xl, x2, x3, x4) = ~ m(0, l, 2, 6, 7, 8, I l, 12, 14)

08)

which is indicated on the Karnaugh map of Fig. 3(a). Step 1 directs the algorithm to Step 4, where the single prime implicate Tmis formed. Passing through Step 5 to Step 2 yields the three prime implicants $1, $2 and $3 in Fig. 3(b). Since not all minterms have been covered (Step 3), return to Step 4. The four prime implicates T2, T3, T4 and T5 are formed in Fig. 3(c). None of these prime implicates considered singly allows new minterm coverage in Step 5. Taken two at a time, T3 with /'4 allows Minterm 8 to be covered and T2 with T3 allows Minterm 2 to be covered. Arbitrarily choosing the 7"2 and T3 combination yields $4 in Step 2, as shown in Fig. 3(d). Again, return to Step 4. T4 and /'5 are regenerated (Fig. 3(e)), but when considered singly only T4 allows new minterm coverage. Returning to Step 2 yields $5 (Fig. 3(f)), which covers Minterm 8. Once again, return to Step 4. T5 is regenerated (Fig. 3(g)), allowing in Step 2 the coverage of the entire map ($6 in Fig. 3(h)). Since all minterms have now been covered (Step 3), proceed to Step 6. Select $6, which covers Minterms 0, 1, 2 and 8, as the last gate candidate formed. Moreover, select $1 to cover Minterms 6, 7 and 14, $2 to cover Minterms 12 and 14, and $3 to cover Minterm 11. Observe that T2, /'3, T4 and T5 must be used as inputs to $6 to cover all maxterms. Rather than selecting Ti to feed St, $2 and/or $3, T4 may be used to feed S, and $2, and /'5 to feed $3, as shown in Fig. 3(i). Alternately, $2 may be used to cover only Minterm 12, since Minterm 14 is already covered by Sl. If both /'3 and T~ are used to feed S2, then the x2 input to $2 can be removed, and $2 covers Minterms 8 and 12. Therefore, this input change yields a second optimal TANT network, in addition to the one shown in Fig. 30)).

Example 3 The purpose of this final example is to illustrate input reductions for second-level and third-level gates. Let the switching function to be realized be given by

F(xl, X2, x3, x4) = ~ m(0, 2, 3, 4, 5, 6, 7, 8, 10, 12, 15).

(19)

Step 1 directs the algorithm to Step 2, where S~ is formed in Fig. 4(a). Passing through Step 3,

JAMES E. LAYTON e! al.

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Fig, 3. Designsteps and optimalTANTnetworkfor Example2. Prime Implicates T~ and T2 are generated in Step 4 (Fig. 4(b)). In Step 5, T~ allows more new minterms, and /'2 is discarded. Returning to Step 2, S2 and $3 are generated (Fig. 4(c)). In Step 4, Te and /'3 are generated, but only 7'2 is retained in Step 5 (Fig. 4(d)). Figure 4(e) shows the results of forming $4, $5 and $6 in Step 2. Thereafter, T3 is regenerated in Step 4, allowing Sv to be formed in Step 2 (Figs. 4(f) and (g)). It is the application of Steps 6 and 7 in this example which requires special attention. $7 is selected, as the last gate candidate generated, for a second-level gate to cover Minterms 0, 2, 4, 6, 8, l0 and 12. Both T2 and T3 are needed as inputs to this gate. In particular, 7"2 covers Maxterm 14, and T3 covers Maxterms l, 9, I l and 13. The sole first second-level gate candidate generated (SO covers Minterms 7 and 15, and no third-level gate outputs are required as added inputs to this gate. Only Minterms 3 and 5 remain to be covered at this point. Minterm 3 can be covered by using either Sz with inputs x3, x4 and T~ or $4 with inputs x3, Tt and T2. Minterm 5 can be covered by using either $3 with inputs x2, x4 and T~ or $5 with inputs x2, T~ and T2. Therefore, using either $2 and $3 or $4 and $5 should result in a TANT network covering all the minterms. However, if $2 and $3 are used, then the x4 input to T~ is redundant and can be removed by Theorem 9. Moreover, the x, input can be omitted from both the $2 and $3 second-level gates as shown in Fig. 2(h), since Minterms 2 and 6 and Minterms 4 and 6 are included in the desired switching function (Theorem 10). Theorem l0 also allows x~ to be removed as an input to Tz, since Minterm 6 is now covered by both $2 and $3. The resulting optimal TANT network is shown in Fig. 4(h).

133

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DISCUSSION A N D EXTENSIONS

The network synthesis procedure utilizes cyclical gate candidate generation and exhaustive input optimization, which is very amenable to digital computers. A computer program for this new algorithm has been developed and tested on a limited number of cases. Further considerations in evaluating this computer-aided design (CAD) program include examining its operating speed, memory requirements, program complexity, and convenience for the user. Other CAD software packages, such as those described in [19] and [24], can then be compared on the basis of these criteria. This algorithm and its associated computer program may be readily extended to realize hazardless TANT networks by including additional implicants and implicates as necessary for second-level and third-level gates. An expansion to handle TANT networks having multiple outputs could be realized by tagging implicants and implicates as they are generated for candidates and identifying outputs with corresponding gate candidates. The design problem of this paper was defined to permit true inputs only, but to extend the application to include sequential .problems requires that selected inputs with both true and complemented values must be allowed. Inputs to the combinational logic in a sequential circuit are of two types. One type of input is from external sources and is allowed to appear only in its uncomplemented form. The other type, which is an output from the memory section of the sequential switching circuit, has both true and complemented values available. Additional work is needed to extend the developed algorithm for sequential TANT network design.

134

JAMES E. LAYTON et al. CONCLUSIONS

A network synthesis algorithm has been developed for the design of optimal three-level NAND-gate combinational switching networks having only uncomplemented inputs (TANT). A detailed description of the procedure has been provided and a flow chart included for easy reference. Three examples have been presented to demonstrate pertinent details of the algorithm. Finally, the development of a CAD package has been mentioned, extensions for handling hazardless and/or multiple-output TANT networks have been suggested, and an expansion of the problem definition to include sequential TANT network synthesis has been described. REFERENCES 1. E. J. McCluskey, Logical design theory of NOR-gate networks with no complemented inputs. 1%3 Proc. 4th Annual Syrup. on Switching Circuit Theory and Logical Design, IEEE Special Publication A-156, pp. 13%148 (1%3). 2. H. T. Nagle, Jr., B. D. Carroll and J. D. Irwin, An Introduction to Computer Logic. Prentice-Hall, Englewood Cliffs. N.J. (1975). 3. D. B. Bradley, A survey of Boolean function realization using NAND and NOR logic, M.S. Thesis, Auburn University, Auburn, Alabama (1970). 4. J. F. Gimpel. The minimization of TANT networks. IEEE Trans. Electron, Comput. EC-16, 18-38 {1967). 5. G. A. Maley and J. Earle, The Logical Design o[ Transistor Digital Computers. Prentice-Hall, Englewood Cliffs, N J. (1%3). 6. L. Hellerman, A catalog of three-variable OR-invert and AND-invert logic circuits. IEEE Trans. Electron. Comput. EC-12, 198--223(1%3). 7. D. T. Ellis, A synthesis of combinational logic with NAND or NOR elements. IEEE Trans. Electron. Comput. EC-14, 701-705 (!%5). 8. E. S. Davidson, An algorithm for NAND decomposition under network constraints. IEEE Trans. Comput. C-18, 1098-1109(1%9). 9. D. L. Dietmeyer and Y. H. Su, Logic design automation of fan-in limited NAND networks, IEEE Trans. Comput. C-18, 11-22 (i%9). 10. P. R. Schneider and D. L. Dietmeyer, An algorithm for synthesis of multiple-output combinational logic. IEEE Trans. Comput. C-17, 117-128 (!%8), I 1. K. K. Chakrabarti, A. K. Choudhury and M. S. Basu, Complementary function approach to the synthesis of three-level NAND networks. IEEE Trans. Comput. C-19, 509-514 (1970). 12. K. S. Koh, A minimization technique for TANT networks. IEEE Trans. Comput. C-20, 105-107 (1971). 13. J. Frackowiak. The synthesis of minimal hazardless TANT networks, IEEE Trans. Comput. C-21. 1099-1108 t l972L 14. C. R. Baugh, C. S. Chandersekaran, R. S. Swee and S. Muroga, Optimal networks of NOR-OR gates for functions of three variables. IEEE Trans. Comput. C-21, 153-160 (1972). 15. M. A. Breuer, Implementation of threshold nets by integer linear programming. IEEE Trans. Electron. Comput. EC-14, 950-952 (1%5). 16. S. H. Cameron, The generation of minimal threshold nets by an integer program. IEEE Trans. Electron. Comput. EC-13, 299-302 (1964). 17. S. Muroga, Logical design of optimal digital networks by integer programming. AdtJances in In/ormation Systems Science. Vol. 3, pp. 283-384. Plenum Press. New York (1970L 18. R. A. Smith, Minimal three-variable NOR and NAND logic circuits. IEEE Trans. Electron Comput. EC-14, 79-81 (1%5). 19. K. R. Hohulin and S. Muroga, Alternative methods for solving the CC-table in Gimpers algorithm for synthesizing optimal three-level NAND networks. T.R. UIUCI)CS-R-75-720, Dept. of Comput. Science, Univ. of Ill., Urbana, Ill. IEEE Comput. Repos. No. R75-330, Abstracted in Computer 8, 94 (Dec. 1975). 20. H. A. Vink, Minimal TANT networks for functions with don't cares and some complemented input variables. IEEE Comput. Repos. No. R76-95, Abstracted in Computer 9, 105 (May 1976). 21. H. P. Lee and E. S. Davidson, A transform for NAND network design. IEEE Trans. Comput. C-21, 12-20 (1972). 22. H. C. Torng, Switching Circuits Theory and Logic Design. Addison-Wesley, Reading, Mass. (1972). 23. H. Eisenberg, An algorithm for the NAND-gate realization of switching functions. Master's thesis, Cornell University, Ithaca. N.Y. (1%9). 24. S. Y. H. Su and C. W. Nam, Computer-aided synthesis of multiple-output multi-level NAND networks with fan-in and fan-out constraints, IEEE Trans. Comput. C.20, 1445-1455 0971).