- Email: [email protected]
System-level modelling in VHDL
Microelectronics Journal, 23 (1992) 2 2 3 - 2 3 0
M ~
System-Level Modelling in VHDL A. C. Woo and L. E. Peppard Department of ElectricalEngineering, Queen's University, Kingston, Ontario, CanadaK7L 3N6
Uninterpreted models such as statecharts and Petri nets are powerfulmodellingparadigmsat the highestlevel of abstraction and are useful at preliminary stages of system design. In this paper, translationstrategiesare presentedto translatethese two paradigms into VHDL. Criteria are presented and used to evaluatethe capabilityof VHDLto capturemodelsat high levels of abstraction. This paper will show that translationsthat meet all specified criteria are possible, but that problems are still encountered. Some suggestionsto enhance VHDL's modelling potential at the uninterpreted level are given.
1. Uninterpreted Modelling o cope with the overwhelming complexity of VLSI circuits, models are used to describe systems at various levels of abstraction. At the highest level of abstraction are uninterpreted models, defined formally in Hady et al. [1]. Uninterpreted models are characterized by their lack of data types and undefined transformational blocks. Tokens are used to mark the flow of information through a network of states. These models are used at preliminary stages of design to explore issues such as design styles, resource allocation and coordination, data flow and component utilization.
T
Hardware description languages such as VHDL were created to capture design concepts at all levels of abstraction and provide a common format for design concepts throughout the design process. They have been proven effective at lower levels of abstraction such as at the gate, RTL and behavioural levels, making them widely used at implementation stages
of design. Unfortunately, these languages require more detail than is available early in the design cycle [2], rendering them unsuitable for uninterpreted modelling [1]. Several good modelling paradigms exist at the uninterpreted level to capture preliminary design concepts. If translations between these paradigms and hardware description languages can be found, the usefulness of HDLs can be extended bringing the goal of a continuous, single-path design environment closer to reality. This paper presents two uninterpreted modelling paradigms, statecharts and Petri nets, and their possible translations to VHDL. To determine the effectiveness of the translations and the language to capture designs at this level of abstraction, four criteria will be used. (1) The VHDL code must functionally model the behaviour of the original uninterpreted specification. (2) The generated code must clearly show the structure of the original system. (3) The VHDL model should be efficient in simulation and in the number of lines of code. (4) The amount of code should grow linearly for increasing system complexity. These criteria can provide a basis for determining how well VHDL captures high-level system models
0 0 2 6 - 2 6 9 2 / 9 2 / $ 5 . 0 0 © 1992, Elsevier Science Publishers Ltd.
223
A C. Woo and L. E. Peppard/System-Level Modelling in VHDL
m.se r ~ l ~ t
~ dies
f - main-component f-w~ch-and-alarm
• ,.= =..=h.
fight
I
I,
J
Fig. i. Description of a ~ta] watch using statecharts. and how the present IEEE-standard VHDL might be improved.
2. Statecharts Statecharts are a visual formalism developed by Harel [3] for the description of complex reactive systems. Figure 1 illustrates a statechart description of a digital watch. The battery-operated watch features an audible alarm, a stopwatch and a backlight. There are four buttons, labelled "a" through "d", through which the functions are controlled. Statecharts are based on states which can be grouped in a hierarchical manner to abstract details of lower levels. Arcs indicate the movement between states and the events upon which state transitions occur.
224
Arcs leading to and from hierarchical states act as interrupts causing internal states to be activated and deactivated. Collections of states which execute concurrently are separated by the dashed lines. For instance, the "light" and "watch-and-alarm" collection of states operate in parallel, independently of each other. Statecharts also offer the ability to re-enter states and resume previous states instead of entering a default state as is the case for the "stopwatch" state. A more complete description of statecharts and the digital watch example can be found in ref. 3. The translation strategy into VHDL is as follows: states are mapped into signals and the arcs are mapped into a generic process sensitive to a particular event. Events (i.e. "battery inserted", "a", "b", etc.)
Microelectronics Journal, VoL 23, No. 3 ili iili iiiiiil ~i!i!il~
Including documentation, the translation generated 860 lines of code. The translation proved to be efficient and the structure of the original statechart description was clearly preserved in the code. Since the transformation between statechart feature and VHDL construct is one-to-one, the code grows linearly with increases in statechart complexity. Simulations using the Intermetrics tool set verified the correct operation of the VHDL code.
are packaged as global signals. Each hierarchical state is mapped as an entity to preserve the structure of the system and a manager process is included in each hierarchical state to activate and deactivate internal states, in addition to handling default and historical entries into the state. Concurrent networks are defined within block constructs where signals can be declared locally. Listing 1 was generated from the "update-alarm" state. The arc process is declared as a component and instantiated for each arc in the description. Each leaf state in the description results in a signal declaration. The manager process is responsible for activating, deactivating and resetting states within. The process is also responsible for activating the correct internal state upon state activation depending on the entry mode, either default or historical.
LISTING 1
Several problems were encountered in the design of the translation strategy. Statecharts have the ability to execute processes when certain states are reached. These actions can be asynchronously suspended or terminated. VHDL does not have semantics for proper process control. A possible way around is the inclusion of special clauses in the process's wait statements. However, this does not provide a
VHDL code generated from update-alarm section of Fig. 1
- - WATCH: VHDL description of David Harel's digital watch - - statechart description written by Arthur Woo, February, 1991 - - MODULE: U P D A T E A L A R M architecture body use WORK.SIGNALS.all; - - receive broadcasted events architecture u p d a t e a l a r m _ _ b o d y of update___alarm is component arc port ( ENABLE, SET, GRST: in bit; ARCIN: in bit; CLR: out bit; ARCOUT: out bit; LRST: in bit ); end component; for all:arc use entity WORK.arc(arc body); signal enable, reset: bit; signal U P D A T E H O U R , UPDATE
MIN, UPDATE
TENMIN: state__type := ('0', '0');
begin
--
super state manager process(default out reset, inl state, outl variable f i r s t e n t r y : boolean := true; begin
reset)
225
(D i
<
A. C. Woo and L. E. Peppard/ System-Level Modelling in VHDL
-0 (D
rr if (not default out reset'stable and default out reset = '1') or (not out1 reset'stable and out1 reset -- '1') then - - default state exit enable < = '0'; - - reset < = '1', '0' after 1 ms; default out state < = '0'; elsif (not in1 state'stable and in1 state = '1') then - - entry by arc crossing reset < = '1', '0' after 1 ms; enable < = '1'; default out state < = '1'; f i r s t e n t r y := false; end if; end process;
U P D A T E MIN.state < = in1 state; in1 reset < = U P D A T E MIN.reset;
--
connect states to ports
out1 state < = U P D A T E HOUR.state; UPDATE HOUR.reset < = o u t 1 reset; arc1: arc port map ( enable, C, reset, UPDATE__MIN.state, U P D A T E MIN.reset, U P D A T E TENMIN.state, U P D A T E T E N M I N . r e s e t ); arc2: arc port map ( enable, C, reset, U P D A T E TENMIN.state, U P D A T E TENMIN.reset, UPDATEHOUR.state, UPDATEHOUR.reset ); end u p d a t e a l a r m _ _ b o d y ;
solution to delayed events. Once a waveform has been scheduled on a signal, the process loses control over it. Should the process become suspended or terminated, the process has no way of reversing its effects without possibly affecting events from other processes.
3. Petri Nets Petri nets are another visual modelling paradigm for representing systems at the uninterpreted level. Several classes of Petri nets exist, but for the purposes of this paper the most basic definition will be used. For a more complete description of Petri nets, readers are referred to refs. 4 and 5, two informative texts on the subject.
226
The most basic interpretation of nets, referred to as condition/event nets, consists of two elements: conditions, represented graphically as circles, and events, represented as line segments. Directed arcs between conditions and events describe the movement of tokens through the net. A condition is said to be valid if it contains a token. During the execution of the net, events occur causing some conditions to become invalid while validating others. Execution rules for the net specify how tokens are placed into and taken from conditions. An event is "active" when all of its input conditions are valid, i.e. it contains a token, and all of its output conditions are not valid. An event "fires" when active by removing a token from each input condition and
O
Microelectronics Journal VoL 23, No. 3 i¸
ill
Oi
O m
placing a token in each output condition. A maximum of one token is allowed in each condition and, by definition, an event occurs in zero time (Fig. 2). In this implementation of Petri nets in VHDL, conditions are mapped into resolved signals of type integer and events are modelled as processes sensitive to input and output conditions. The event process waits for tokens to appear on all of its inputs. If all ouTut conditions are free at this point, tokens are transferred from input conditions to output conditions. It is possible for several arcs to lead into a condition which translates into more than one driver to a signal; therefore, a resolution function must be defined. Since the dynamic behaviour of Petri nets ensures that at most one driver will be active at any instant of time, a simple resolution function which returns the value of the single driver has been implemented.
LISTING 2
consumer
busy ~ r e a d y
channel
~4
producer
busy~eady
Fig. 2. Simple Petri net description of a producer and consumer process communicating over a channel. Listing 2 is a sample of VHDL code generated using this translation strategy. The event process, whose code is not listed, executes the behaviour as outlined above. Simulations show that the behaviour of the simulated code matches the behaviour of the net. The structure of the net is clearly evident from the code. The generic nature of the transition entity makes the code efficient and will ensure linear growth of the code for increasing net complexity.
VHDL listing for Petri net of Fig. 2
- - Petri net example: consumer/producer processes using a -single channel, written April 1991 by Arthur Woo
use WORK.PETRI PACKAGE.all; architecture main__body of main is component transition generic (num inputs: positive; num outputs: positive; seed: integer ); port ( input: inout integer vector(1 to num inputs) bus; output: inout integer_ vector(1 to num__ouTuts ) bus); end component; for all:transition use entity WORK.transition(transition body); - - for each state there is one signal declared signal consumer__busy: integer__resolved register := 0; signal consumer__ready: integer resolved register := 0; signal producer__busy: integer__resolved register := 0; signal producer..ready: integer resolved register := 0; signal channel: integer__resolved register := 0;
be~n
227
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A. C. Woo and L. E. Peppard/ System-Level Modelling in VHDL
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process - - problems with simulation tool force this strange syntax begin consumer___busy <= 1 after 1ms; consumer busy <= transport null after 2ms; producer___ready <= 1 after 1ms; producer___ready<= transport null after 2ms; wait; end process; - - each transition is instantiated here el: transition generic map (num inputs=> 1, num outputs=> 1, seed => 227 ) port map (input(l) => consumer busy, output(l) => consumer ready); e2: transition generic map ( num__inputs => 2, num___outputs=> 1, seed => 431 ) port map (input(l) => consumer ready, input(2) => channel, output(l) => consumer busy); e3: transition generic map (num inputs=> 1, num outputs=> 1, seed => 67 ) port map (input(l) => producer busy, output(l) => producer ready ); e4: transition generic map ( num..__inputs=> 1, num..__outputs=> 2, seed => 115 ) port map (input(l) => producer_, ready, output(l) => producer..___busy, output(2) => channel); end main.__body;
Although the translation satisfied all criteria as stated previously, several issues again were raised during the design of the translation strategy. The lack of global variables which consequendy forced the use of global signals produced several inefficiencies in the simulation, namely the implementation of a resolution function and unnecessary maintenance of signal attributes. The lack of features in VHDL to handle the non-deterministic nature of Petri nets was another problem. To overcome this, a random delay was incorporated in the event behaviour. In this way, the random ordering of simultaneous events was possible. One consequence of the random delay is that time no longer has meaning, as can be seen in Listing 3. This may cause complications in trying to interface a Petri net model with other models with timing parameters.
228
Another weakness of the models' non-deterministic features is the lack of a random number generator in VHDL. Cerney et al. [6] have addressed this issue. Unfortunately the implementation of a random number generator is complex due to the concurrent nature of VHDL. The inclusion o f such a function in the VHDL standard would eliminate this coding inefficiency. The function used in this experiment is simple but serves to demonstrate the effectiveness of the translation.
4. Discussion The goal of this work is to explore the potential in VHDL to capture high-level system models described in established modelling paradigms. The design of translation strategies from Petri nets and statecharts
Microelectronics Journal, Vol. 23, No. 3 !~
i¸ ;
i~iii~iiill ii~oiiiiiii!il i!ii: LISTING 3
Results from Petri net simulation VHDL Report Generator SIGNAL NAMES
TIME (MS) 0 +1 1 17099 +1 19666 +1 31123 +1 32829 +1 33979 +1 50763 +1 55910 +1 59982 +1
PRODUCER__BUSY 0
PRODUCER___READY 0 0 1
1
0
0
1
CHANNEL 0
0
0
1
1
0
into VHDL has pointed out some of the strengths and weaknesses of VHDL to fulfil this purpose.
The successful translation of both Petri nets and statecharts into VHDL has proven the feasibility of high-level modelling in VHDL. Several features can be identified as key to this success. They include constructs such as the entity declaration to mimic exactly the structure and the hierarchy of the original model. The signal storage element allowed the connectivity to be duplicated and thus provided a means of communications between processes. Algorithmic descriptions of the entity behaviour allowed VHDL to match the dynamic behaviour of the original model. Another important feature of VHDL which allows the capture of high-level models is the ability to describe concurrent as well as sequential actions.
CONSUMERREADY 0
0
1
1
0
0
1
1
0 1
CONSUMER___BUSY 0 0 1
1
1
One of the weaknesses in using VHDL for high-level modelling is the lack of global variables. Global variables are purposely ruled out in the present standard for good reason. Problems of mutual exclusion are avoided by using global signals with their associated resolution function, but the overhead of executing this function along with maintaining signal attributes adds to the inefficiency of the simulation. A compromise solution may be the creation of a hybrid signal/variable type. It would be used like a register signal but would allow only one or fewer drivers at a time making the resolution function unnecessary. None of the attributes of signals would be associated with the hybrid type making it more efficient in simulation. Such a storage type would be ideal for both Petri net and statechart modelling. The lack of a random number function is also a
229
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A C. Woo and L. E. Peppard/System-Level Modelling in VHDL
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ec
weakness. Such a function could easily be made part of the standard since its inclusion will have no sideeffects.
features in VHDL to handle non-determinism in modelling paradigms. References
5. Conclusions
This paper has shown two modelling paradigms suitable for uninterpreted modelling of complex VLSI systems and has presented original strategies for their translation into VHDL. Criteria for the translations have been stated and used as the basis for evaluating the potential in VHDL in capturing these high-level models. Although translations have been proven possible, several problems were encountered, namely the lack of asynchronous control over process execution, the inefficiencies of global signals when used as global variables, and the lack of
230
[1] F. Hady, J. Aylor, R. Williams and R. Waxman, Uninterpreted modeling using the VHSIC hardware description language (VHDL), Proc. Int. Conf. on Computer Aided Design, 1989, pp. 172-175. [2] R. Auletta and J. Aylor, A non-interpreted model for digital system design, Proc. IEEE, SOUTHEASTCON, Richmond, VA, 1986, pp. 296-299. [3] D. Harel, Statecharts: A visual formalism for complex systems, Science of Computer Programming, 8 (1987) 231-274. [4] J. Peterson, Petri Net Theory and the Modeling of Systems, Prentice-Hall, Englewood Cliffs, 1981. [5] W. Reisig, Petri Nets: An Introduction, Springer-Verlag, Berlin, 1985. [6] E. Cerny, M. Aboulhamid and S. Curry, Some elements for high-level modelling in VHDL, Proc. Canadian Conference on Very Large Scale Integration, 1989.
M ~
System-Level Modelling in VHDL A. C. Woo and L. E. Peppard Department of ElectricalEngineering, Queen's University, Kingston, Ontario, CanadaK7L 3N6
Uninterpreted models such as statecharts and Petri nets are powerfulmodellingparadigmsat the highestlevel of abstraction and are useful at preliminary stages of system design. In this paper, translationstrategiesare presentedto translatethese two paradigms into VHDL. Criteria are presented and used to evaluatethe capabilityof VHDLto capturemodelsat high levels of abstraction. This paper will show that translationsthat meet all specified criteria are possible, but that problems are still encountered. Some suggestionsto enhance VHDL's modelling potential at the uninterpreted level are given.
1. Uninterpreted Modelling o cope with the overwhelming complexity of VLSI circuits, models are used to describe systems at various levels of abstraction. At the highest level of abstraction are uninterpreted models, defined formally in Hady et al. [1]. Uninterpreted models are characterized by their lack of data types and undefined transformational blocks. Tokens are used to mark the flow of information through a network of states. These models are used at preliminary stages of design to explore issues such as design styles, resource allocation and coordination, data flow and component utilization.
T
Hardware description languages such as VHDL were created to capture design concepts at all levels of abstraction and provide a common format for design concepts throughout the design process. They have been proven effective at lower levels of abstraction such as at the gate, RTL and behavioural levels, making them widely used at implementation stages
of design. Unfortunately, these languages require more detail than is available early in the design cycle [2], rendering them unsuitable for uninterpreted modelling [1]. Several good modelling paradigms exist at the uninterpreted level to capture preliminary design concepts. If translations between these paradigms and hardware description languages can be found, the usefulness of HDLs can be extended bringing the goal of a continuous, single-path design environment closer to reality. This paper presents two uninterpreted modelling paradigms, statecharts and Petri nets, and their possible translations to VHDL. To determine the effectiveness of the translations and the language to capture designs at this level of abstraction, four criteria will be used. (1) The VHDL code must functionally model the behaviour of the original uninterpreted specification. (2) The generated code must clearly show the structure of the original system. (3) The VHDL model should be efficient in simulation and in the number of lines of code. (4) The amount of code should grow linearly for increasing system complexity. These criteria can provide a basis for determining how well VHDL captures high-level system models
0 0 2 6 - 2 6 9 2 / 9 2 / $ 5 . 0 0 © 1992, Elsevier Science Publishers Ltd.
223
A C. Woo and L. E. Peppard/System-Level Modelling in VHDL
m.se r ~ l ~ t
~ dies
f - main-component f-w~ch-and-alarm
• ,.= =..=h.
fight
I
I,
J
Fig. i. Description of a ~ta] watch using statecharts. and how the present IEEE-standard VHDL might be improved.
2. Statecharts Statecharts are a visual formalism developed by Harel [3] for the description of complex reactive systems. Figure 1 illustrates a statechart description of a digital watch. The battery-operated watch features an audible alarm, a stopwatch and a backlight. There are four buttons, labelled "a" through "d", through which the functions are controlled. Statecharts are based on states which can be grouped in a hierarchical manner to abstract details of lower levels. Arcs indicate the movement between states and the events upon which state transitions occur.
224
Arcs leading to and from hierarchical states act as interrupts causing internal states to be activated and deactivated. Collections of states which execute concurrently are separated by the dashed lines. For instance, the "light" and "watch-and-alarm" collection of states operate in parallel, independently of each other. Statecharts also offer the ability to re-enter states and resume previous states instead of entering a default state as is the case for the "stopwatch" state. A more complete description of statecharts and the digital watch example can be found in ref. 3. The translation strategy into VHDL is as follows: states are mapped into signals and the arcs are mapped into a generic process sensitive to a particular event. Events (i.e. "battery inserted", "a", "b", etc.)
Microelectronics Journal, VoL 23, No. 3 ili iili iiiiiil ~i!i!il~
Including documentation, the translation generated 860 lines of code. The translation proved to be efficient and the structure of the original statechart description was clearly preserved in the code. Since the transformation between statechart feature and VHDL construct is one-to-one, the code grows linearly with increases in statechart complexity. Simulations using the Intermetrics tool set verified the correct operation of the VHDL code.
are packaged as global signals. Each hierarchical state is mapped as an entity to preserve the structure of the system and a manager process is included in each hierarchical state to activate and deactivate internal states, in addition to handling default and historical entries into the state. Concurrent networks are defined within block constructs where signals can be declared locally. Listing 1 was generated from the "update-alarm" state. The arc process is declared as a component and instantiated for each arc in the description. Each leaf state in the description results in a signal declaration. The manager process is responsible for activating, deactivating and resetting states within. The process is also responsible for activating the correct internal state upon state activation depending on the entry mode, either default or historical.
LISTING 1
Several problems were encountered in the design of the translation strategy. Statecharts have the ability to execute processes when certain states are reached. These actions can be asynchronously suspended or terminated. VHDL does not have semantics for proper process control. A possible way around is the inclusion of special clauses in the process's wait statements. However, this does not provide a
VHDL code generated from update-alarm section of Fig. 1
- - WATCH: VHDL description of David Harel's digital watch - - statechart description written by Arthur Woo, February, 1991 - - MODULE: U P D A T E A L A R M architecture body use WORK.SIGNALS.all; - - receive broadcasted events architecture u p d a t e a l a r m _ _ b o d y of update___alarm is component arc port ( ENABLE, SET, GRST: in bit; ARCIN: in bit; CLR: out bit; ARCOUT: out bit; LRST: in bit ); end component; for all:arc use entity WORK.arc(arc body); signal enable, reset: bit; signal U P D A T E H O U R , UPDATE
MIN, UPDATE
TENMIN: state__type := ('0', '0');
begin
--
super state manager process(default out reset, inl state, outl variable f i r s t e n t r y : boolean := true; begin
reset)
225
(D i
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A. C. Woo and L. E. Peppard/ System-Level Modelling in VHDL
-0 (D
rr if (not default out reset'stable and default out reset = '1') or (not out1 reset'stable and out1 reset -- '1') then - - default state exit enable < = '0'; - - reset < = '1', '0' after 1 ms; default out state < = '0'; elsif (not in1 state'stable and in1 state = '1') then - - entry by arc crossing reset < = '1', '0' after 1 ms; enable < = '1'; default out state < = '1'; f i r s t e n t r y := false; end if; end process;
U P D A T E MIN.state < = in1 state; in1 reset < = U P D A T E MIN.reset;
--
connect states to ports
out1 state < = U P D A T E HOUR.state; UPDATE HOUR.reset < = o u t 1 reset; arc1: arc port map ( enable, C, reset, UPDATE__MIN.state, U P D A T E MIN.reset, U P D A T E TENMIN.state, U P D A T E T E N M I N . r e s e t ); arc2: arc port map ( enable, C, reset, U P D A T E TENMIN.state, U P D A T E TENMIN.reset, UPDATEHOUR.state, UPDATEHOUR.reset ); end u p d a t e a l a r m _ _ b o d y ;
solution to delayed events. Once a waveform has been scheduled on a signal, the process loses control over it. Should the process become suspended or terminated, the process has no way of reversing its effects without possibly affecting events from other processes.
3. Petri Nets Petri nets are another visual modelling paradigm for representing systems at the uninterpreted level. Several classes of Petri nets exist, but for the purposes of this paper the most basic definition will be used. For a more complete description of Petri nets, readers are referred to refs. 4 and 5, two informative texts on the subject.
226
The most basic interpretation of nets, referred to as condition/event nets, consists of two elements: conditions, represented graphically as circles, and events, represented as line segments. Directed arcs between conditions and events describe the movement of tokens through the net. A condition is said to be valid if it contains a token. During the execution of the net, events occur causing some conditions to become invalid while validating others. Execution rules for the net specify how tokens are placed into and taken from conditions. An event is "active" when all of its input conditions are valid, i.e. it contains a token, and all of its output conditions are not valid. An event "fires" when active by removing a token from each input condition and
O
Microelectronics Journal VoL 23, No. 3 i¸
ill
Oi
O m
placing a token in each output condition. A maximum of one token is allowed in each condition and, by definition, an event occurs in zero time (Fig. 2). In this implementation of Petri nets in VHDL, conditions are mapped into resolved signals of type integer and events are modelled as processes sensitive to input and output conditions. The event process waits for tokens to appear on all of its inputs. If all ouTut conditions are free at this point, tokens are transferred from input conditions to output conditions. It is possible for several arcs to lead into a condition which translates into more than one driver to a signal; therefore, a resolution function must be defined. Since the dynamic behaviour of Petri nets ensures that at most one driver will be active at any instant of time, a simple resolution function which returns the value of the single driver has been implemented.
LISTING 2
consumer
busy ~ r e a d y
channel
~4
producer
busy~eady
Fig. 2. Simple Petri net description of a producer and consumer process communicating over a channel. Listing 2 is a sample of VHDL code generated using this translation strategy. The event process, whose code is not listed, executes the behaviour as outlined above. Simulations show that the behaviour of the simulated code matches the behaviour of the net. The structure of the net is clearly evident from the code. The generic nature of the transition entity makes the code efficient and will ensure linear growth of the code for increasing net complexity.
VHDL listing for Petri net of Fig. 2
- - Petri net example: consumer/producer processes using a -single channel, written April 1991 by Arthur Woo
use WORK.PETRI PACKAGE.all; architecture main__body of main is component transition generic (num inputs: positive; num outputs: positive; seed: integer ); port ( input: inout integer vector(1 to num inputs) bus; output: inout integer_ vector(1 to num__ouTuts ) bus); end component; for all:transition use entity WORK.transition(transition body); - - for each state there is one signal declared signal consumer__busy: integer__resolved register := 0; signal consumer__ready: integer resolved register := 0; signal producer__busy: integer__resolved register := 0; signal producer..ready: integer resolved register := 0; signal channel: integer__resolved register := 0;
be~n
227
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~ m
<
A. C. Woo and L. E. Peppard/ System-Level Modelling in VHDL
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process - - problems with simulation tool force this strange syntax begin consumer___busy <= 1 after 1ms; consumer busy <= transport null after 2ms; producer___ready <= 1 after 1ms; producer___ready<= transport null after 2ms; wait; end process; - - each transition is instantiated here el: transition generic map (num inputs=> 1, num outputs=> 1, seed => 227 ) port map (input(l) => consumer busy, output(l) => consumer ready); e2: transition generic map ( num__inputs => 2, num___outputs=> 1, seed => 431 ) port map (input(l) => consumer ready, input(2) => channel, output(l) => consumer busy); e3: transition generic map (num inputs=> 1, num outputs=> 1, seed => 67 ) port map (input(l) => producer busy, output(l) => producer ready ); e4: transition generic map ( num..__inputs=> 1, num..__outputs=> 2, seed => 115 ) port map (input(l) => producer_, ready, output(l) => producer..___busy, output(2) => channel); end main.__body;
Although the translation satisfied all criteria as stated previously, several issues again were raised during the design of the translation strategy. The lack of global variables which consequendy forced the use of global signals produced several inefficiencies in the simulation, namely the implementation of a resolution function and unnecessary maintenance of signal attributes. The lack of features in VHDL to handle the non-deterministic nature of Petri nets was another problem. To overcome this, a random delay was incorporated in the event behaviour. In this way, the random ordering of simultaneous events was possible. One consequence of the random delay is that time no longer has meaning, as can be seen in Listing 3. This may cause complications in trying to interface a Petri net model with other models with timing parameters.
228
Another weakness of the models' non-deterministic features is the lack of a random number generator in VHDL. Cerney et al. [6] have addressed this issue. Unfortunately the implementation of a random number generator is complex due to the concurrent nature of VHDL. The inclusion o f such a function in the VHDL standard would eliminate this coding inefficiency. The function used in this experiment is simple but serves to demonstrate the effectiveness of the translation.
4. Discussion The goal of this work is to explore the potential in VHDL to capture high-level system models described in established modelling paradigms. The design of translation strategies from Petri nets and statecharts
Microelectronics Journal, Vol. 23, No. 3 !~
i¸ ;
i~iii~iiill ii~oiiiiiii!il i!ii: LISTING 3
Results from Petri net simulation VHDL Report Generator SIGNAL NAMES
TIME (MS) 0 +1 1 17099 +1 19666 +1 31123 +1 32829 +1 33979 +1 50763 +1 55910 +1 59982 +1
PRODUCER__BUSY 0
PRODUCER___READY 0 0 1
1
0
0
1
CHANNEL 0
0
0
1
1
0
into VHDL has pointed out some of the strengths and weaknesses of VHDL to fulfil this purpose.
The successful translation of both Petri nets and statecharts into VHDL has proven the feasibility of high-level modelling in VHDL. Several features can be identified as key to this success. They include constructs such as the entity declaration to mimic exactly the structure and the hierarchy of the original model. The signal storage element allowed the connectivity to be duplicated and thus provided a means of communications between processes. Algorithmic descriptions of the entity behaviour allowed VHDL to match the dynamic behaviour of the original model. Another important feature of VHDL which allows the capture of high-level models is the ability to describe concurrent as well as sequential actions.
CONSUMERREADY 0
0
1
1
0
0
1
1
0 1
CONSUMER___BUSY 0 0 1
1
1
One of the weaknesses in using VHDL for high-level modelling is the lack of global variables. Global variables are purposely ruled out in the present standard for good reason. Problems of mutual exclusion are avoided by using global signals with their associated resolution function, but the overhead of executing this function along with maintaining signal attributes adds to the inefficiency of the simulation. A compromise solution may be the creation of a hybrid signal/variable type. It would be used like a register signal but would allow only one or fewer drivers at a time making the resolution function unnecessary. None of the attributes of signals would be associated with the hybrid type making it more efficient in simulation. Such a storage type would be ideal for both Petri net and statechart modelling. The lack of a random number function is also a
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weakness. Such a function could easily be made part of the standard since its inclusion will have no sideeffects.
features in VHDL to handle non-determinism in modelling paradigms. References
5. Conclusions
This paper has shown two modelling paradigms suitable for uninterpreted modelling of complex VLSI systems and has presented original strategies for their translation into VHDL. Criteria for the translations have been stated and used as the basis for evaluating the potential in VHDL in capturing these high-level models. Although translations have been proven possible, several problems were encountered, namely the lack of asynchronous control over process execution, the inefficiencies of global signals when used as global variables, and the lack of
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[1] F. Hady, J. Aylor, R. Williams and R. Waxman, Uninterpreted modeling using the VHSIC hardware description language (VHDL), Proc. Int. Conf. on Computer Aided Design, 1989, pp. 172-175. [2] R. Auletta and J. Aylor, A non-interpreted model for digital system design, Proc. IEEE, SOUTHEASTCON, Richmond, VA, 1986, pp. 296-299. [3] D. Harel, Statecharts: A visual formalism for complex systems, Science of Computer Programming, 8 (1987) 231-274. [4] J. Peterson, Petri Net Theory and the Modeling of Systems, Prentice-Hall, Englewood Cliffs, 1981. [5] W. Reisig, Petri Nets: An Introduction, Springer-Verlag, Berlin, 1985. [6] E. Cerny, M. Aboulhamid and S. Curry, Some elements for high-level modelling in VHDL, Proc. Canadian Conference on Very Large Scale Integration, 1989.