System Software support for distributed real-time systems

The Journal of Systems and Software 53 (2000) 245±264

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System Software support for distributed real-time systems Yacine Atif * School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, Singapore Received 15 December 1998; received in revised form 16 February 1999; accepted 10 May 1999

Abstract In this paper, we consider a scalable distributed-memory architecture for which we propose a problem representation that assigns real-time tasks on the processing units of the architecture to maximize deadline compliance rate. Based on the selected problem representation, we derive an algorithm that dynamically schedules real-time tasks on the processors of the distributed architecture. The algorithm uses a formula to generate the adequate scheduling time so that deadline loss due to scheduling overhead is minimized while deadline compliance rate is being maximized. The technique we propose is proved to be correct in the sense that the delivered solutions are not obsolete, i.e. the assigned tasks to working processors are guaranteed to meet their deadlines once executed. The correctness criterion is obtained based on our technique to control the scheduling time.To evaluate the performance of the algorithms that we propose, we provide a number of experiments through a simulation study. We also propose an implementation of our algorithms in the context of scheduling real-time transactions on an Intel-Paragon distributed-memory multiprocessor. The results of the conducted experiments show interesting performance trade-o€s among the candidate algorithms. Ó 2000 Elsevier Science Inc. All rights reserved. Keywords: System Software; Scheduling and resource allocation; Distributed real-time systems; Performance evaluation

1. Introduction Real-time task scheduling on a multiprocessor architecture is characterized as sequencing a set of tasks and assigning them to processors of the system such that each task's time constraints are satis®ed. Based on the time at which scheduling is performed, real-time scheduling algorithms have been divided into two categories, namely static and dynamic. In this paper, our focus is on dynamic algorithms. These algorithms (Mok, 1983; Sprunt et al., 1989; Zhao et al., 1987a,b; Sha et al., 1988; Schwan and Zhou, 1992; Shen et al., 1993) produce schedules on line in hope of using more comprehensive and up-to-date information about the tasks and the environment. Due to the on-line nature of their problem solving, dynamic algorithms must be ecient, since their complexity directly a€ects the overall system performance (Ramamritham and Stankovic, 1984; Stankovic et al., 1995; Atif et al., 1998). Sequencing and assignment of real-time and non-real-time tasks on multiprocessor architectures has been formulated in the past as a search for a schedule in a search space. Many of the existing techniques for scheduling ordinary tasks on a multiprocessor architecture adopt an assignment-oriented search representation (Hamidzadeh et al., 1995; Ma et al., 1982; Shen and Tsai, 1985). Techniques for scheduling real-time tasks on uniprocessor and multiprocessor architectures have generally adopted a sequence-oriented search representation (Shen et al., 1993; Yuan-Geng Huang et al., 1989; Zhao et al., 1987a,b). An assignment-oriented representation emphasizes the choice of processors to which tasks are assigned, in order to satisfy the problem objectives. A sequence-oriented representation emphasizes the order in which tasks should be scheduled, in order to satisfy the problem objectives. Assignment-oriented representations are naturally suitable for task assignment in multiprocessor architectures. The sequence-oriented representations are commonly chosen for real-time scheduling, since they emphasize the ordering of the tasks considering task characteristics such as deadlines.

*

Tel.: +65-790-6371; fax: +65-792-2971. E-mail address: [email protected] (Y. Atif).

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Dynamic techniques for scheduling real-time tasks on a multiprocessor architecture using an assignment-oriented representation have rarely been discussed. Performance implications of using such techniques and their comparison with sequence-oriented techniques have not been fully studied. This is a major issue that we address in this paper. Many of the existing dynamic algorithms for scheduling real-time tasks ignore the direct e€ect of factors such as when scheduling is performed, where scheduling is performed and the scheduling duration, on schedule quality. This issue is also addressed in this paper. The algorithms proposed in the literature are either static, thus lacking the ability to adapt their performance to the changes in the environment or dynamic, thus requiring a time-complexity control. Time-control complexity has up to our knowledge not been addressed explicitly. Implicitly, however, some algorithms do try to minimize the timecomplexity by limiting the search space but at the expense of limiting ± also ± the solution space. Our algorithm's objective is to explicitly control the time-complexity. The algorithm self-adapts its search cost to ®nd a schedule within the complete solution space. A main contribution of the paper is to evaluate the trade-o€s between dynamic techniques that use an assignmentoriented representation and those which use a sequence-oriented representation. Another contribution is to address the problem of deciding when to invoke the scheduling process and what the magnitude of the scheduling quantum should be to minimize scheduling overhead and to guarantee deadlines of scheduled and arriving tasks. As part of the paper, we propose a technique to dynamically schedule a set of aperiodic, non-preemptable, real-time tasks on a distributed-memory multiprocessor. The proposed technique searches for a schedule in an assignmentoriented representation of the problem. It uses a processor for scheduling and masks the scheduling overhead by overlapping scheduling with the execution of other tasks. Our technique automatically controls and allocates the scheduling time in order to minimize the overhead and to minimize deadline violation of scheduled and arriving tasks. We evaluate our technique by comparing its performance with another dynamic scheduling technique that uses a sequence-oriented representation. The results of our experiments show signi®cant performance improvement for our technique, in terms of deadline compliance and in terms of scalability as the number of processors increases. The results also reveal interesting performance trade-o€s among candidate algorithms. The remainder of this paper is organized as follows. Section 2 speci®es the model and problem to be addressed. Section 3 introduces our scheduling technique. As part of this section, we discuss the assignment-oriented representation of our technique and demonstrate some of its characteristics. Section 4 provides an experimental evaluation of our techniqueÕs performance. Finally, Section 5 concludes the paper with a summary of the results. 2. Model and problem In this paper, we address the problem of scheduling a set T of n aperiodic, non-preemptable, independent, real-time tasks Ti with deadlines, on the m processors Pj of a distributed-memory multiprocessor architecture. Aperiodic tasks are tasks with arbitrary arrival times whose characteristics are not known a priori. In a distributed-memory architecture, each processor has its own local memory. Processors access remotely located data by exchanging messages. Memory access delays are non-uniform in such an architecture, since a processor can access data in its local memory more quickly than it can access data in other processorsÕ memory (by message pasing). Since data objects can be distributed among local memories of a distributed architecture, and since each task Ti references a subset of the data objects, Ti will have an anity for the processors Pj that hold Ti Õs referenced data objects in their local memory. A parameter in a distributed architecture is the degree of anity among tasks and processors. This is an indicator of the degree of data replication and can be de®ned as the probability that a task Ti has anity with a processor Pj . A high degree of anity means that many data objects are replicated on several processors. Namely, each processorÕs local memory has a copy of most data objects, and thus, any given task has anity with several processors. A low degree of anity, on the other hand, means that data objects are not replicated and any task has anity with only few processors. ``Anity'' refers to data locality for a particular task. The needed data by a task may not be stored in the local memory of the processor to which that task has been assigned to execute. Inter-processor communication is required then to copy the data to the local memory of the processor to which the task has been assigned to execute. Such interprocessor communication incurs a communication cost that will delay the execution of the task possibly beyond its deadline. We use ``anity'' degree in our model as a parameter that measures the probability of inter-processor communication frequency. A high anity degree will decrease inter-processor communication occurrences whereas a low-level degree will increase them. Each task Ti in T assigned to execute on processor Pj is characterized by a processing time pi , a memory access cost cij , arrival time ai , and a deadline di (see Table 1 for de®nition of these and other notations). cij is a notion of anity between task Ti and processor Pj . In our model, cij is 0 if Ti has anity with Pj (i.e. Ti Õs referenced data reside on Pj Õs

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Table 1 Notation Symbol

De®nition

Batch Pj Ti …Ti Pj † pi cij ai di tc Qs AQs ts te RQs ssij seij asij aeij Slacki

A set of available tasks to schedule A processor …1 6 j 6 m† A task …1 6 i 6 n† Assignment of Ti to Pj for execution Worst-case processing time of Ti Memory access cost of task Ti on processor Pj Arrival time of Ti Deadline of Ti Current time Allocated scheduling quantum (upper bound) Actual duration of scheduling (AQs 6 Qs ) Time at which scheduling starts The time at which scheduling ends …te ˆ ts ‡ AQs † The remaining time of scheduling …RQs ˆ Qs ÿ …tc ÿ ts †† Scheduled start time of Ti on Pj Scheduled end time of Ti on Pj …seij ˆ ssij ‡ pi ‡ cij † Actual start time of Ti on Pj …asij ˆ te ‡ ssij ) Actual end time of Ti on Pj …aeij ˆ te ‡ seij † The maximum time by which the start of Ti Õs execution can be delayed from time tc , without missing its deadline The waiting time before Pj becomes available for executing additional tasks Ti 2 Batch ^ …aeij 6 di †

Loadj Feasible …Ti Pj †

local memory) and it is some constant C if Ti does not have anity with Pj . A non-zero cij implies that a non-local memory access cost is incurred if Ti is scheduled to execute on Pj . In distributed architectures that use cut-through routing protocols (e.g. warmhole), non-local memory access costs are independent of the distance between the accessing processor and the target memory, and can be accounted for by a constant like C in our model (Kumar et al., 1994). We de®ne a task-to-processor assignment (Ti Pj ) to be feasible, if Ti ®nishes its execution on a processor Pj before its deadline. This condition is signi®ed by the inequality te ‡ ssij ‡ pi ‡ cij ( di (see Table 1 for the de®nition of these notations). The non-uniform memory access delays cij give this cost model a non-uniformity in feasibility of executing a task on di€erent processors. Namely, a task that is feasible on one processor may not be feasible on another processor, even if this task is the only one assigned to either processor for execution. Accounting for the scheduling cost in de®ning feasibility is important. In our model, this is considered by the term te which signi®es the time at which a scheduling phase ends. Note that knowing te is important in guaranteeing a task assignmentÕs feasibility. By explicitly controlling and allocating the scheduling time, our proposed algorithms can determine te and account for it in the cost model. A schedule, in our model, is de®ned to be feasible, if all the task assignments included in that schedule are feasible. If a schedule includes all the tasks in the batch (see Table 1 for the de®nition of a batch), then it is considered to be complete. Otherwise, it is referred to as a partial schedule. The objectives of our scheduling algorithms are as follows: · Maximize deadline compliance, i.e. maximize the percentage of tasks whose deadlines are met. · Maximize scalability, i.e. increase deadline compliance as the number of processors increases.

3. Real-time self-adjusting dynamic scheduling (RT-SADS) RT-SADS performs a search for a feasible schedule in an assignment-oriented search representation. It uses a dedicated processor to perform scheduling phases concurrently with execution of real-time tasks on other processors. The input to each scheduling phase j is a set of tasks (i.e. Batch(j)). Initially, Batch(0) consists of a set of the arrived tasks. At the end of each scheduling phase j, Batch(j ‡ 1) is formed by removing, from Batch(j), the scheduled tasks and tasks whose deadlines are missed, and by adding the set of tasks that arrived during scheduling phase j. Note that tasks in Batch(j) will not enter Batch(j + 1) or later batches, if they are scheduled in phase j (i.e. they will not be reconsidered for scheduling later). Instead, they form a schedule Sj which will be delivered to the ready queues of the working processors. Thus, the tasks in Sj are executed by the working processors while scheduling of Sj‡1 is in progress on the scheduling processor. In this section, we ®rst describe the search representation of our scheduling problem. We

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then show the basic steps performed by RT-SADS in a scheduling phase. The discussion of mechanisms for allocation of scheduling time in RT-SADS will then follow. Next, we discuss mechanisms for prediction of time-constraint violation in RT-SADS and the algorithmÕs ability to guarantee deadlines of scheduled tasks. A cost model that RTSADS can use to balance the load among processors and to minimize total execution time is discussed thereafter. A speci®cation of RT-SADS in pseudo-code format is included in Appendix A at the end of the paper. 3.1. Scheduling representation Scheduling can be represented as the problem of incrementally searching for a feasible schedule in a graph representation G…V ; E† of the task space. G in our representation of the problem is in the form of a tree. The vertices vi 2 V in G represent task-to-processor assignments …Ti Pj †. A partial path …vi ; vj ; . . . ; vk † from the root vi to a vertex vk in G represents a partial schedule that includes all task assignments represented by vi ; vj ; . . . ; vk . The edges …vi ; vj † 2 E represent extending the partial schedule by one task-to-processor assignment. By extending a schedule (or path), one task assignment at a time, a feasible schedule is incrementally built. Thus, schedule construction proceeds from one level in G to the next level. Complete schedules, if they exist, will be at the leaves of G. The incremental schedule construction allows a dynamic algorithm (as the one presented later in this section) to produce a partial schedule which is feasible at any point during scheduling. This allows the algorithm to be interrupted at the end of any iteration and still produce feasible schedules. To choose a new task to add to the schedule and to assign that task to one of the processors, we need to evaluate and compare a set of candidate vertices of G with one another. The candidate vertices are stored in a candidate list CL. A constraint on the candidate vertices in CL is that they must represent feasible task-to-processor assignments. Thus, feasibility tests are applied to di€erent vertices in G to identify the valid task assignments that can be added to the partial schedule. Another mechanism for evaluating vertices may be a cost function that we maximize or minimize to achieve a set of objectives. Each vertex will be assigned a value using this function. Yet another evaluation may consist of computation of a heuristic function associated with each vertex to indicate priority or degree of promise of that vertex. We shall investigate the e€ect of cost functions and heuristics in later sections. In the remainder of this section, we assume feasibility tests to be necessary components of a real-time scheduling algorithm. We discuss the interaction of such tests with the search representation in the context of dynamic scheduling. As we mentioned earlier, a vertex (or a task-to-processor assignment) is feasible, if it represents a task assignment …Ti Pj † in which deadline of Ti is met. During scheduling, infeasible vertices are rejected and their entire subtree is pruned from further investigation. The reason for this prunning is that if a vertex is infeasible, then all the schedules represented in that vertexÕs subtree will also be infeasible. Upon encountering an infeasible vertex, the search will continue by examining other vertices for inclusion in the schedule. Consideration of other vertices may involve backtracking to other branches in G. We de®ne backtracking as a situation in which the search cannot extend the current partial path (or schedule) further and switches to examine another partial path for extension. The nature of backtracking depends on the search strategy and the search representation used. Backtracking may result from consideration of optimizing factors, as well as from consideration of vertex feasibility. We de®ne dead-end as a situation in which no other feasible candidates remain to be considered for extending a schedule (i.e. when CL is empty). A dead-end signi®es that extending any partial path (i.e. partial schedule) in G to include another task assignment will result in an infeasible schedule. The topology and semantics of G depend on the search representation used. In this paper, we consider an assignment-oriented representation. In such a representation (see Fig. 1), at each level of G a task Ti is selected and the search decides to which processor Pj task Ti should be assigned. At the following level, another task (e.g. Ti‡1 ) is selected and assigned to one of the processors and so on. Note that at each level, all processors are considered for assignment again, even if they already have tasks assigned to them. Each vertex in G P has m children and G will have n n levels. The size of G grows exponentially with m and n. The space size is calculated as iˆ0 mi and the branching factor at each level remains constant (i.e. m). The search representation allows consideration and reconsideration for the way tasks are sequenced and assigned. However, the emphasis is more on assignment than on sequencing. A major issue in the search space is in the way it a€ects backtracking. Upon encountering an infeasible vertex representing task assignment …Ti Pj †, backtracking will consider assigning Ti to a di€erent processor. Backtracking can undo or resequence tasks on all processors. To clarify the notion of backtracking in this representation, consider the example shown in Figs. 2 and 3. In the example, we assume that there exist four processors P1 ; P2 ; P3 and P4 in the system and that there are four available tasks T1 ; T2 ; T3 and T4 . Let us assume that tasks T1 and T2 are feasibly scheduled, one after another, on P1 and P2 , respectively (solid arrows in Fig. 2), and that assigning task T3 to processor P3 makes that task infeasible (Fig. 2(a)). The assignment-oriented representation considers assigning T3 to a di€erent processor such as P4 if such a processor exists (Fig. 2(b)). This consideration is depicted in Fig. 2 with the dotted arrow

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Fig. 1. Assignment-oriented scheduling model.

Fig. 2. Assignment alternatives.

Fig. 3. Example of scheduling alternatives.

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labelled b. From the nature of backtracking in this example, we note that if the number of processors is large, the search is likely to ®nd an empty processor on which to place T3 . In subsequent steps, P3 will be considered again for executing other tasks feasibly. Thus, we expect this representation to facilitate scalability issues. To clarify the search process for a schedule using the above representation, consider the example shown in Table 2. The scheduling problem here would be to ®nd a feasible schedule for four tasks T1 ; T2 ; T3 , and T4 which entered the system simultaneously at time 0. Let us assume that our system consists of three processors P1 ; P2 , and P3 . The tasks have anity with some processors as shown in Table 2. Let us also assume that the non-local memory access cost C is 20 time units. In this example, the only feasible schedule for these tasks is the one shown in Fig. 4 (i.e. f…T1 P1 †; …T2 P2 †; …T3 P2 †; …T4 P3 †g). In Fig. 5, a search procedure which strives to reach a feasible schedule is shown. The ®gure shows the vertices in the search space that have been examined. The white vertices signify feasible task-to-processor assignments. The vertices with grey shading signify infeasible task-to-processor assignments and those with line shading are leaves signifying

Table 2 Example of a scheduling problem Task T1 T2 T3 T4

ai 0 0 0 0

pi

di

Anityi

2 8 12 3

9 11 24 20

P1 P2 P2 P3

Fig. 4. The valid schedule for the example in Table 2.

Fig. 5. Scheduling representation for the example in Table 2.

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feasible task assignments which result in a complete, feasible schedule. The search starts at the root with the aim to reach a leaf of the search tree. Upon examination of each vertex, a feasibility test is performed to test whether that vertexÕs task meets its timing constraints. The search starts by considering assignment of task T1 to processor P1 . This assignment passes the feasibility test. In the next step, the search considers assigning T2 to P1 , which turns out to be infeasible. Processor P2 is considered next for executing T2 . This assignment is feasible and the search attempts to extend the partial schedule built so far (i.e. f…T1 P1 †; …T2 P2 †g) with one more task assignment (i.e. …T3 P1 †) which is not feasible. Assignment …T3 P2 † is considered next which is feasible. The remaining task to be scheduled, at this point, is T4 . Executing T4 on P1 and P2 will not be feasible but executing it on P3 is indeed feasible. This last assignment results in successfully ®nding a complete, feasible schedule (i.e. f…T1 P1 †; …T2 P2 †; …T3 P2 †; …T4 P3 †g) similar to the one shown in Fig. 5. In a dynamic environment, the e€ect of search representation on performance is more prominent. Dynamic algorithms are forced to use heuristics such as limited backtracking (Zhao et al., 1987a,b; Ramamritham et al., 1987; Stankovic et al., 1987), limit on the depth of search, and/or an upper bound on the time of search (Atif et al., 1998), that prune the search space signi®cantly, in order to reduce the scheduling complexity. By further reducing the searchÕs options to explore during dynamic scheduling, it is more likely that the search will terminate (e.g. due to reaching a dead-end or due to reaching a bound on scheduling complexity) at a shallow depth. This will result in assignment of tasks only to a fraction of the processors in the system during each scheduling phase. Thus, it may so happen that many processors remain idle while others are heavily loaded. This will contribute further to such representationsÕ incapability to scale up their performance as the number of processors increases in the system. Our experiments in later sections will validate these conjectures. 3.2. Scheduling phase In the following discussion, a vertex in task-space G is de®ned to be generated, when enough memory for a data structure representing that vertex is allocated and when the vertex and its attributes are evaluated and stored in the data structure. An evaluation of a generated vertex vi consists of computing the task-to-processor assignment that vi represents, computing the partial schedule that the path leading to vi represents, and performing a feasibility test to see whether that schedule is feasible. Other evaluations may consist of computation of a cost function or a heuristic function associated with that vertex which indicates the value or priority of that vertex. A vertex is de®ned to be expanded when its successor vertices are generated. The successors of a vertex vi are the set of all the k vertices fv1 ; . . . ; vk g which are connected to vi via direct links …vi ; v1 †; . . . ; …vi ; vk †. Scheduling phase j starts at the root (i.e. empty schedule) of G which represents the current vertex CV, and the current partial schedule CPS. In one iteration of a scheduling phase j, CV is expanded and its feasible successors are kept in a list. If a heuristic and/or a cost function exists, the list of feasible successors is sorted according to heuristic/ cost values with the highest-priority vertex in front of the list. The vertices of this list are then added to the front of the list of candidate vertices, CL. The vertices in CL are prospects for extending CPS to include more task assignments while remaining feasible. In the following iterations, the ®rst vertex in CL is removed from the list and is expanded as the new CV. CPS is now the path from the root to this vertex. It may so happen that none of the successors of an expanded vertex pass the feasibility test. In such a situation no new vertices are added to CL and the search will backtrack to explore other candidates by expanding the ®rst vertex in CL which, in this case, is not an extension (successor) of the current partial path and comes from another path in G. The iterations of a scheduling phase continue until either a leaf vertex is reached, until a dead-end is reached (i.e. CL becomes empty), or when the limit Qs (j) on the duration of scheduling phase j is reached. The result of each scheduling phase j is a feasible partial or complete schedule Sj . During the execution phase j, the tasks in Sj are executed by their assigned working processors. The tasks which were not scheduled during scheduling phase j are merged with the newly arrived tasks to form Batch(j ‡ 1). Tasks in Batch(j ‡ 1) are then tested and those tasks whose deadlines have already been missed (i.e. fTi j…Ti 2 Batch…j ‡ 1†† ^ …pi ‡ tc > di †g) are removed from Batch(j ‡ 1). Next, we discuss RT-SADSÕs mechanisms for allocating the time duration of scheduling phases. 3.3. Allocation of scheduling time RT-SADS uses a novel on-line parameter tuning and prediction technique to determine the time and duration of a scheduling phase. The algorithm continually self-adjusts the allocated time Qs (j) of scheduling phase j using a set of criteria based on parameters such as slack, arrival rate and processor load. The motivation for designing such criteria is to allocate longer times to scheduling when the task slacks are large or when arrival rates are low, or when the working processors are busy executing tasks. Note that longer scheduling times allow RT-SADS to optimize longer and ®nd

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higher-quality schedules. When the slacks are small or the arrival rates are high, or when working processors become idle, scheduling durations are shortened to honor the deadline of scheduled tasks, to account for arriving tasks more frequently, and to reduce processor idle times. The allocated time of scheduling phase j is controlled by a criterion as shown in Fig. 6. The term k=k in this criterion is included, in order to stop a scheduling phase early in bursty arrivals, so that incoming tasks are accounted for soon after their arrivals. k denotes the task arrival rate and k is a coecient that can be set to control the average number of task arrivals during a scheduling phase. Under low arrival rates, the criterion of Fig. 7 will allow longer scheduling phases to optimize the tasks in the current batch and to allow a reasonable number of tasks to arrive to form the next batch. The term Min_Slack in Fig. 6 is included in the expression to limit the amount of time allocated to scheduling phase j so that none of the deadlines of tasks in the current batch are violated due to scheduling cost. This term, however, ignores the waiting time before a processor becomes available. If the minimum waiting time among working processors (i.e. Min_Load) is larger than the slack of a task, then the deadline of this task is missed anyway, even if it is scheduled and executed right away. In this case, the allocated scheduling time is extended to Min_Load providing the scheduling process with more time to improve the schedule quality. If, on the other hand, Min_Slack is larger than Min_Load, the allocated scheduling time is set to Min_Slack to increase the scheduling time at the expense of some processor idle time. To clarify the rationale behind the Max term of the expression in Fig. 6, consider the example depicted in Fig. 7. The ®gure shows four tasks which arrived during scheduling phase j ÿ 1 …j > 1† to form Batch(j). Min_Slack of Batch(j) in Fig. 7(a) is Slack3 . The schedule Sjÿ1 is assigned to the working processors P1 , P2 and P3 . P0 is designated as the scheduling processor. Min_Load, in this example, is Load3 and Min_Slack < Min_Load. If the allocated scheduling time Qs …j† is set to Min_Slack, then at the schedule delivery time, no task in Sj can immediately start execution because all the processors are busy executing their previous task assignments. More speci®cally, T3 would miss its deadline anyway since it has to wait for the assigned processor to be available. Thus, Qs (j) is set to Min_Load, to allow longer scheduling duration without any consequences due to extra scheduling time. Next, let us consider the expression for calculating

Fig. 6. Criterion for allocation of scheduling quantum.

Fig. 7. Example of scheduling-time allocation.

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scheduling quantum under the conditions shown in Fig. 7(b). Min_Slack of Batch(j) is again Slack3 and Min_Load is Load3 . This time Min_Slack > Min_Load, so Qs (j) is set to Min_Slack. Processor P3 will incur some idle time in return for a larger scheduling quantum. 3.4. Prediction of time-constraint violation RT-SADS predicts deadline violation of tasks based on a feasibility test that takes into account the scheduling time of a phase, as well as the current time, deadline, and processing time of tasks. Accounting for the scheduling time in the feasibility test ensures that no task will miss its deadline due to scheduling time. The test for adding a task assignment …Tl Pk † to the current feasible partial schedule CPS to obtain feasible partial schedule CPS0 in scheduling phase j is performed as shown in Fig. 8. Next, we provide a theorem that guarantees to minimize to 0 the number of scheduled tasks whose deadlines are missed during their execution. Theorem. The tasks scheduled by RT-SADS are guaranteed to meet their deadlines, once executed. Proof. The proof is done by contradiction. Let us assume that a task Tl 2 Batch…j† is scheduled on processor Pk during the jth phase and that Tl misses its deadline at execution time. This assumption leads to the following condition: te …j† ‡ selk > dl :

…1†

Here we are assuming that the execution of tasks in a schedule will start immediately after scheduling ends. On the other hand, RT-SADSÕs bound on scheduling time allocated to each phase ensures that te …j† 6 tc ‡ RQs …j†:

…2†

Combining (1) and (2) leads to tc ‡ RQs …j† ‡ selk > dl :

…3†

The feasibility test performed at time tc ensures that: tc ‡ RQs …j† ‡ selk 6 dl , contradicting inequality (3). Therefore, our assumption regarding deadline violation of Tl is false, which concludes the proof of the theorem.  3.5. Load-balancing A cost function that calculates the total execution time of a given partial schedule is used in a version of RT-SADS to compare di€erent partial schedules. An objective can then be to search for a schedule that minimizes this function. Such a schedule is the one that o€ers the most evenly balanced load among all processors. As part of calculating the total execution time of a schedule, the function must be able to determine the cost of executing tasks Tl on processors Pk . This cost is p1 ‡ clk , where pl is the processing time required to execute task Tl and clk is the memory access delay required to transfer any data objects, should Tl execute on Pk . At any point during scheduling phase j, the execution time cek for each processor Pk when tasks Tl are assigned to it is X …pl ‡ clk †; cek ˆ Loadk …j ÿ 1†Qs …j† ‡ …Tl Pk †

where Loadk …j ÿ 1† is the execution cost of processor Pk at the end of scheduling phase …j ÿ 1†. The total execution time for a schedule is determined by the processor that ®nishes executing its tasks last. So, the execution time CEi of the partial schedule represented by a path from the root in G to a vertex vi is the maximum of the cek values for all working processors, i.e., CEi ˆ Max‰cek Š;

where …1 6 k 6 m ÿ 1†:

One of the important features of RT-SADS's cost model is that it accounts for non-uniformity in the tasks' memory access delays when scheduled on speci®c processors. This model simultaneously addresses the tradeo€s between the

Fig. 8. Feasibility test of RT-SADS.

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two interacting factors of processor load-balancing and memory access costs. Another important feature of RTSADS's cost model is its adjustability to the degree in which these factors a€ect performance in the system. For example, in applications where the degree of anity is high and variance in task processing times is also high, this cost model e€ectively concentrates on balancing the processors' loads. In a system where the degree of anity between tasks and processors is low and where task processing times do not vary greatly, the cost model automatically emphasizes more heavily on the need for scheduling tasks on those processors which have greater anity with those tasks.

4. Experimental evaluation To evaluate the deadline scalability performance of the proposed technique, we provide below a simulation study followed by a distributed real-time database application that we implemented on an Intel Paragon distributed-memory multiprocessor. We start by describing the design and the results of the simulation study. To validate the obtained simulation results, we reveal the performance results of the implemented application. 4.1. Simulation In this section, we evaluate the deadline compliance and scalability of RT-SADS by comparing its performance with another dynamic algorithmÕs performance in a number of experiments. The other candidate algorithm uses a sequenceoriented representation and performs limited-backtracking to reduce the search complexity. In one set of experiments we study the e€ect, on performance, of search representation and mechanisms for controlling and allocating scheduling time. The results show that RT-SADS demonstrates improved performance in terms of deadline compliance and scalability. In another experiment, we evaluate the e€ect of load-balancing mechanisms on performance. By minimizing the total execution cost of partial schedules (see Section 4.1.4), RT-SADS balances the load among processors. This feature is compared against a mechanism that assigns tasks to processors in order of those processorsÕ earliest available time. The results show that RT-SADSÕs load balancing mechanism improves its performance. An experiment was also designed to study the e€ect of heuristics on the candidate algorithms. The purpose of a heuristic function (e.g. earliest-deadline-®rst) is to speed-up the search by prioritizing candidates for extending partial schedules. The results show improved performance for both candidate algorithms. The ®nal experiment studies the e€ect of the degree of anity on performance. The results of this experiment validate our expectations that RT-SADS adjusts well to different degrees of anity compared to the other algorithm which uses a sequence-oriented search representation. Twotailed di€erence-of-means tests were used to show the signi®cance of the di€erence in performance between candidate algorithms. 4.1.1. Experiment design In the experiments, a Poisson process was used to create a sequence of aperiodic task arrivals. The time window, within which arrivals were observed, was set to 100 time units. The arrival rate k was set to 2, 3 and 4 for di€erent data sets. The processing times pi of tasks Ti are uniformly distributed within the interval between 1 and 50 time units. A task assigned to a processor with which it has no anity will incur a memory access delay of 100 time units. The number of processors in the system ranged from 2 to 16. To account for the scheduling overhead incurred by RTSADS, we provide that algorithm with one less processor than the other candidate algorithm. Hence, in a system with a total of 16 processors, 15 working processors are left for RT-SADS to execute the assigned tasks. Deadlines di are uniformly distributed in the interval (Endi ; Dmax ) where Endi is the ®nish time of Ti assuming it starts at ai (i.e. Endi ˆ ai ‡ pi ), and Dmax is a maximum value a deadline can have and is calculated as Dmax ˆ Endi ‡ SFKd . SFKd is a parameter that controls the degree of laxity in task deadlines. Kd is ®xed to 3 in our experiments and the slack factor SF 1 was set to 4 and 6 for di€erent data sets. Larger SF values represent larger slack, whereas small SF values represent tight deadlines. The degree of anity between tasks and processors, de®ned as the probability that a given task will have an anity with a given processor, was set to 50% in one experiment and ranged from 10% to 100% in another experiment. Another parameter in our experiments is the constant coecient k of the term k=k of RT-SADSÕs criterion for allocation of scheduling time. This parameter implies the expected task batch size for each scheduling phase of RT-SADS and was set to 20 in the experiments. A metric of performance in our experiments is deadline compliance. Deadline compliance measures the percentage of tasks which have completed their execution by their deadline. Another related metric is scalability, which measures 1

The terms ``laxity'' and SF are used interchangeably in this section.

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the ability to increase deadline compliance as the number of processors increases. We measure the scheduling cost as logical time units. This time is calculated as NG/R, where NG is the number of vertices generated in the task-space G and vertex generation rate R is the number of vertices in G that a system can generate per unit of time. R is an indicator of processing-speed and is an architecture- and implementation-dependent parameter. We chose this formula to be able to measure scheduling e€ort in an architecture- and implementation-independent way. This formula is not only an indicator of the time complexity of the algorithms but (thanks to NG) it also provides insight into the memory requirements of the algorithms, as well. R was set to 10 in the experiments. Each experiment was run 10 times and the mean of the 10 runs was plotted in the ®gures. Two-tailed di€erence-of-means tests indicated a con®dence interval of 99% at a 0.01 signi®cance level for all the results collected in these experiments. 4.1.2. Candidate algorithms In our experiments, we compare three versions of the RT-SADS algorithm with three versions of a limited-backtracking algorithm that searches for feasible schedules in a sequence-oriented representation. In the basic version of RT-SADS, the algorithm uses only a feasibility test for evaluating a partial schedule or a task assignment. The tasks, in this version of the algorithm, are selected for assignment in a ®rst-come-®rst-served order (i.e. in order of arrival time). In another version of the algorithm (labelled RT-SADS-CF in the ®gures), the algorithm uses a total execution cost function, similar to the one discussed in Section 4.1.4, to assign values to partial schedules. In this algorithm, the feasible successors of the current partial schedule CPS (which are the same as CVÕs successors) are ®rst sorted in ascending order of their cost values and are then added at the front of the candidate list CL. This version of RT-SADS is expected to achieve better load-balancing across processors. In the third version of the algorithm (labelled RT-SADS-CF-EDF), in addition to using the cost function for minimizing total execution time, an earliest-deadline-®rst heuristic is used to prioritize the order in which tasks are considered for assignment. This heuristic is expected to improve deadline compliance by improving the search eciency within the time limit of a scheduling phase. Given the same amount of time, a more ecient search procedure is expected to feasibly schedule a larger number of tasks. Next, we discuss the details of the limited-backtracking algorithm and its three implementations. Despite their di€erences, many of the features of the limited-backtracking algorithms, discussed in our experiments, were inspired by the techniques reported in Zhao et al. (1987a,b), Ramamritham et al. (1987) and Stankovic et al. (1987). The search for a schedule in the limited-backtracking algorithm is performed in a sequence-oriented task-space G similar to that shown in Fig. 9. To keep the scheduling cost low, a limited-backtracking algorithm bounds the search complexity by specifying a preset backtracing level l. The search starts at the root (i.e. empty schedule) of G which represents the current vertex CV and the current partial schedule CPS. During an iteration, CV is expanded by generating l of its successors. The feasible vertices among the l successors are ®rst sorted according to their cost/ heuristic values (if such a cost/heuristic is used) with the best-value vertex in front. They are then added to the front of the candidate list CL. In the following iterations, the ®rst vertex in CL is removed from the list and is expanded as the new CV. CPS is now the path from the root to this vertex. If none of the l successors of an expanded vertex pass the feasibility test, the search will backtrack to explore other candidates. This is done by expanding the ®rst vertex in CL which, in this case, is not a child of CV and comes from another branch in G. The iterations of the limited-backtracking algorithm continue until either a leaf vertex is reached,

Fig. 9. Sequence-oriented scheduling model.

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or until the algorithm encounters a dead-end (i.e. CL becomes empty). Reaching a leaf signi®es that a complete feasible schedule was found. Upon termination of a scheduling phase, the scheduled tasks are executed by their assigned processors. The limited-backtracking algorithm uses an interleaved-scheduling-and-execution strategy as follows. During a scheduling phase, a processor Ps schedules a batch of tasks as explained above. As part of this scheduling process, Ps assigns tasks to all processors, including itself. Once the scheduling phase is completed, the task assignments are delivered to processors. The processors, including Ps , will then execute their assigned tasks. Ps will start scheduling phase j, once it has executed all the tasks that it assigned to itself during scheduling phase j ÿ 1. Choosing the appropriate level of backtracking l is an important task for the limited-backtracking algorithms, since it can a€ect these algorithmsÕ performance signi®cantly. We have previously shown (Atif et al., 1998) that it is dicult to choose a preset backtracking level that performs well under all conditions. For the comparison studies of our experiments, we chose backtracking level 2, since this level of backtracking (or others close to it) seemed to provide good performance under a variety of conditions. Three versions of the limited-backtracking algorithm were implemented and compared in the experiments. In one version (labelled BT2 in the ®gures), the algorithm uses only a feasibility test for evaluating a partial schedule or a task assignment. The processors in this version are selected for assignment in a round-robin fashion, without a preference for any particular order in a round. The tasks are considered for scheduling in a ®rst-come-®rst-served order. In another version of the algorithm (labelled BT2-LLP in the ®gures), the algorithm prioritizes the order in which processors are selected for task assignment, according to a least-loaded-processor-®rst strategy. This strategy is intended to improve load-balancing by giving priority to assigning tasks to those processors that have smaller loads. In the third version of the algorithm (labelled BT2-LLP-EDF), in addition to using the least-loaded-processor-®rst strategy, an earliest-deadline-®rst heuristic is used to prioritize the order in which tasks are considered for assignment. Using this heuristic, a feasible task assignment …Ti Pj † is given priority for being included in the schedule over another feasible assignment …Tl Pj †; if di < dl . This heuristic is expected to improve deadline compliance and to reduce scheduling complexity. Next, we discuss the experiment results. 4.1.3. Deadline compliance and scalability In this section, we present the results of an experiment that compared deadline compliance and scalability of RTSADS and BT2 under di€erent arrival rates, degree of laxity and number of processors. Figs. 10±13 show the results of these experiments. The X-axis in these ®gures shows the number of processors and the Y-axis shows the percentage of tasks whose deadlines are met (i.e. deadline compliance). A legend is provided for the ®gures in Table 3. An important point to note in the ®gures is that BT2 outperforms RT-SADS where there exist few processors in the system. As we discussed before, sequence-oriented algorithms (e.g. BT2) do have the capability to exploit the processing power of a few processors in the system. Since the number of processors is small, an emphasis on sequencing the tasks may provide an added advantage to an algorithm. In the extreme case of a uniprocessor system, for example, sequencing can lead to optimal results. As the number of processors increases, we note that RT-SADS outperforms BT2. This is due to RT-SADSÕs ability to exploit all the processors in the system at each level of the task space. The

Fig. 10. Deadline compliance (SF ˆ 4, k ˆ 2).

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Fig. 11. Deadline compliance (SF ˆ 4, k ˆ 4†.

Fig. 12. Deadline compliance (SF ˆ 6, k ˆ 2†.

®gures show that BT2 does not scale up its deadline compliance, whereas RT-SADS scales up to achieve very high deadline compliance even under tight deadlines and high arrival rates. When the number of processors is large, RTSADS outperforms BT2 by as much as an order of magnitude. We note from the ®gures that under tight deadlines (i.e. SF ˆ 4), higher arrival rates (e.g. k ˆ 4) cause deadline compliance to drop. We note, however, that BT2 is more sensitive to the increase in arrival rate than RT-SADS. Another point to note in the ®gures is that when the degree of laxity is larger (i.e. SF ˆ 6), the algorithms show an improved performance in terms of deadline compliance. For example, RT-SADS is capable of achieving near 100% deadline compliance when the degree of laxity is 6 and when arrival rate is 2 or 4. We notice again that BT2 su€ers more of a drop in performance than RT-SADS when the deadlines become tight. We conclude that RT-SADS adapts better to varying degrees of laxity and arrival rates. This feature can be attributed to RT-SADSÕs automatic adjustment of scheduling e€ort based on environment parameters such as slack and arrival rate. 4.1.4. E€ect of load-balancing Figs. 10±13 also show the results of an experiment that compared performance of RT-SADS-CF with BT2-LLP and the other candidate algorithms. The purpose of this experiment was to compare the performance that results from

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Fig. 13. Deadline compliance (SF ˆ 6, k ˆ 4†.

Table 3 Legend for Figs. 10±13 RT-SADS RT-SADS-CF RT-SADS-CF-EDF

BT2 BT2-LLP BT2-LLP-EDF

using a least-loaded-processor-®rst heuristic to balance the load with the performance that results from using a global cost function (similar to the one discussed in Section 4.1.2) that simultaneously addresses load-balancing and memory access delays. As the ®gures show, the least-loaded-processor-®rst heuristic helps BT2-LLPÕs deadline compliance only slightly. RT-SADS-CFÕs cost function, on the other hand, improves the algorithmÕs performance more signi®cantly. This improvement has a larger margin when degree of laxity is large (i.e. SF ˆ 6) and arrival rate is high (i.e. k ˆ 4). We note in Figs. 10, 11 and 13 that RT-SADS-CF scales up more than RT-SADS, since the gap between these algorithms widens as the number of processors increases. We conclude from this result that RT-SADS-CFÕs cost function results in a more balanced load among processors, particularly as the number of processors increases. Fig. 12 shows similar results except that for larger number of processors, RT-SADS-CFÕs and RT-SADSÕs performance converge. This result is attributed to the ease of scheduling tasks with loose deadlines that arrive slowly into a system with abundant resources. In such conditions, the system is under-loaded and an added cost function is not expected to improve performance much. 4.1.5. E€ect of heuristics Figs. 10±13 show the results of one more experiment, as well. This experiment compared RT-SADS-CF-EDF with BT2-LLP-EDF and the other candidate algorithms. The purpose of this experiment was to see the e€ect of adding a heuristic such as earliest-deadline-®rst to the candidate algorithms. As the ®gures show, the heuristic improves the performance of both BT2-LLP-EDF and RT-SADS-CF-EDF. We note, however, that this heuristic does not improve BT2-LLP-EDFÕs scalability. In situations, where the constraints on the system and on the tasks are not stringent, the earliest-deadline-®rst heuristic not only improves RT-SADS-CF-EDFÕs deadline compliance, but it also improves that algorithmÕs scalability. This characteristic is evident in Figs. 10, 11 and 13 which show a widening gap between RT-SADS-CF and RT-SADS-CF-EDF as the number of processors increases. In Fig. 12, which shows a situation with relaxed constraints, RT-SADS algorithmsÕ performance converges when the number of processors is large. This again is attributed to the fact that under these relaxed conditions, RT-SADS has enough time and resources to schedule the few tasks that make up each batch using just its basic search mechanism and feasibility test.

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4.1.6. E€ect of anity In this section, we present the results of our experiment that compared deadline compliance of RT-SADS-CF-EDF and BT2-LLP-EDF under varying degrees of anity. The purpose of this experiment was to provide insights into the e€ect of anity on performance. We expect low degrees of anity to hinder a sequence-oriented algorithmÕs performance more than it would hinder performance of an assignment-oriented algorithm. This phenomenon is attributed to the higher likelihood of facing a dead-end at a shallow depth of a sequence-oriented representation when the degree of anity is low. Fig. 14 shows the results of this experiment where the degree of laxity is 6, the arrival rate is 3 and the total number of processors in the system is 16. The X-axis in the ®gure shows the degree of anity which ranges from 10% to 100%. The Y-axis shows the percentage of tasks whose deadlines were met (i.e. deadline compliance). While RT-SADS-CFEDF maintains its performance at close to 100%, BT2-LLP-EDF reveals that it is very sensitive to the change in the degree of anity. By employing an assignment-oriented search strategy, RT-SADS can search for the processor which has the data needed by the considered task at each level and can schedule that task feasibly on that processor. RTSADS is also able to schedule a task on a processor which does not have anity with that task, if such an assignment is feasible. The sequence-oriented search representation employed by BT2 su€ers from an increasing number of scheduling failures when the degree of anity decreases. The lower the degree of anity, the higher the probability will be that the sequence-oriented search will face a dead-end at a shallower depth. Another point to note in the results shown in Fig. 14 is the performance of BT2-LLP-EDF when the degree of anity is high. This is similar to a situation where every data object is replicated on all processors and no delays are incurred, due to non-local memory accesses. We can see that even under these circumstances RT-SADS-CF-EDF performs signi®cantly better than BT2-LLP-EDF. We attribute this improved performance to RT-SADS-CF-EDFÕs self-adjusting criterion for allocating scheduling time and for its globally optimizing cost function. We note also that even under high degrees of anity, BT2Õs limited backtracking may prune the search space so that the search will reach shallow depths during each scheduling phase. This will cause only a fraction of the processors to be busy at each point in time and will result in poor performance. 4.2. Application In this section, we evaluate the deadline compliance scalability of RT-SADS algorithm in the context of a distributed real-time database application. In this application, an entire relational database is partitioned equally among processorsÕ private memories of an Intel Paragon multiprocessors and transactions are executed concurrently. To simplify this study, we assume read-only transactions. Our simple database and transaction model highlights the applicability of our algorithms and validates their performance on a distributed-memory multiprocessor architecture. The performance metric which we stress on in this study is deadline compliance scalability. That is, the system can be continuously expanded in complying with transactionsÕ deadlines up to the ``high-end'' by adding more hardware modules.

Fig. 14. Deadline compliance (SF ˆ 6, k ˆ 3†.

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Assuming the global database holds r tuples, we divide it into d sub-databases. Such division can be performed through a hashing function in order to speed up the location of a tuple with respect to the sub-databases. When mapped on a distributed-memory architecture, each sub-database resides in the local memory of a speci®c processor. Depending on the replication rate, multiple copies of a sub-database may reside in several local memories. A transaction is characterized by the attributesÕ values that transaction aims to locate in the distributed database. In order to execute transactions by their deadlines, a host processor is dedicated to perform a continuous scheduling process while the remaining processing units perform the actual execution of transactions. Executing a transaction would mean iterating a checking process among the tuples which partially match the attributesÕ values of the transaction. It is important for the scheduling process to evaluate the execution cost of a transaction beforehand in order to perform accurate scheduling decision. In order to re¯ect a transaction processing cost, we adopted the following estimation function: Execution Cost…q† ˆ kx‰IF key 2 F THEN Frequency of matching key values ELSE r=dŠ; where F is the set of attributes for which values are given in a transaction q and k is the processing time to execute one checking iteration. Hence, to estimate the execution cost of a transaction, the host processor maintains the global index ®le of the database. If a transaction provides a key value, the index ®le is used to evaluate the number of tuples a processing node would need to check in the worst-case in order to locate the records requested by that transaction. Therefore, this mechanism returns estimates of the transaction worst-case computation times which can be used by a scheduling algorithm like RT-SADS. 4.2.1. Experiment design The parameters con®guration for these experiments are as follows. Each sub-database holds 1000 records and 10 attributes. For simplicity, the attributesÕ domains are disjoint from each other among the sub-databases. A uniformly distributed item is generated for each attribute-value based on its domain. The sub-databases are indexed according to a speci®c key attribute say, attribute #1. A transaction contains a uniformly distributed number of given attributevalues. The values are picked equiprobably from their respective domains. In our experiments, we generated 1000 transactions. The transactionsÕ deadlines are proportionally generated based on the estimated transaction processing time. Deadline(q) ˆ SFx10x Estimated_Cost(q). SF values range from 1 to 3. A low value of SF signi®es tight deadlines whereas a high value of SF signi®es loose deadlines. In the ®gures, we use the term laxity which is equivalent to the deadline factor. Another parameter in our experiment is the replication rate of the databases. The replication rate has the same semantic as the task-to-processor anity. However, quantitatively they are inversely proportional. That is a high degree of anity is equivalent to a degree of replication rate. We divided the global database into 10 sub-databases. Based on the replication rate R, we copy the sub-databases in the local memory of the processing nodes. RÕs values ranged from 10% to 100%. In the extreme cases, a 100% replication rate would result in having the global database in the local memory of each processor, whereas a 10% replication rate would result in having each processor holding in its local memory, at most one copy of a sub-database. The number of processors ranged in our experiment from 2 to 10. Finally, we assume a bursty arrival of 1000 transactions which simultaneously reach the host node that is executing the scheduling task. The metric of performance in our experiments is deadline compliance. Deadline compliance measures the percentage of transactions which have completed their execution by their deadline. Another related metric is scalability, which measures the ability to increase deadline compliance as the number of processors increases. We measure the scheduling cost as the physical time required to run the scheduling algorithm. Each experiment was run 10 times and the mean of the 10 runs was plotted in the ®gures. Two-tailed di€erenceof-means tests indicated a con®dence interval of 95%. 4.2.2. Experiment results We compare RT-SADS-CF-EDF 2 algorithm which uses an assignment-oriented representation, with another dynamic algorithm that is equivalent to BT2-LLP-EDF1 that uses a sequence-oriented representation. Generally, the results con®rm our previous expectations (resulted from the simulation study) regarding the deadline scalability issue. 2

See Section 4.1.2 for a description of the candidate algorithms.

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Fig. 15. Scalability under low laxity (R ˆ 30% and SF ˆ 1).

Fig. 16. Scalability under medium laxity (R ˆ 30% and SF ˆ 2).

Figs. 15 and 16 show the scalability aspects in terms of meeting deadlines as the number of processors increases. In this experiment R was ®xed to a small value (i.e. 30%). In all parameters con®guration, RT-SADS-CF-EDF outperforms the sequence-oriented based algorithm BT2-LLP-EDF, by as much as 60% as the number of processors increases. Fig. 15 shows that under very tight deadlines, a sequence-oriented algorithm does not scale up, whereas RT-SADS-CF-EDF continues to increase its deadline compliance as more processors are provided. Fig. 16 shows that RT-SADS-CF-EDF is more sensitive to the looseness of deadlines than BT2-LLP-EDF. A small value of replication rate increases transaction-to-processor anity and hence many transactions will have to be scheduled on the processors that hold the needed sub-database in their private memory to avoid communication latencies that may delay transactions processing beyond their deadline. In such a situation, a sequence-oriented algorithm like BT2-LLP-EDF would frequently face dead-end paths as it spends most of the allocated scheduling time alternating transactions consideration for scheduling, whereas an assignment-oriented algorithm like RT-SADS-CF-EDF that alternates processors consideration for assignment would quickly break such a dead-end since it considers all processors as potential candidates. Figs. 17 and 18 show the performance of the algorithms in terms of databases replication rates. As the replication rate increases, the inter-processor communication frequency decreases. BT2-LLP-EDF increases deadline hit ratios

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Fig. 17. Deadline compliance under varying degree of replication rate (P ˆ 10 and SF ˆ 1).

Fig. 18. Deadline compliance under varying degree of replication rate (P ˆ 10 and SF ˆ 2).

as the replication rate increases. This is due to the fact that, with multiple copies of sub-databases being duplicated among processorsÕ local memories, processors selection is not important. Nevertheless, RT-SADS-CF-EDF still maintains large performance di€erence over BT2-LLP-EDF. This is because load-balancing capabilities of RT-SADS-CF-EDF that helps deadline compliance, become easier to handle since there is less inter-processor communication requirements. Fig. 18 shows that the gain in performance when deadlines are looser is higher for RT-SADS. This is indicative that RT-SADS-CF-EDF is faster than BT2-LLP-EDF which search representation has a larger branching factor.

5. Conclusion We have introduced a real-time search technique to dynamically schedule real-time tasks on the procesors of a distributed system. The proposed technique automatically controls and allocates the scheduling time to minimize the scheduling overhead and to minimize deadline violation of real-time tasks, due to the scheduling overhead.

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Performance results show the e€ectiveness of our search-based representation and our selected criterion to control the scheduling time. Appendix A. Pseudo-code for RT-SADS PROCEDURE RT-SADS (start:vertex, batch: set_of_tasks); VAR queue,succ_list: queue-of-vertices; x,current_vertex,new_start: vertex; new_batch, remaining_task_set, arrived_atsk_set: set_of_tasks; BEGIN queue : ˆ start; sort (batch, heuristic); /* if there exists a heuristic*/ WHILE {NOT [leaf(head(queue))] AND [time_left_to_schedule] AND NOT [empty (queue)]} DO BEGIN current_vertex : ˆ head(queue); delete(current_vertex,queue); succ_list : ˆ successors(current_vertex); FOR each x IN succ_list DO IF not feasible(x) THEN delete (x, succ_list); sort(succ_list, cost_function); /* If there exists a cost function */ queue ˆ insert (succ_list, queue); END IF leaf(head(queue)) THEN deliver_schedule(head(queue)); ELSE IF NOT [time_left_to_schedule] THEN deliver_schedule(head(queue)); ELSE deliver_schedule(current_vertex); allocate_scheduling_time_of_next_phase; new_batch : ˆ remaining_task_set [ arrived_task_set; new_start : ˆ create_vertex(new_batch); RT-SADS (new_start) END References Hamidzadeh, B., Lilja, D.J., Atif, Y., 1995. Dynamic scheduling techniques for heterogeneous computing systems. Concurrency, Practice and Experience 7 (7), 633±652. Kumar, V., Grama, A., Gupta, A., Karypis, G., 1994. Introduction to Parallel Computing: Design and Analysis of Parallel Algorithms. Benjamin/ Cummings, Menlo Park, CA. Ma, D.Y.R., Lee, E.Y.S., Tsuchiya, M., 1982. A task allocation model for distributed computing systems. IEEE Transactions on Computers, January, 41±47. Mok, A.K., 1983. Fundamental design problems of distributed systems for hard real-time environments. Ph.D. Thesis, Laboratory for Computer Science, MIT/MIT/LCS. TR-297. Ramamritham, K., Stankovic, J.A., 1984. Dynamic task scheduling in hard real-time distributed systems. IEEE Software, July, 65±75. Schwan, K., Zhou, H., 1992., Dynamic scheduling of hard real-time tasks and real-time threads. IEEE Transactions on Software Engineering, August. Sha, L., Goodenough, J.B., Ralya, T., 1988. An analytical approach to real-time software engineering. Software Engineering Institute Draft Report. Shen, C., Ramamritham, K., Stankovic, J.A., 1993. Resource reclaiming in multiprocessor real-time systems. IEEE Transactions on Parallel and Distributed Systems 4 (4). Shen, C.C., Tsai, W.H., 1985. A graph matching approach to optimal task assignment in distributed computing systems using a minimax criterion. IEEE Transactions on Computers c-43 (3), 197±203. Sprunt, B., Sha, L., Lehoczky, J., 1989. Aperiodic task scheduling for hard real-time systems. Journal of Real-Time Systems 1, 27±60. Stankovic, J.A., Spuri, M., Natale, M.D., Buttazzo, G.C., 1995. Implications of classical scheduling results for real-time systems. IEEE Computer, 16±25. Yuan-Geng Huang, H., Kanal, L.N., Tripathi, S.K., 1989. Scheduling N jobs on one machine with insert-idle-time. In: Proceedings of the Second International Conference on Industrial and Engineering Applications of Arti®cial Intelligence and Expert Systems. IEA/AIE-89. Zhao, W., Ramamritham, K., Stankovic, J.A., 1987a. Preemptive scheduling under time and resource const raints. IEEE Transactions on Computers, August.

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Zhao, W., Ramamritham, K., Stankovic, J.A., 1987b. Scheduling tasks with resource requirements in hard real-time systems. IEEE Transactions on Software Engineering SE-12 (5). Dr. Yacine Atif graduated with a Master of Computer Science from the University of Nancy (France). He received his Ph.D. from the University of Science and Technology (Hong Kong). He is currently Assistant-Professor at the school of Electrical and Electronic Engineering at NTU University (Singapore). His current research interests are: Real-Time Systems, Parallel Processing and Distributed Computing.