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Systolic VLSI arrays for the metric approach to pattern recognition
1432
World Abstracts on Microelectronics and Reliability
delay and skew can be minimized either by a good routing strategy, or by inserting buffers in the clock tree. In this paper we develop an effective buffer insertion algorithm for high speed clock layout to minimize the clock delay and skew. Our approach is based on a new interconnection delay model, in which several practical factors such as crossunders and vias are considered in the delay calculation; furthermore, both minimum-size buffers and cascaded clock buffers are used to minimize the total clock delay. The algorithm runs in O(n) time, where n is the number of legal buffer positions in the clock tree, and obtains up to 95% clock delay reduction on practical examples.
to the array from the host computer while maximizing the silicon area using a serial approach instead of a standard parallel approach. The important design concerns of expandability and flexibility of the array architecture are discussed.
SPRAM technology cultivates characteristics useful in many fields. YUKIO SATO. JEE (Japan) 26 (August 1992). Static random access memory (SRAM) devices retain their contents as long as the power to the computer remains on. SRAMs do not require multiple refreshing every second, while DRAMs do. Once computers put a value into a static memory location, that value stays there. SRAMs feature low power consumption and high speeds. Many kinds of office automation (OA) equipment incorporate SRAMs, and make full use of SRAM characteristics. This article introduces the varieties of SRAMs, their applications and market trends, and it outlines trends in SRAM technology and in technological development.
Systolic VLSI arrays for the metric approach to pattern recognition. JAMESA. MCMAHON, MICHAELA. POTHIER and VIRENDRAC. BHAVSAR.Microelectronics Journal 23, 345 (1992). This paper presents a VLSI implementation of a parallel algorithm using a diagonal systolic array for on-line pattern recognition. It reveals a natural way of handling large data transfers
7. S E M I C O N D U C T O R
INTEGRATED
CIRCUITS, DEVICES AND MATERIALS
Promising alternative approach for high-power GaAs/Si MESFETs fabrication. R. BISARO, J. P. HIRTZ, C. ARNODO,S. DELAGE,B. GERARDand A. BOSELLA. Revue Technique Thomson-CSF 24(2), 515 (1992). (In French.) GaAs power MESFET structures have been grown by MBE on high resistivity VPE silicon epitaxially grown on low resistivity (2 mD.cm) silicon substrates. A particularity of the growth procedure is the nucleation by migration enhanced epitaxy and the annealing of the first few hundred angstr6ms-thick GaAs layer before using standard MBE growth conditions for GaAs. A completely front-size process with source interconnection via the low resistivity silicon substrate and 0.7/~m gate length has been achieved. The compatibility of GaAs and Si technologies has been demonstrated. Silicon keeps its semiinsulating properties during in situ cleaning at 1,000°C for 15 min and during GaAs MBE growth at 580°C. Ohmic source contacts have been fabricated in AuSb annealed at 360°C for 30 s which preserves the Ti-A1 Schottky contact of the GaAs MESFET gates. The use of GaAs grown at low temperature ( ~ 200°C) as a buffer layer has greatly improved the surface morphology and the electrical isolation of the MESFETs. A drain current of 220 mA (Vds = 2.5 V and Vgs = 0 V), a pinch-off voltage Vp = - 2 . 8 V, a transconductance gm(Idss) = 230 mS/mm and gm(Idss/2)= 120 mS for a gate width of 600 #m have been obtained and are equivalent to the same GaAs/GaAs MESFETs. In spite of minor technological problems encountered during reactive ion etching (RIE) of deep via-hole sources (20 tam deep), the entirely front-side process performed seems a promising alternative approach for high-power GaAs MESFET fabrication.
Silicon wafer cleaning with CF4IH z plasma and its effect on the properties of dry thermally grown oxide. R. K. CHANANA,R. DWIVEDI and S. K. SRIVASTAVA. Solid-State Electronics 35(10), 1417 (1992). In the present study, a dry cleaning method for silicon wafers has been evaluated using CF4/50% H 2 plasma followed by exposure to 02 and H 2 plasmas separately. The effect of the cleaning process and the exposure to these plasmas on the interface trap level density, fixed oxide charge density, and flat band voltage has been investigated. It has been found that the cleaning method including the 02 plasma exposure gives low values of these parameters, which are also low when compared to the values obtained for MOS devices fabricated after the conventional wet chemical cleaning process prevalent in the microelectronic industries. The proposed cleaning process eliminates the regrowth of native oxide which is unavoidable in the wet chemical cleaning process. Long--channel silicon-on-insulator MOSFET theory. A. ORTIZ-CONDE et al. Solid-State Electronics 35(9), 1291 (1992). Based on the procedure of Pierret and Shields [Solid-St. Electron. 26, 143 (1983)] for the long-channel bulk MOSFET, a new singleintegral expression is obtained to describe the current-voltage characteristics for the silicon-on-insulator (SOl) MOSFET. This expression is valid for: any degree of inversion, all back-gate bias conditions and any semiconductor film thickness. Our single-integral expression, applied to a given back-gate bias condition and using the appropriate approximations, can be simplified to the results of the previous models.
World Abstracts on Microelectronics and Reliability
delay and skew can be minimized either by a good routing strategy, or by inserting buffers in the clock tree. In this paper we develop an effective buffer insertion algorithm for high speed clock layout to minimize the clock delay and skew. Our approach is based on a new interconnection delay model, in which several practical factors such as crossunders and vias are considered in the delay calculation; furthermore, both minimum-size buffers and cascaded clock buffers are used to minimize the total clock delay. The algorithm runs in O(n) time, where n is the number of legal buffer positions in the clock tree, and obtains up to 95% clock delay reduction on practical examples.
to the array from the host computer while maximizing the silicon area using a serial approach instead of a standard parallel approach. The important design concerns of expandability and flexibility of the array architecture are discussed.
SPRAM technology cultivates characteristics useful in many fields. YUKIO SATO. JEE (Japan) 26 (August 1992). Static random access memory (SRAM) devices retain their contents as long as the power to the computer remains on. SRAMs do not require multiple refreshing every second, while DRAMs do. Once computers put a value into a static memory location, that value stays there. SRAMs feature low power consumption and high speeds. Many kinds of office automation (OA) equipment incorporate SRAMs, and make full use of SRAM characteristics. This article introduces the varieties of SRAMs, their applications and market trends, and it outlines trends in SRAM technology and in technological development.
Systolic VLSI arrays for the metric approach to pattern recognition. JAMESA. MCMAHON, MICHAELA. POTHIER and VIRENDRAC. BHAVSAR.Microelectronics Journal 23, 345 (1992). This paper presents a VLSI implementation of a parallel algorithm using a diagonal systolic array for on-line pattern recognition. It reveals a natural way of handling large data transfers
7. S E M I C O N D U C T O R
INTEGRATED
CIRCUITS, DEVICES AND MATERIALS
Promising alternative approach for high-power GaAs/Si MESFETs fabrication. R. BISARO, J. P. HIRTZ, C. ARNODO,S. DELAGE,B. GERARDand A. BOSELLA. Revue Technique Thomson-CSF 24(2), 515 (1992). (In French.) GaAs power MESFET structures have been grown by MBE on high resistivity VPE silicon epitaxially grown on low resistivity (2 mD.cm) silicon substrates. A particularity of the growth procedure is the nucleation by migration enhanced epitaxy and the annealing of the first few hundred angstr6ms-thick GaAs layer before using standard MBE growth conditions for GaAs. A completely front-size process with source interconnection via the low resistivity silicon substrate and 0.7/~m gate length has been achieved. The compatibility of GaAs and Si technologies has been demonstrated. Silicon keeps its semiinsulating properties during in situ cleaning at 1,000°C for 15 min and during GaAs MBE growth at 580°C. Ohmic source contacts have been fabricated in AuSb annealed at 360°C for 30 s which preserves the Ti-A1 Schottky contact of the GaAs MESFET gates. The use of GaAs grown at low temperature ( ~ 200°C) as a buffer layer has greatly improved the surface morphology and the electrical isolation of the MESFETs. A drain current of 220 mA (Vds = 2.5 V and Vgs = 0 V), a pinch-off voltage Vp = - 2 . 8 V, a transconductance gm(Idss) = 230 mS/mm and gm(Idss/2)= 120 mS for a gate width of 600 #m have been obtained and are equivalent to the same GaAs/GaAs MESFETs. In spite of minor technological problems encountered during reactive ion etching (RIE) of deep via-hole sources (20 tam deep), the entirely front-side process performed seems a promising alternative approach for high-power GaAs MESFET fabrication.
Silicon wafer cleaning with CF4IH z plasma and its effect on the properties of dry thermally grown oxide. R. K. CHANANA,R. DWIVEDI and S. K. SRIVASTAVA. Solid-State Electronics 35(10), 1417 (1992). In the present study, a dry cleaning method for silicon wafers has been evaluated using CF4/50% H 2 plasma followed by exposure to 02 and H 2 plasmas separately. The effect of the cleaning process and the exposure to these plasmas on the interface trap level density, fixed oxide charge density, and flat band voltage has been investigated. It has been found that the cleaning method including the 02 plasma exposure gives low values of these parameters, which are also low when compared to the values obtained for MOS devices fabricated after the conventional wet chemical cleaning process prevalent in the microelectronic industries. The proposed cleaning process eliminates the regrowth of native oxide which is unavoidable in the wet chemical cleaning process. Long--channel silicon-on-insulator MOSFET theory. A. ORTIZ-CONDE et al. Solid-State Electronics 35(9), 1291 (1992). Based on the procedure of Pierret and Shields [Solid-St. Electron. 26, 143 (1983)] for the long-channel bulk MOSFET, a new singleintegral expression is obtained to describe the current-voltage characteristics for the silicon-on-insulator (SOl) MOSFET. This expression is valid for: any degree of inversion, all back-gate bias conditions and any semiconductor film thickness. Our single-integral expression, applied to a given back-gate bias condition and using the appropriate approximations, can be simplified to the results of the previous models.