Task Allocation in a Microprocessor-Based Distributed CNC Configuration

C o pyri g ht c IFAC Compone nts and Instrum ents fo r Distri buted Contro l Systems. Paris . Fran ce 1982

TASK ALLOCATION IN A MICROPROCESSORBASED DISTRIBUTED CNC CONFIGURATION Th. Borangiu and R. Dobrescu Department of Control and Computers, Polytechnz'cal instz'tut e of Bucharest , Bu ch arest, Romanz'a

Abstract. The paper approaches an advanced concept in the Computerized Numerical Control (CNC) of machine-tools, which consists of dynamic parallel allocation between a number of processors which form a distributed control configuration. The proposed structure offers the following basic functions: linear tridimensional and circular bidimensional contouring by means of high efficiency interpolation algorithms, path correction for different tools, optimization of the cutting process according to overall criteria, such as cutting productivity or cost, tool life, a.o., versatile communication with the operator, automatic part program acquisition and editing, and programmable control of switching operations. The automation of the part production is achieved by a modular multimicrocomputer system, containing a number of processors, which comunicate both OD an universal parallel bus (MULTIBUS) and on dedicated, high speed direct busses, thus improving the overall process data transfer and the d8.ta exchange inside the control system. Keywords. Multiprocessing systems; microprocessors; numerical control; communication interface; digital circuits. INTRODUCTION

sity storage ROM and RAM components, at a low power consumption, which provides a high degree of autonomy of the control system, despite the relative frequent fall periods of peripheral units, such as the paper tape reader.

Microcomputer-based techniques offer the possibility to build up numerical control structures for machine-tools with implementation of the basic control functions at a low cost. The research carried out in this field was directed mainly to ensure three objectives: - the increase of logiC and arithmetic computing capability of the central processing unit of the control system, in order to provide high efficient path generation and path correction sections, as well as the extension of process control strategies, such as the real time optimization of the cutting procesS"; - the extension of typical input/output interface functions by integration of analogue and numeric data processing and special command emission, dedicated to specific machine actuators ( ego d.c. motors, stepper motors ), in industrial LSI components or microprocessor-based modular programs; - the increase of part program storage capacity, by utilization of high den83

At the same time, it was generally considered that a single microcomputer-based processing unit does not ensure the difficult tehnical requirements imposed by the real time numerical control: contouring accuracy up to l}lm for displacements of tenth of meters, feedrates up to 15 m/ min and a sophisticated dialogue between the operator and the control equipment. It becomes obvious that an optimal control configuration for machinetools consists of the distribution of the basic function between a number of processors (Binder, 19t1O), which operate in parallel and communicate data and commands according to the following tasks: path generation, which involves geometric data processing, feed and speed automation according to optimality criteria, programmable control of sequential cycles and data entry and display at the

84

Th . Borangiu a nd R. Dobresc u

operator's console. Thus, a decomposition of the process control problem into position loop and feedrate loop is obtained by means of dynamic activation of modularesoftware packages associated to distinct hardware units, running a s yn chronousl y . SYS TEM ARCHITECTURE The distributed CNC system configur ation is presented in Fig. I and consists of the following processors: - the Central Control Processor (CCP), which represents the coordination processor, is build around an 8 bit microprocessor of the Intel 8080/85 type and performs automatic part program acquisition from a cassette unit and the operator console, data conversion, program editing, and supplies the necessary data and commands for automatic execution of the distributed program running, according to the operating modes of the whole structure ;

- the Programmable Controller ( PC ), with one bit lengt h d ata processing, interfaces the CNC system with the conventional driving section of the machine tool and performs sequen t ial control programs; - the Communication Processor (C P ) i s an intelligent transmitter- receiver which conects the CNC multiproces s or system to a DNC minic omputer f or DMA part program acquisition, part production supervising and periodic transmission of economic information (eg. number of pa rts, tool we ar , time required for part execution and f or tool changes, power consumption, etc.). Thus, a hiera rchic cont rol configuration of multiple CNC's (u n to twelve) is obtained. .

The physical construction of the CNC sys tem is based on the impl ement ation of the above mentioned processors on separat e boards; thus, each processing unit becomes a single bo ard eompute:r, with typic al h ard ~:are ch a r a cteristics. The processors exchange data and commands over a c ommon bus , the access being granted on a priority - the microprogrammed Path Generation based scheme. Anyone of the s ys tem's Processor (PGP) designed with the Inprocessors are potential masters, betel 3000 LSI family, operates with 32 bit data format and performs high speed ing able to drive the mul t ipro cess or bus, except for t he PC , which al way s numeric interpolation for pl ane and space displacement of the working pOint, occupies a slave position. path correction for different types of tools and workpiece compensations and The function distribution among seveserial distribution of the command ral processors which operate in parapulses for the feed actuators; llel allows hardware reduction of their organization, as well as the utilization of the 8 bit microproces- the Adaptive Control Processor (ACP) represents a 8080/85 high speed feedsors of the Intel 8080/ 85 type. This is an important facility in t he derate con~oller, with arithmetic hardware extension, which receives the in- sign of the control configuration, from the point of view of both s oftterpolation pulses and the feedback ware development and of standa rd mUlposition of one axis, strobes in the position error and according to a con- tiprocessor bus utilization, such a s the MULTIBU S interfacing . As it will trol algorithm (eg. classical PI, PID be mentioned, special attention wa s or state estimation) outputs the fipaid to th e optimization of dat a ring pulses applied to the SCR bridge for armature voltage regulation of d.c. transfer speed, and al s o to include a microprorammed, double word l e n ~th motors. In addition, the ACP procesprocessor the PGP ) ~nth re s pect sor inputs data which reflects the mato the 16-bit data lines of the mulchining intensity: Vibration levels, tiprocessor bus. This is necessary torque, deflection and speed of the main spindle, feedrate, electric power because on one side d a t a lines su ch as the serial interpolation commands of the main drive and computes the opout putted by the PGP sho uld reach timal values for the feedrate (wOPT ) the feedrate controller ( ACP ) withand spindle speed (sOPT). These vaout delay in order to ensure the machining accuracy, and on the other lues are obtained by means of a disside high speed contouring wit h on crete decisional strategy which extreline path correction over a wide dismizes a nonlinear overall performance placement requires dat a form ats greaindex, subject to nonlinear constrater than 24 bits. A microprogr ammed ints, such as machining productivity computer, such as t h e Intel 3000 ofor cost. The optimal values of the fers the possibility to build up infeedrate will control the interpolaterpolation and correction microprotion cycle inside the PGP, while the grams which minimize the to tal amount optimal value o f the speed is output of memory, and to simplify the basic directly to the main drive interface arithmetic routines by parallel pro(Borangiu and Dobrescu, 1980); cessing in integ er or flo ating point

Tas k All oca ti o n i n a Mi c r o pr ocesso r- Ba s e d Distributed C~C Configu r a t ion

data reprezentation, at a superfast microinstruction cycle of typical 175 nanoseconds (Rauch and Worn, 1978). The difficulties generated by the data format incompatibility between the 8 and 32 bit processors have been overcomed by making use of the 16 bit data capacity transfer provided by the selected system bus.

85

rate loops, by making use of a non bus vectored interrupt logic; - the partition of resources. The SEC s which form the CNC system share common resource s which are common on the Multibus.

The 8 bit to 3 2 bit data format adaptation is accomplished in this application by means of 16 bit data transA final point of this discussion refers fers, when one of the two linked proto the particular interfacing between cessors is the PGP. This re q uires one byte d a ta buffering on the 8 bit the CCP and the PC. Although a double N'aster, which uses an 8 bit 8212 I/O access RAM memory of 1 bit word length port in the output mode, in order to provides a versatile data and command perform a sixteen bit d 8ta emission: buffering, the direct I/O connection OUT X between the two processors seems to be MOV M,B more efficient for the specific asynchronous transfer which include maximum where X represents the internal address of the 821 2 port on the Master 32 data lines. As for the control of the operator's console and the magnetic which drives the bus, and M is the secassette unit, the interfacing by means lected external RAM zone on the Intel 3000 board, which represents the data of dedicated ports such as the 8279 Programmable Keyboard/Display Interface destination. and the 8 251 Programmable Communication At the same time, the 3 2 bit Master Interface involves typiCal I/O addresPGP performs sixteen bit input/output sing techniques combined ~~th the CCP operations by using data byte swapping. interrupt system. In order to access an external RAM placed on an 8 bit processor board, Experimental results carried on the SMP 1 multiprocessor structure develop- the 3000 Master uses 16 bit pattern ped at the Control and Computer Depart- ex e cuted as two single byte transfers (Sabatier, 1981). ment of the Poly technical Institute of Bucharest were entirely satisfactory The Multibus system accomodates the from both the point of view of compupotential bus masters CCP, PGP, the ting capacity and of overall communithree ACPs and CP on the same system, cation speed. each one taking control of the bus when it needs to execute data trans COMMUNICATION SYSTEM fers. A fixed parallel priority technique is accomplished by using an external priority resolution circuit The CNC multiprocessor system makes consisting of a priority encoder conuse of Intel's Multibus™ for data and trolled by the EREQ lines, and a pricommand transfer. For this particular ority decoder which produces the BPRN application, both the connection of lines. The PGP, CCP, ACP and CP are the 8 bit microprocessor-based single assigned adjacent priority levels, board computer CCP, ACP and CP, and of with the highest level for PGP. Fig. the 32 bit PGP micro programmed computer 2 presents the standard control cirare possible. Three basiC functions cuit placed on each SBC bus master, of the Multibus structure determined which provides the necessary bus prithe choice of this product for multiority resolution lines. processor interfacing: The common resources of the CNC struc- the modular int erconnection and comture are represented by RAM zones munication between a number of single placed on each processor board, with board computers of different types: double access from the own microprowhen the transfer involves two 8 bit cessor and from the Multibus. In the processors, t h e bus operates in the present application each of the proone byte mode, and when the data transcessors contains 4K bytes of double fer implies the 32 bit PGP, the sixaccess memory, except for the PGP, teen bit mode is used; which has a special double access 256 words x 16 bits RAM zone. - the connection of several processors operating in parallel. The Multibus The 8 bit master interface for the increases the efficiency of the CNC internal common memory is given in system data processing, by minimizing Fig. 3. The scheme makes use of a set the bus conflicts and by synchronizing of 8216 bus drivers for internal adthe interpolation routines associated dreSSing and of a set of 8226 drivers to the displacement loops with the afor internal addressing which are acdaptive control routines of the feedtivated either for external access

86

Th. Borang iu and R. Dobr e s cu

from the Multibus, when another master performs data read or write operations with the common memory, or when the internal master, after being granted the bus, accomplishes a data exchange with an external common memory. In order to acquire for one or more transfers to or from a memory connected to the Multibus, a master activates its BREQ/ line. The priority is established by the parallel resolution circuit which activates the master of highest priority.

the external common memory, together wi th the READY/ and XACK/ signals are produced. The three access lines are synchronized with the memory read or write lines, depending upon the data transfer direction, and fed to a combinatorial logiC for chip select, data flow direction and write ena.ble controls of the interface, as shown in Fig. 4.

The bus exchange takes place after the BUSY/ line is set inactive ( a previous command is finished or there was no master holding the bus ). This allows the actual bus master to take control by activating BUSY/ with the next trailing edge of BCLK/ and by enabling its own data and address drivers 8216, 8226 D,A. A data exchange with a common memory placed on an 8 bit processor is done on the DAT~/ - DAT77 lines, while a data transfer to the PGP common memory requires an additional instruction: strobe into the own 8212 output port the content of the accumulator, which represents the higher byte of the 16 bi t transferred datCl. ( and appears on DAT8/ - DATF/ ). At the same time an external access request (ER) line activates the 8226 common memory data and address drivers of the destination board, cheking for a possible dialogue between the internal processor with its own common memory. If this is the situation, the bus master waits for the internal processor to accomplish its transfer. Thus, interlaced internal and external accesses to a common memory are possible, after every word transfer. However, the internal master may prevent any external access to its common memory from the Multibus, by activating its BUS LOCK! line. Also, there are no interruptions in accessing its dedicated ROM or RAM memories, when another bUB master accesses the common memory placed on its board ( Barthmaier, 1979 ).

A special interfacing technique has been developped for the PGP, due to the fact that severe restrictions are imposed on its real time operating mode. The basic functions of this processor are the space linear and plane circular interpolation which use the corrected coordinates of the initial and final points of the current segment; these new values are computed according to some well defined tool compensation rules.

The control circuit of an 8 bit master interface decodes the internal access request IR (internal master to its own common memory), communication request CR (internal master to an external common memory) and external request ER (external bus master to its own common memory) from the upper internal or Multibus address lines, and applies these three commands to a seqential state machine which receives also the BUS GRANT ED/ and BUS LOCK! internal signals and the system synchronization signal CCLK/. As a result, internal access (lA) or external access (EA) to the own common memory or communication access (CA) to

PATH GENERATION PROC ESSOR INTERFACE

In order to ensure the continuous displacement of the working point the interlaced access of the PGP and of some other bus masters at the common memory placed on the PGP board holds no more; in addition, new geometric data from the part program must be available without any delay when the current segment processing is finished. For these reasons, the common memory on the PGP board appears as three 256 word x 16 bit RAM zones, with independent address and data lines, which store the geometric and speed information associated to the phrases k, k + 1, and k + 2 of the part program. The data written into the k zone represents the current interpolation data basis; tool compensation and internal or external segment connection are processed for the next segment (k + 1 phrase), and the data stored in the k + 2 zone provides the continuity of the operation. The master PGP uses the data stored in the first two RAM zones, while external access from a bus master (eg. the CCP or ACP) is given for the third RAM zone. Once the PGP has accomplished the current segment interpolation, it releases the access to the interpolation zone and accesses the compensation zone, which becomes the interpolation zone and the continuity zone which now allows for compensation computing. By means of an interrupt Signal, the PGP determines the part program decoder (the CCP) to require the system bus and to write new data into the available RAM zone. Thus, for a bus master the common memory on the PGP board has the same address, but in fact a circular acce~ c~cle is generated by the PGP which

Ta sk All o cati on in a Microprocessor-Based Distribut ed CNC Config ur a ti o n

demultiplexes the Multibus data and address lines by means of a three bit ring shifting. Fig. 5 presents the 32 bit PGP master interface. In order to maintain compatibility with the 8 bit CNC masters a byte swapping bus is included in the PGP interface. For data exchange, there are three 8287 buffers: the lower byte buffer (Cl) accesses DAT~/- DAT7/, the upper byte buffer (C3) accesses DAT8/ - DATF/, and the swap byte buffer (C2) accesses the DAT~/ - DAT7/ lines and transfers the data to/from the on-board data bus lines D8 - DF. An external access from a bus master to the common memory {one of the MC 1, MC 2 and MC 3 RAM zones) involves the 8287 Cl and C3 buffers, while a communication access from the PGP master to an 8 bit common memory uses _ 8287 Cl buffer for low byte transfer and the swap buffer for high byte transfer on the same low data lines of the Multibus. The internal 16 bit data source for communication access may be either the upper group of 300~ CPEs, or the lower group; when the master is the PGP, it uses for data link the bidirectional 82l6 Cl buffer and, if necessary, the 8216 1 and 8216 D buffers which operate on separate CPEs input - output lines. The control circuit (Fig. 5b) contains a three bit serial shift register, which is controlled at power start by the CCP, and in normal operating mode by the PGP, which simultaneously signals to the CCP that the current inte~ polation has been finished, and new data is necessary. The I/O data lines of the MC 1, 2, 3 common memories are obtained by wiring together the B outputs of the 8286 El ,E2,E3 drivers (on the Multibus side) and of the 8286 11 ,12,13 drivers (on the 3000 processor side). Two similar groups of 8286 drivers (E4,E5, E6 and 14,15,16) are used for 256 location memory addressing. One important problem is the correlation between the displacement loop implemented by the master PGP and the feedrate loop implemented by the master ACP. Given a programmed feedrate value, F [mm/min] , if the interpolation routine is based on continuous test of the implicit x - y path equation, the internal computing frequency f of the 3000 master is given c (ego for linear interpolation) as:

fc

=

IXf=1

Y

+ \YFI

X~ +

yfl.

. f·

100

0

[ii-j

87

where the final coordinates of an interpolated segment, XF , Y are exF pressed in

rm.

The PGP uses a programmable interval timer (8253) operating in mode 2 loaded with a content N which gi~es the real interpolation cycle 7:, expressed as follows: 1;; = N'

= -~- • c

fB '

where fB = 2 MHz is the basic clock frequency of the timer. Once started the 8253 output is connected to an ' interrupt request line of the 3214 programmable interrupt controller, which synchronizes the activation of the interpolation routine; after one computing cycle, one displacement pulse either on the X or Y axis is transferred to the associated ACP master (Fig. 6a). It is to be mentioned that every 100 msec, the PGP checks for a manual mo~ dification of the displacement feed, from the feedrate override switch on the operator's console. If a change was initiated from 1;1 to 1:2 , the PGP modifies the N{~) value in A~ steps; a software implemented routine performs feedrate acceleration and deceleration in order to reach the final point of a current segment with a fixed value, ~FIN' which allows a smooth connection of two successive segments (Fig. 6b) • The initial value of ~ is computed by the CCP master, from the part program and transferred into the common memory on the PGP board which allows an external access. "'/hen the adaptive control of the feedrate is imposed, in noncorrected interpolation or paraxial cutting operations, the ACP master provides the feedrate data basis (~OPT) for the PGP displacement loop. CONCLUSIONS The multiprocessor CNC configuration previously described improves the real time control performances from both the point of view of system decoupling into the displacement loop and the speed loop, which allows for parallel processing of high efficient contouring and adaptive control routines, and from the point of view of the utilization of Intel standard 8 bit and microprogrammed processors. Special techniques have been developped in order to improve the overall data transfer speed, independent of

Th. Bo rangiu a nd R. Dobre s c u

88

the word length of the system's master processors; at the same time, the presence of the CP master allows a simple integration of the described configuration in a hierarchical control of part fabrication for a group of up to twelve machine tools. REFERENCES Barthmaier, J. (1979). Intel MULTIBUS™ Interfacing. Application Note, AP-28A,Santa Clara, 1-16.

Binder, D. (1980~. Modulares Mehrprozessor-Steuer-System fUr Arbeitsmaschinen. Wt. Z. Ind. Fertig., 8, 525-529. Borangiu, Th., and R. Dobrescu (1980). Biprocessor Configuration with Alternating Hierarchy for High Speed Process Control. In R. Isermann (Ed1, Digital Computer Applications to Process Control, Pergamon Press, 443-450. Rauch, P., and H. W~rn (1978). Busstrukturiertes MehrprozessorSteuerungsystem. Wt. Z. Ind. Fer tig., 6, 335-342. Sabat1er, A7 (1981). L·utilization du Multibus. Recuei1 des Notes d'Application, Syst~mes iSBa/iCS, 7-13.

cp

Acp AdQf"ive C<:>ntrol

Prcx::e .....or Fi ~ .

-.

Distributed CNC System Configuration

\~tT

~'T

c

'WIT

c.

C.~I

1110,.; t.:y

~ oci

ry

Encoder Jlecoder

Fig. 2.

Control circuit bus priority

89

Task Allocation ~n a Microprocessor-Based Distributed C~C Configuration

A'C>R.01 - At>RFI

'"

~

CA.!

I

EAI

S205

, 4 Control r' Circuit

,--~

CS/

c..... It>e. ?>x

!)\ ~

MC

A

RAM

'a22(,p\

I)IEN/

C!.I

llO f---

~l>I£M/

Tc.t./

~WEI

'T"

f?r 1 &20'5

CS!

~"'tlI!> I-

824"

t>I

I""

t

C'>/

.I

~T&

1..MEMA.I

r--- .1>1 2",

924(,) llo

lE

~~

Tl lw'OIM,e.

6R.1'.>lT

--

CS!

i

])a.

..

821"

CS,

Del> -PF ICe. MEMW/, •••

I>I

~

8 - Bit Master Interface

!RI

lA! =&~U~~~~~~'~/______~~P____________________~CA~!

Fig. 4.

Control circuit of 8 - Bit Master Interface a) Block Diagram;· b) ASM and Ready Logic

(Fig. 5 - see next page )

Fig. 6.

f- O\Jrx

:DIElIl

Arl-AF

Fig. 3.

8212. ~MDJ)!;,

i MR.DC/· MEMW!

----

Ctol

~

lxl ~A

~li\

~1EN1

EAI MEM.,/

CAI

~

'

f---- DI822bJ)

WE/

'A'~ AM~!

1>lEN/

it

SCe:. (MWTC /, •••

2", ! l e -

\ 10 I-----

4K"Sb

1

!:>AT~! -l>A"T F /

Computing timing and feedrate control

Th . Bo ra ng iu and R. Dob r escu

90

)AT~/­ -D~7

'/

..

oE

'--B

eQ87

,-1.

DATS(-

DATF/

A 2)( B

B

A

~e~

B287

. JT

.,

,

~J"

DE

1Iu.

EA/

CM1

(~/

IM

Ar;yg,r/>/-

~

l&.H

I/O

Vc.c

Mwn:..

oe

T"

c.~

~Efl

A

f ..el cM2 11 0

CS/

A

Y

r---_ EAJ

--- B A 1--- - ----~---t-----+-----+----I}B - A~F-/ 2"::::--t

..

'02S~

T

t-----

B

AI

1

.. T"

01:

T

oE

CA/ EtJ/

~

T

TcsE:2.

OE

r-~~~~=3~==~==~~/~~-~~~ ... c1~

A'1R.(/_ At;Jfl.f-1 c.c;\2.

Fi g . 5 .

1>1 I--

Q2.I"c.:

oE

cl J~~

4x

32-Bit Master Interface

a ) Basic Configuration

b) Control Circuit

,