TCAD performance analysis of high-K dielectrics for gate all around InAs nanowire transistor considering scaling of gate dielectric thickness

Microelectronic Engineering 160 (2016) 22–26

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TCAD performance analysis of high-K dielectrics for gate all around InAs nanowire transistor considering scaling of gate dielectric thickness Richa Gupta, Rakesh Vaid ⁎ Department of Physics and Electronics, University of Jammu, Jammu 180006, J & K, India

a r t i c l e

i n f o

Article history: Received 26 January 2016 Received in revised form 18 February 2016 Accepted 27 February 2016 Available online 02 March 2016 Keywords: Gate All Around (GAA) Lanthanum oxide (La2O3) Drain Induced Barrier Lowering (DIBL) Effective oxide thickness (EOT) Nanowire FET (NWFET) Subthreshold slope (SS)

a b s t r a c t Gate dielectric thickness is an important parameter in designing nanowire FETs. In this letter, the performance potential of SiO2, ZrO2, HfO2 and La2O3 gate dielectrics for InAs based gate all-around nanowire transistor has been reported based on TCAD analysis. The results demonstrate that La2O3 can replace SiO2, ZrO2, HfO2 owing to its high current driving capability (44% increase), high mobility, low leakage current, high transconductance, high switching speed (~25 μs), excellent charge density, better sub-threshold slope (~60 mV/decade), reduced DIBL (~10.4%) and also the effective oxide thickness of La2O3 is found to be 0.13 nm. © 2016 Elsevier B.V. All rights reserved.

1. Introduction As the thickness of gate dielectric keeps on shrinking, it is facing its physical limitations from the view point of leakage currents and reliability requirements because of direct tunneling [1]. Therefore, as a replacement of SiO2, high-k dielectric materials have attracted extensive interest in the last decade due to their great potential for maintaining further down-scaling in EOT (equivalent oxide thickness) with a physically thicker film and a low dielectric leakage current. Theoretically, the combination of high-K gate dielectrics and III-V compound semiconductors seems to be ideal in pursuing everlasting goals namely high device performance and low power dissipation in the future nano-devices. The primary goal of this paper is to study the performance of InAs based GAA nanowire transistor with different high-k materials. Hafnium oxide (HfO2) gate dielectric material can provide good thermal stability, high re-crystallization temperature and better interface qualities in comparison to other gate insulator materials; also the effective oxide thickness of HfO2 is found to be 0.4 nm [2]. In addition, Hafnium oxide based materials such as, HfSiXOY, HfOXNY, HfSiXOYNZ (KHfO2 ~25) have emerged as leading candidates to replace SiO2 gate insulators in advanced CMOS applications [3]. However, amorphous HfO2 suffers from the problem of crystallization at relatively low temperatures (~500 °C), which not only increase the leakage current, but also deteriorates the interface quality of high-k oxide and Si substrate [4]. Recently, a lot of investigations on the material properties and applications of ⁎ Corresponding author. E-mail addresses: [email protected] (R. Gupta), [email protected] (R. Vaid).

http://dx.doi.org/10.1016/j.mee.2016.02.057 0167-9317/© 2016 Elsevier B.V. All rights reserved.

high-k dielectrics have been conducted which includes aluminum oxide Al2O3 [5,6], lanthanum oxide La2O3 [7], yttrium oxide Y2O3 [8], tantalum pentoxide Ta2O5 [9], titanium dioxide TiO2 [9], zirconium dioxide ZrO2 [10], rare-earth scandates DyScO3 [11], and SmScO3 [12]. La2O3 has excellent properties such as high dielectric constant (KLa2O3 = 30), large bandgap (5.8–6.55 eV) and large conduction band offset with Si (N 2 eV) [13]. Experimental results clearly illustrate the advantages of La2O3 over HfO2 MOSFET. Especially, silicate reaction observed at La2O3/Si interface has been found to suppress the formation of SiO2 layer to realize direct contact, which is useful for further scaling in equivalent oxide thickness. La2O3 also shows relatively high interfacial state density due to lack of interfacial layer but its effective mobility is much greater in comparison to HfO2 MOSFET resulting in smaller EOT [14]. The article is planned in the following manner. In Sections 2 and 3, device structure and analytical expressions have been given. Systematic analysis of the electrical properties and the calculations of various performance parameters of the device are being made in Section 4. Finally, the work is summarized in Section 5. 2. Device structure The device structure of the GAA Indium Arsenide (InAs) nanowire transistor studied in this paper has been represented by Fig. 1 and the parameters used for device simulation are shown in Table 1. In this multigate nanowire transistor, the channel is surrounded by several gates on multiple surfaces, allowing more effective suppression of “off-state” leakage current and also allows enhanced current per area

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Fig. 1. Schematics of gate all around nanowire transistor.

in the “on-state”. This advantage directly leads to lower power consumption and enhanced device performance [15]. In this structure, the nanowire is used as a channel, which is surrounded by an oxide layer and is finally surrounded by a metal contact which serves as a gate terminal. Here, the current flows through the nanowire or is pinched off under the control of the voltage on the gate-electrode, which surrounds the nanowire. 3. Analytical expressions

current equation for gate all around nanowire transistor can be calculated from the Landauer–Bvttiker formula as: Id¼2q h

XZ

dET m ðEÞ ðfs ðEÞ–fD ðEÞÞ

ð4Þ

m

The term Tm(E) in the above equation represents the transmission probability of a particular sub-band, ‘m’ represents the sub-band and ‘E’ represents the energy. The sub-band is given by the formula:

The GAA InAs nanowire transistor in the ballistic transport regime has been simulated based on the effective mass theory using the selfconsistent Poisson-NEGF calculations performed through Multigate Nanowire FET TCAD simulator [16]. The effective mass Hamiltonian of the device that we have used in our simulation is given by:

where, Gm is the one-dimensional Green's function for a sub-band ‘m’ and is given by:

H 3D Ψðx; y; zÞ ¼ E Ψðx; y; zÞ

h i−1 X X ½Gm ¼ E−H 1D m − s; m− D; m

ð1Þ

For 3-D Hamiltonian of a device, the Newton dynamics is usually replaced by the quantum dynamics while quantum transport is taken into consideration. Here, ‘H′ describes the quantum state of the physical system (here the channel of MOSFET) and its variation with time. Here, H3D is given by: H3D


 ℏ ∂ ℏ ∂ 1 ∂ ℏ2 ∂ 1 ∂ − þ Vðx; y; zÞ ð2Þ ¼− −   2 2mx ∂x 2 ∂y m y ∂y 2 ∂z m z ∂z 2

2

2




where, mx*, my*, mz* are the effective masses of electrons in the x, y, z directions, respectively and V(x, y, z) represents the conduction bandedge profile, given by: Vðx; y; zÞ ¼

E0c ðy; zÞ−ϕðX; Y; ZÞ

ð3Þ

where, E0c (y, z) is half of the band gap of silicon or oxide depending upon whether the location (y, z) lies in the silicon region or the oxide region and Φ (x, y, z) represents the vacuum level potential. The drain Table 1 Parameters used in TCAD simulation. S. No.

Parameters

Symbol

Value (nm)

1. 2. 3. 4. 5. 6. 7.

Source/drain length Gate length Oxide width Channel length Buried oxide thickness Substrate body width Substrate thickness

Lsd Lg Wox Lc Tbox WInAs TInAs

10 10 1 10 5 5 25

  T m ðEÞ ¼ T r Гs;m Gm ГD;m Gþ m

ð5Þ

ð6Þ

where, 2

H1D m ¼ −

2

ħ d þ Em ðxÞ 2m x dx2

ð7Þ

Here, Em are the Eigen value energies for the ‘m’ sub-bands separately and ∑s,m and ∑D,m are the source and drain self energies of subband. Гs;m ¼ i ГD;m ¼ i



þ

∑s; m−∑s; m



X Xþ  D; m− D;m

ð8Þ ð9Þ

The Fermi distribution functions at the source and drain ends are given by: f SðDÞ ðEÞ ¼

1 1þ

eE−E F

SðDÞ

.

ð10Þ

KB ðTÞ

where, E F SðDÞ are the Fermi energies at the source and drain regions respectively. The 3-D charge density can be calculated from the equation given by: n3D ðx; y; zÞ ¼

X

nm 1D ðxÞ jψm ðy; z; xÞj2

ð11Þ

m

where, the summation is over the number of sub-bands that are occupied in the 2D quantum well at each of ‘X’. This three dimensional

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The drain current of much higher magnitude is obtained by using La2O3 as gate dielectric material because of its relatively large dielectric constant and smaller effective mass in comparison to SiO 2 , ZrO2 and HfO2 resulting in improved performance of the nanowire transistor. 4.2. Mid-channel charge density and energy band profile

Fig. 2. Drain current versus gate voltage for different dielectric materials.

quantum charge density is used to calculate the potential Ø (x, y, z) at each point by making use of Poisson's equation. 4. Results and discussion In this section, various material properties of SiO2, ZrO2, HfO2 and La2O3 dielectrics for GAA InAs nanowire transistor have been critically investigated. 4.1. Ids-Vgs characteristics Fig. 2 shows the variation of drain current versus gate voltage for different dielectric materials in linear scale at constant Vds = 0.5 V and Tox = 1 nm. From the plot, one aspect can be clearly stated that as the dielectric constant increases, the drain current shows an improvement.

Fig. 3(a) shows the variation of the charge density along the length of the channel for the different gate dielectric materials. From the graph, it is quite evident that SiO2 has the lowest charge density in comparison to high-k materials. However, La2O3 seems to have an excellent charge density profile relative to other gate dielectric materials for exactly the same dimensions. It further confirms that the maximum conduction in the device occurs for La2O3 gate dielectric. Fig. 3(b) shows the variation of energy with respect to the position along the length of the channel at oxide thickness 1 nm. From the graph, it can be seen that the best conduction for SiO2 occurs at higher energy values (~−1.7 eV) whereas La2O3 requires quite lower energy for conduction and shows excellent conduction at nearly − 2.1 eV, which is nearly 0.4 eV smaller. This clearly shows the performance potential of La2O3 gate dielectric for making gate all-around InAs nanowire transistors. 4.3. Variation of Ion, Ioff, gm and Ion/Ioff Fig. 4(a) shows the variation of on-current with respect to various gate insulator materials at constant oxide thickness of 1 nm. From this graph, it is apparent that the on-current shows significant improvement with the increase in dielectric constant. Qualitatively, it can be stated that the increase in dielectric constant results in enhanced gate oxide capacitance and hence better gate control. The maximum drive current for both SiO 2 and La 2O 3 occurs at 1 nm. SiO2 gives Ion of 139 μA while La 2 O 3 gives I on of 200 μA at 1 nm oxide thickness; thereby, giving nearly 44% more drive current for La2O3 in comparison to SiO2. Fig. 4(b) shows the variation of leakage current with respect to different gate insulator materials and exhibits an effective suppression for all the gate dielectric materials. OFF currents of magnitude nearly 102 times smaller were observed by using La2O3 in comparison to SiO2. This is because a thin insulator

Fig. 3. (a) Mid-channel charge density profile (b) Mid-channel conduction band profile.

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Fig. 4. Variation of (a) Ion (b) Ioff (c) gm (d) Ion/Ioff versus various gate dielectric materials at Tox=1 nm.

can cause large leakage current density because of the occurrence of direct tunneling. La2O3 has shown a very strong insulating character with InAs as a substrate. Fig. 4(c) shows the variation of transconductance with SiO2, ZrO2, HfO2 and La2O3 as gate dielectric materials at Vds = 1 V. It is always desired to have the higher values of transconductance which directly results in higher gain. Actually, the high value of transconductance means that the device has more effective control over the gate. The transconductance value for La 2O 3 is 44% higher than SiO2 , which implies that La 2O 3 has more control on gate at 1 nm oxide thickness in comparison to SiO2. From the Fig. 4(d), it can be observed that La2O3 shows higher ON/ OFF ratios by a factor of 102 as compared to the SiO2 at an oxide thickness of 1 nm. The primary reason for higher ON/OFF ratios for rareearth La2O3 is due the better sub-threshold characteristics, namely lower leakage currents when compared to the SiO2.

high-k layer can be expressed as: EOT ¼ єSiO2 =єhigh−k : T high−k

ð12Þ

where, єSiO2 and єhigh − k are the dielectric constants of SiO2 and high-k dielectrics. Thigh-k is the physical thickness of high-k dielectric gate oxide. 4.6. Drain Induced Barrier Lowering (DIBL) The percentage reduction of DIBL for different dielectrics can be depicted in graphical way as shown by Fig. 7. In logarithmic plot, the voltage difference between two I-V curves at a single value of drain current gives us the DIBL below threshold voltage. It has been observed that SiO2 exhibits the lowest capability for the suppression of DIBL. For

4.4. Sub-threshold slope (SS) SS is basically a short channel effect associated with the transistor's turn-off characteristics and is defined as the change in gate voltage required to produce a decade change in drain current. The SS should be as small as possible to quickly turn on or off the transistor. Fig. 5 shows the variation of sub-threshold slope for various gate dielectric materials at 1 nm oxide thickness. A sub-threshold slope of 180 mV/decade at an oxide thickness of 1 nm was observed for SiO2 while La2O3 had a sub-threshold slope of 60 mV/decade, which is nearly the ideal value for the sub-threshold slope.

4.5. Effective oxide thickness (EOT) Fig. 6 shows the variation of EOT for ZrO2, HfO2 and La2O3 gate insulator materials at dielectric thickness of 1 nm. From the graph, it is quite obvious that EOT values for ZrO2 and HfO2 are nearly the same (~ 0.156 nm). However, La2O3 has shown the lowest value of EOT (~ 0.13 nm). The relationship between EOT and the thickness of a

Fig. 5. Variation of subthreshold slope for different dielectric materials at 1 nm oxide thickness.

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the gate over the channel, thereby, making La2O3 gate insulator as the outstanding candidate for amplification purpose. The EOT of La2O3 is 0.13 nm against 1.2 nm for SiO2 to produce exactly the same effect. Acknowledgment Both the authors (Richa Gupta and Rakesh Vaid) acknowledge the University Grants Commission (UGC) for providing financial assistance under junior research fellowship (JRF) and major research project (MRP-MAJOR-ELEC-2013-22797) under the 12th plan period respectively. References

Fig. 6. Variation of effective oxide thickness with respect to different gate dielectric materials at TOX = 1 nm.

high-K dielectrics namely ZrO2, HfO2 and La2O3, improved DIBL results have been observed. The effective suppression of DIBL by using high-K dielectric materials can be given [17] as:

DIBL ¼ 0:80

ℇ Si ℇ ox

1þ

X j2 L2 el

!

T ox T dep Lel 2

V ds

ð13Þ

where ℇSi the permittivity of silicon is, ℇox is the permittivity of oxide, Xj is the junction depth, Lel is the gate length, Tox is the oxide thickness, Tdep is the depletion layer thickness, Vds is the source-drain voltage. 5. Conclusions Oxide thickness scaling limits of ZrO2, HfO2 and La2O3 for Gate all around InAs nanowire transistor have been investigated using 3-D numerical simulations. La2O3 as gate dielectric can enhance the device performance as it provides the highest mobility, lowest leakage, highest switching speed, excellent charge density and excellent capability of suppressing the SCEs. The direct relationship between high-K dielectric value and oxide capacitance results in enhanced electrostatic control of

Fig. 7. Percentage reduction of DIBL for different gate dielectric materials at TOX = 1 nm.

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