Teaching bit-slice microprocessor applications using simulation techniques

Teaching bit-slice microprocessor applications using simulation techniques Undergraduates can benefit substantially from an introduction to bit-slice microprocessors. A J Walker describes a digital system simulator with this teaching application in view

A case is often made for a greater emphasis on microprogramming techniques at an undergraduate level, particularly in view o f the ephemeral nature of fixed instruction set microprocessors. However, the basic principles involved in the design of modern computing machines may be more clearly understood when considered in terms of bit-slice microprocessors. The success of this teaching approach is heavily dependent on the nature of the teaching aids available to the student for the execution of microprogramming exercises. A minicomputer~ased interactive digital system simulator is described with a suite o f routines for the modelling of a comprehensive range o f bit and word processing logic elements and includes models of devices from a widely available bit-slice component family. A cursory review of the curricula of undergraduate level electrical engineering students in the field of computer engineering reveals a typical progression commencing with an introduction to combinational logic design, through sequential logic design to the concepts of the stored program computer I . The course continues with a consideration of the computer in relation to its environment with regard to hardware aspects (interfacing, peripherals, etc) and software aspects (operating systems, utilities, languages, etc). Most students readily grasp the concepts of macroinstruction sets, accumulators, scratchpad registers, stacks and the like, but admit to conceptual difficulties at the more fundamental level of microinstruction execution. To some it may appear an irrelevant concern as to how macroinstructions are executed and that what is of cardinal importance is that the student be able to make intelligent application of the computing machine and its resources. If a university education in the applied sciences is considered to be more concerned with reasons for the fundamental behaviour of physical systems, then in view of the ephemeral nature of fixed instruction set microprocessors, a good case may be made for introducing undergraduate students to microprogramming in a more concerted Department of Electrical Engineering, University of the Witwatersrand, 1 Jan Smuts Avenue, Johannesburg, 2001, South Africa

vol 5 no 9 november 1981

fashion than that which is presently made. The architecture of current fixed instruction set microprocessors and computers may then be introduced and the reasons for architectural differences appreciated with greater depth of understanding. In the author's opinion, the appropriate place in the curriculum for an introduction to microprogramming is directly following an exposure to the principles of sequential logic design. The concept of microprogramming as a cycle by cycle management and control of local hardware resources follows easily after a review of sequential logic design techniques. From an educational view-point it is important that the logical behaviour of student designed digital systems be verifiable. The logical behaviour of circuits consisting of combinational logic in most instances may be verified by careful inspection. In terms of sequential logic design this approach becomes progressively less effective with a growth in circuit complexity. While it may be more desirable to encourage students to verify pencil and paper sequential logic designs through hardware implementation, this approach is unpractical with large student numbers and a crowded curriculum. As in the case of popular fixed instruction set microprocessors, introductory kits and development systems are available for user microprogrammable microprocessors 2-~, although the nature of the support offered is a different order. The Advanced Micro Devices (AMD) learning and evaluation kit s, based on the AM 2900 bit-slice component family 6, has been designed to provide an introduction to these components and to facilitate the execution of simple microprogramming exercises. From a teaching view-point, the use of the kit is handicapped by a primitive man/machine interface in the form of switches for data entry and light emitting diodes for data display. An effort has been made to alleviate the worst effects of these limitations by interfacing the kit to a fixed instruction set microprocessor kit supporting a specially designed monitor with keyboard input and visual display output. The microinstruction sequencer and register/arithmetic logic unit (RALU) used in the AMD kit are both four bits wide, thus substantially limiting the number of microinstructions which may be executed and the computational

0141 --9331/81/090387-07 $02.00 © 1981 I PC Business Press

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precision. With no free board space, the kit is also architecturally inflexible.

TEACHING AID REQUIREMENTS Many of the problems relating to a student introduction to bit-slice microprocessors stem from the amount of time required to successfully implement and debug hardwarebased designs, the limitation of the man/machine interface (at best a logic analyser) and the time required to implement design changes. Restricted access to the states of significant registers (which are usually internal to the bit-slice components) serves to further hamper the design effort. These limitations taken together serve to obscure the learning process and the benefit of the exercise is lost amidst the details associated with entering, executing and debugging the microprogramming exercise. An alternative approach to the verification of the logical behaviour of student designed digital systems is simulation. All the impediments mentioned above to student understanding concerned architecture, word-lengths, data input and display may be overcome with an appropriate digital system simulator. There is freedom for growth in system complexity with the commensurate increase in student comprehension. The simulation tool should provide the facilities for the simultaneous display of a large number of device outputs in appropriate formats. Single-bit processing device outputs (gates, flipflops, etc) should be viewable in truth table or waveform format, while the outputs of word processing devices should be independently viewable in a user-selectable radix and data format. Word processing devices are largely encompassed by the medium and large scale range of integrated circuits. A key aspect in the successful application of simulation to the logical verification of student designs is the degree of availability of the simulation tool to the student. Batch execution of simulation exercises is generally undesirable on account of the unavoidable delays in the implementation of design changes. The execution and debugging of simulation exercises normally involves the process of source statement editing, compilation and execution. To reach the required degree of interactivity, it should not be necessary for the user to exit from the simulator to undertake any one of these activities. At execution time the user must be able to interrupt the execution, proceed if required, or be able to change the initial contents of registers, flipflops, memories, the periods of clock pulse sources and parameters relating to data display. The hardware description language used for the symbolic network description should, as far as possible, exhibit a one-to-one relationship between logic devices as represented in the schematic diagram and the network description statements. This assumes the availability of a comprehensive range of logic network modelling elements.

MINICOMPUTER-BASED LOGIC VERIFICATION AID The development of the logic verification aid 7 described here was stimulated by the apparent absence of a digital system simulator suitable for use at an undergraduate level. The principal objective was to provide a resource to which students would have easy access and, with a minimum of formal instruction, be able to successfully verify the

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behaviour of pencil and paper designed combinational and sequential logic circuits. In view of the intended teaching application, currently available packages for digital system simulation were considered unsuited to the task, being largely batch-oriented and requiring up to a mainframe processing environment 8,9 . The availability of a number of stand-alone Nova minicomputers and an Eclipse S/140-based multiuser multiprogramming system within the department led to the decision to produce a simulation tool which would successfully execute in a minicomputer environment. In view of the intended application of the simulation system to the verification of design exercises using bit-slice components, models of which (with a single exception) were not supported in available simulation packages, it was recognized that models of devices in this category would have to be developed. The verification of the logical behaviour of the models would be undertaken by comparing model behaviour against the logical behaviour of the equivalent physical component when stimulated with identical input conditions. It was considered that this type of comparison would be most easily implemented on the department's minicomputer systems. The simulation system software comprised an excessively large number of modelling routines. The executive is largely invisible to the user. The user interface to the executive is a suite of executive commands. The three modes of simulator operation are the system definition, program and runtime modes. The user is made aware of the present mode by a characteristic console prompt. The relationship between the executive commands and the prevailing mode of operation are shown in Figure 1. In the system definition mode the user must define the element type and quantity which will be required in the present simulation exercise. On completion of the system definition the program mode is entered, where the statements representing the symbolic network description are entered. A user program is divided into three segments by the keywords of BEGIN, SIMULATE and END. Statements between BEGIN and SIMULATE are executed once only at the start of a simulation exercise, while statements between SIMULATE and END are executed repeatedly and represent the main body of a simulation program.

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Figure 2. Symbolic networks description statements for the simulation of the AMD /earning and evaluation hit Statements which follow END are executed once only at the end of a simulation exercise. A single pass compiler is used to produce machine executable code. In the runtime mode the simulation is initialized and executed for the required number of states. The term state is used here in a loose sense to represent one time period. An executing program may be interrupted with the keyboard escape key. If desired, the simulation execution may be continued, data entered and the simulation rerun. The display of simulation results for bit processing elements (gate and flop devices) may be in truth table or waveform format. The outputs of word processing elements (predominantly those in the category of MSI and LSI devices) may be viewed in the radices of binary, octal, decimal and hexadecimal. The format of data representation of any element output may be changed at runtime. The hardware description language format follows the general form Element name, number, input parameter 1 . . . input parameter n Element name refers to a routine which may represent a system utility or a logic processing element mode. The number is a parameter typically associated with the logic element models and serves to distinguish between elements of the same type. The parameters 1 - n pertain to the outputs of the logic modelling elements and each parameter typically cons;sts of an Elen~ent name and number pair. The

vol 5 no 9 november 1981

input parameters are most frequently numerical in the runtime mode and serve to specify initial device states, clock periods, display presentation data and the like. Examples of the type of modelling elements available and the manner in which a simulation program is constructed is shown in Figure 2. The listing represents a simulation of the logical behaviour of the AMD learning and evaluation kit. The most complex device used in the kit is the AM 2901 RALU. To illustrate the manner in which this element model is used and the facilities which are available to the user, an overview is given to this device model.

AM 2901 REGISTER ARITHMETIC/LOGIC UNIT MODEL The essential aspects of the constituent logic elements in this device are shown in Figure 3. The key elements are 16 word by 4 bit two port random access memory (RAM) and an eight function arithmetic/logic unit (ALU). The RAM is provided with two address units, referred to as the A and B inputs and two data inputs. Data may be written into the memory using only the B address input when the RAM is enabled. Data input to the RAM is derived from a three input multiplexer, which is used to shift the ALU input. Independent latches are provided at the A and B output ports. These latches hold data when the clock is

389

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Figure 3. A MD learning and evaluation kit low, while data is simultaneously being written into the RAM. The ALU performs three arithmetic and five logical operations on the R and S input words. The R multiplexer derives inputs from the ALU output port and the direct data input. The S multiplexer derives its inputs from the A and B latch outputs and the Q register output. Both multiplexers have an inhibit facility. (Full details of this device and its functions are given elsewhere.) The outputs from the ALU include carry generate, carry propagate, carry out, most significant bit-state, result equal to zero and overflow status. The ALU output is routed to several destinations and can be used as the device output, or as input to the RAM or Q register. The symbolic network description program statement has the following form in the described simulator, AM01, number, Z, clock, ALU source, ALU function, ALU destination, direct data, A address, B address. (,Carry in, RAM 0, RAM Z-I, Q REG 0, Q REG Z-I, output enable) Each of the parameters, with the exception of Z, are normally derived from the outputs of other modelling elements (name element, number) in the logic circuit. The parameter Z (2 ~ Z ~ 16 bit) enable the user to specify the desired RALU word length. Data changes internal to the RALU occur on the low/high clock transition. The remaining input parameters each represent the physical equivalent. The word processing inputs (i.e., ALU source, function, destination, direct data, A and B RAM address inputs) are each represented by single input parameters. The specification of all parameters in brackets are optional and where omitted, they are assigned the value of zero.

390

The data statement has the form, AM01, number, address, data where (0 ~< Address ~< 16) enables the user to assign data values to the RAM locations 0-15, and to Q register which is treated as location 16. The ability to specify initial conditions to these registers facilitates the debugging of microprogramming exercises which might otherwise rely on previous microcode to initialize register contents. In all cases the data word entered into these registers lies in the range (0, 2Z-1 ). The physical device has eleven different outputs. In the device model, each output is accessed through the use of a parameter string AM01, number, output The significance of each output is listed in Table 1. Outputs 1-11 correspond to those available from the physical device, while outputs 12-45 allow access to a variety of internal states i.e., RAM locations, multiplexer outputs, as the simulation exercise proceeds. By means of these outputs the behaviour of the device may be examined in detail. From a teaching viewpoint, this type of facility has proved highly beneficial in helping students to understand the logical behaviour of the device.

Execution of micropro~'amming exercises using a simulation of the A M D kit The principal reason for introducing students to microprogramming by way of simulation is that there are considerably fewer obstacles to the learning process using interactive simulation techniques than using hardware-based teaching aids for the same purpose. It is obvious that a student will also benefit substantially from an exposure to the behaviour of physical bit-slice components, particu-

microprocessors and microsystems

Table 1. Output listings for parameter string Output

Description

6 7 8 9 10 11 12 13 14 15

RALU word output (Z bits wide) Carry generate Carry propagate Carry out Overflow Magnitude = 0 Most significant bit RAMp shifter output RAMz_z shifter output Q registero shifter output Q registerz_ 1 shifter output RAM enable RAM multiplexer control RAM multiplexer output RAM location 0 through to

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RAM location 15 RAM A port output RAM B port output A latch output B latch output Q register enable Q register multiplexer control Q register multiplexer output Q register input latch state Q register output latch state R multiplexer control R multiplexer output S multiplexer control S multiplexer output ALU word output ALU output multiplexer control

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larly with regard to the constraints of propagation delays, power consumption, etc. From a teaching point of view, a student would be required to master a representative range of microprogramming exercises, such as those described in the AMD handbook, using the simulated version of the kit, before proceeding to execute a more select range of exercises on a hardware version of the kit. The purpose behind the execution of the first group of exercises using the simulator is to develop an understanding of microprogramming as a technique, while the educational emphasis behind the execution of the second group of exercises is to develop an awareness of the physical characteristics and limitations of the components. Having mastered the concepts of microprogramming, the student has the necessary freedom using simulation to undertake microprogramming exercises of a more advanced nature, involving architectural extensions to the kit with a view of the simulation of a stored program computer with a representative range of macroinstructions. As shown in Figure 3, the inputs to the AM 2909 sequencer include the file enable (FE), push/pop control (PUP), multiplexer control ($1 So), and OR inputs. These are controlled by the mapping ROM, whose address select comprises the four next address bits from the microinstruction register and a least signiticant bit from the condition

vol 5 no 9 november 1981

code multiplexer. The carry-in control and register input of the sequencer are directly derived from fields of the microinstruction register. The microprogram memory has a 16 word address space and a 32-bit word length, which is partitioned into 11 fields which are dedicated to the selection of the next microinstruction address and the control of the RALU. The multiplexers which provide input/output control to the 16 word register array (RAM) and extension register (QREG) in the AM 2901 implement the four possible shift operations. The appropriate shift condition is selected by a 2-bit field in the program memory. The RALU status register and condition code multiplexer are controlled by the mapping ROM. The next microinstruction selection may be made conditional on the status of the RALU carry state, zero result, most significant bit, or overflow status. The simulated version of the kit differs from the vendor supplied kit in two respects. In the physical kit the register, Ri, in the AM 2909 constitutes part of the microinstruction register and hold the branch address. The use of Ri in this capacity has the advantage of reducing the number of integrated circuits needed for the microinstruction register. In the kit simulation the buffered output is available for all fields constituting the microprogram memory output and the branch address field is take directly to the D input of the sequencer. This difference is indiscernible to the user. The second difference concerns the combination of the shift condition multiplexer bits (MUX~, MUXe), which are separate in the physical kit, into a single 2-bit field in the simulated version of the kit. This adjustment simplifies the task of encoding microinstructions. With reference to Figure 4, ROM,2 represents the mapping ROM while ROM,1 serves as the program memory plus microinstruction register. A change in microprogramming exercises is simply implemented by changing the data in the latter memory. Latches 1,2 and 3 are pseudoelements in the sense that they have no equivalent in the physical kit, but are used for bit/word and word/bit conversion purposes for the generation of the mapping ROM address. The multiplexers, MUX,1-MUX,4 implement the various shift conditions, while BUFFER,1 and MUX,5 represent the status register and condition code multiplexer respectively. The AM 2909 sequencer and AM 2901 RALU are represented by AM09,1 and AM01,1 respectively. Data which are entered in the runtime mode may be updated as the need arises. With reference to Figure 5, the data entered into the mapping ROM reflects the address/data field entries required to implement the next instruction control data as supplied with the AMD kit. The address/data field entries shown for the microprogram memory in Figure S implement an exercise for counting the number of ones in a single register word (register 0 of the RALU). This exercise represents a simplified version of Exercise 10 in the AMD kit handbook. The present exercise serves to demonstrate the sequencer bebaviour with regard to continue, jump to subroutine, return from subroutine, conditional and unconditional branching. The aspects of RALU behaviour which are demonstrated are register loading, incrementing and decrementing, logical AND and no operation. The microprogram is executed for 25 microcycles (listed as 50 states), as shown in Figure 6. The sequencer next address output is listed alongside the internal state

391

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Figure 4. Block diagram o f the logic used for the simulation o f the AMD learning and evaluation kit

changes in the output of the multiplexer, incrementer, microprogram counter register, stackpointer and second file location. Similarly, the RALU output is shown alongside the internal state changes in the registers 0, 1 and 2, the outputs of A and B latches, S and R multiplexers and the RAM shifter output. CONCLUSIONS

This interactive digital system simulator was first introduced into the digital system design program for senior students in the Department of Electrical Engineering at * *

#

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moving from simulator familiarization, through microprogramming exercises using the simulation program of the * "

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the University in September 1979. Since that time the simulation software suite has been extended and refined, with many of the suggestions for improvement coming from the students concerned. To date, the most comprehensive teaching application of the simulation system has concerned the design of a stored program computer with a comprehensive macroinstruction set. In a term comprising 12 teaching weeks, a class of 22 senior students have each progressed through a series of four tasks,

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Figure 5. Runtime and data statements for the execution o f a simple microprogramming exercise

392

microprocessors and microsystems

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A A A A A A A A A A A A R R R R R R R M R M N ~

2 1 1 2 1 0 0 5 0 5 ~ 0 ~ 0 4 1 2 3 2 0 0 4 0 5 0 0 4 0 6 1 3 4 3 0 0 0 1 5 0 0 0 0 ~ t , 5 4 0 0 1 0 5 0 0 1 5 1 0 1 1 4 1 5 5 0 0 5 0 Z 0 0 0 5 12 I 5 6 1 5 1 5 1 0 2 0 0 0 0 14 i 6 7 6 0 5 3 0 2 0 0 0 4 1 6 1 3 4 7 0 5 2 0 2 0 0 2 0 1 8 1 4 5 4 0 5 0 1 2 0 0 . 2 1 5 6 5 0 5 2 0 1 0 0 0 2 1 6 7 6 0 5 2 0 1 0 0 0 3 2 4 1 3 4 7 0 5 1 0 1 0 0 1 0 2 6 1 4 5 4 0 5 1 0 1 0 0 1 1 2 8 1 1 4 1 5 5 0 5 1 0 0 0 0 0 1 I 5 6 1 5 1 5 2 0 0 0 0 0 1 1 6 7 6 0 5 1 0 0 0 0 0 2 1 3 4 7 0 5 0 1 0 0 0 0 0 3 6 1 4 5 4 0 5 0 1 0 0 0 1 0 4 2 1 1 46 | 4~ 1

7 8 7 0 5 0 1 0 0 0 0 0 1 5 0 8 0 5 0 1 0 0 0 0 0 1 5 0 0 0 5 2 0 0 0 0 0 2 15 0 0 0 5 2 0 0 0 0 0 2

Figure 6. Simulation results for a simple exercise

AMD kit, to the modelling of an elementary stored program computer based on the AMD kit architecture and finishing with the simulation of a stored program computer supporting a comprehensive macroinstruction set. The successful implementation of these tasks have required between 20 and 30 h of terminal time per student. The computer resources used for the support of the design program have included an Eclipse S/140 minicomputer (256 kbyte memory) supporting the advanced operating system 1° . The system further comprises a 25 Mbyte disc storage unit, four user consoles, operator console and a line printer. The simulation system software plus user workspace occupies 28 kbyte of memory per user. Versions of the simulator have been produced which are supported by the DOS/RDOS 11 and RTOSt2 operating systems. The simulation system software is executable on all Data General computers including and following the Nova 2 series.

vol 5 no 9 november 1981

REFERENCES 1 Zaky, S G, Vranisec, Z G and Hanacher V C 'On the teaching of computer organisation to engineering undergraduates' IEEE Trans. on Education Vol E-20 No 1 (1977) pp 27-30 2 Davies, A C and Ibrahim, D 'A basis for laboratory work with bit-slice microprogrammable microprocessors' Hartley, M G (Ed) The Challenge of Microprocessors Manchester University Press, Manchester, UK (1979) 3 Dimand, K R and King, J A 'A flexible development system for microprogrammable microprocessors' Hartley, M G (Ed) The Challenge of Microprocessors Manchester University Press, Manchester, UK (1979) 4 Gibson, R 'Microprogramming and microprocessors: investigation of development systems' Hartley, M G {Ed) The Challenge of Microprocessors Manchester University Press, Manchester, UK (1979) 5 A m 2900 Learning and Evaluation Kit Instruction Manual Advanced Micro Devices Inc., Sunnyvale,

California, USA (1976) 6 The Am Family Data Book Advanced Micro Devices

Inc., Sunnyvale, California, USA (1978) 7 Walker, A ] 'An interactive microcomputer based digital system simulator' Internal Research Report Department of Electrical Engineering, University of the Witwatersrand, Johannesburg, South Africa (1981) 8 Biancomono, V 'Logic simulators programs set pace in computer aided design' Electronics Vol 49 No 598 (1977) pp 98-101 9 Ashby, D H and Johnson, D 'Simulating digital logic networks' Electronic Engineering Vol 49 No 598 (1977) pp 71-72 10 Introduction to the Advanced Operating System Data General Corp., Southboro, Massachusetts, USA (1978) 11 Learning to use your RDOS/DOS Operating System Data General Corp., Southboro, Massachusetts, USA (1978) 12 Introduction to the Real Time Operating System

Data General Corp., Southboro, Massachusetts, USA (1974)

393