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Technology prevents reflow soldering defects linked to miniaturization
295
World Abstracts on Microelectronics and Reliability described, with examples of how each has improved quality and yield. (1) Silicon wafer measurements obtained from the supplier or made at incoming inspection are correlated with device parameters and chip yield. (2) Control charts in manufacturing are generated on-line from monitor wafer data entered by operators, giving immediate feedback. In addition, a daily summary report lists any chart out of control. In certain instances it is necessary to improve the process capability of an operation. A feedback technique is used to do this for operations which have a predictable systematic drift. (3) Individual wafer positions in critical operations are automatically recorded through the fabrication line. This greatly facilitates correlation of input to output parameters and pinpoints the root cause of physical, device parameter, of chip yield fluctuations. (4) Rapid correlation of the myriad of data obtained throughout the fabrication and wafer test areas is done with a common data base and tools which transform the raw data into an optimum form for analysis.
Automatic soldering technology accommodates computer needs. KAZUNORIOKI. JEE (Japan), 46 (October 1990). The introduction of the computer has given rise to a wave of electronics and automation sweeping over not only data collection, but also the fields of machine and production control. This trend has brought about a shift from analog to digital electronic equipment for both consumer and industrial use. Even in the field of mounting machinery today, when the switch from fexible manufacturing systems to computer-integrated manufacturing has attracted a great deal of attention, automatic soldering equipment that can accommodate computers is an important issue. Technology prevents reflow soldering defects linked to miniaturization. Nonuo KAMATA and KEIICHI SHIMAMAKLJEE (Japan), 34 (October 1990). Chip component mounting technologies and soldering technologies--in particular, reflow soldering techniques---occupy an important position in electronics. This article first surveys trends in mounting technology and the trend toward smaller chip component sizes in high-density mounting. Then it examines the causes of soldering defects in reflow soldering and the countermeasures against them. Finally it touches upon hurdles to be overcome in technological development. Multilayer ceramic packaging alternatives. JOHNL. SPRAGUE. IEEE Trans. Compon. Hybrids mfg Technol. 13(2), 390 (1990). This paper reviews the current state-of-the-art in multilayer substrates for integrated circuit (IC) packaging. The characteristics, advantages, and disadvantages of the following materials systems are presented: ct-A1203, BeO, AIN, SiC, Si3N4, BN, mullite, cordierite, glass-ceramics, low-K composites, and polymer systems such as polyimide. These are discussed in both single dielectric configurations as well as more complex systems such as the thin film multi-chip module (TFMCM), Si-on-Si wafer-scale integration (SOSWSI), and packaging schemes that incorporate passive components such as capacitors in the substrate. The following conclusions are drawn: (I) the package is less and less just a protective environment and more and more a key functional part of the entire electronic system: (2) the systems manufacturer will play an increasingly important role as the creator of the package; (3) the multichip module (MCM) will slowly be replaced by such schemes as SOSWSI and especially TFMCM; and (4) while A1203 will continue to dominate the materials field, a number of other materials will be increasingly used,
6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S , A new intelligent one-chip microcomputer: the applicationspecific mierocompnter. JEE (Japan), 40 (May 1990). For the
especially AIN and SiC, where thermal dissipation is key, and Cu/polymer systems, where low dielectric constants are required.
Mass production buck-grinding/wafer-thinning technology for GaAs devices. MASANORINISHIGUCHI et al. IEEE Trans. Compon. Hybrids mfg Technol. 13(3), 528 (1990). The first mass production back-grinding technology that is applicable to a fully-automatic wafer-thinning process in GaAs device manufacturing has been successfully developed. Excellent productivity has been realized because the brittleness of GaAs has been overcome. A mirror-like stress-free surface was obtained by utilizing the wafer-rotating downfeed grinding method with slight chemical etching. The thickness of the deformed layer due to back-grinding was evaluated at 0.6/~m. The wafer bow and the changes in electrical characteristics of GaAs devices caused by this layer were eliminated by chemical etching. The threshold voltages of GaAs MESFETs were confirmed to shift negatively by no more than 5 mV. This technology has been successfully demonstrated in several kinds of GaAs device fabrication processes. New development of thin plastic package with high terminal counts. MASANOBUKOHARA et al. IEEE Trans. Comport. Hybrids mfg Technol. 13(2), 401 (1990). A small and thin quad flat package (QFP) type plastic package for logic large scale integrated (LSI) devices with high pin counts has been newly developed. The size of the package with 252 input and output pins is 17.3 by 17.3 mm and the thickness is 1.52 mm. The pitch and the width of the leads are 0.25 and 0.1 mm, respectively. The main technologies for assembly of the packages are tape automated bonding (TAB) interconnection technology which has been developed for bonding of high-terminalcount LSIs, and the molding technology which has also been developed for very small and thin plastic packages. The reliability of the package and the outer lead bonding of the package were evaluated, and it was confirmed that both the package and the bonding have no problem in the pressure cooker test (PCT), the temperature cycle test, and the high-temperature-storage test. On the possibility of internal gettering in commercially available silicon wafers. KRZYSZTOFKUCHARSK1,JAROSLAW JABLONSKI and JERZY WOJCIECHOWSKI. Electron. Technol. 21(3/4), 21 (1988). The results of the study on internal gettering in commercially available, domestic Czochralskigrown (CZ) silicon are presented. The effect of pre-annealing conditions on the parameters of internal getter in reference samples with well-determined interstitial oxygen concentration are discussed as well as the possibility of internal getter formation in silicon wafers with uncontrolled interstitial oxygen concentration used for current IC production. The methodology of internal getter formation and modification of its parameters is presented. The influence of the getter parameters on the effectiveness of contamination removal was studied. The pre-annealing conditions allowing for improvement of subsurface active region parameters in silicon wafers utilized in a manufacturing process were determined. An improvement of material parameters manifesting itself by an increase of minority carrier generation lifetime was observed both for the case of a thermal simulation of the IC fabrication process as well as for the real manufacturing process of integrated circuits produced by CMOS, NMOS and PMOS technologies.
SYSTEMS
AND
EQUIPMENTS
"unseen controller" in consumer electricals, ASIC technology is providing solutions to the market demand for more
World Abstracts on Microelectronics and Reliability described, with examples of how each has improved quality and yield. (1) Silicon wafer measurements obtained from the supplier or made at incoming inspection are correlated with device parameters and chip yield. (2) Control charts in manufacturing are generated on-line from monitor wafer data entered by operators, giving immediate feedback. In addition, a daily summary report lists any chart out of control. In certain instances it is necessary to improve the process capability of an operation. A feedback technique is used to do this for operations which have a predictable systematic drift. (3) Individual wafer positions in critical operations are automatically recorded through the fabrication line. This greatly facilitates correlation of input to output parameters and pinpoints the root cause of physical, device parameter, of chip yield fluctuations. (4) Rapid correlation of the myriad of data obtained throughout the fabrication and wafer test areas is done with a common data base and tools which transform the raw data into an optimum form for analysis.
Automatic soldering technology accommodates computer needs. KAZUNORIOKI. JEE (Japan), 46 (October 1990). The introduction of the computer has given rise to a wave of electronics and automation sweeping over not only data collection, but also the fields of machine and production control. This trend has brought about a shift from analog to digital electronic equipment for both consumer and industrial use. Even in the field of mounting machinery today, when the switch from fexible manufacturing systems to computer-integrated manufacturing has attracted a great deal of attention, automatic soldering equipment that can accommodate computers is an important issue. Technology prevents reflow soldering defects linked to miniaturization. Nonuo KAMATA and KEIICHI SHIMAMAKLJEE (Japan), 34 (October 1990). Chip component mounting technologies and soldering technologies--in particular, reflow soldering techniques---occupy an important position in electronics. This article first surveys trends in mounting technology and the trend toward smaller chip component sizes in high-density mounting. Then it examines the causes of soldering defects in reflow soldering and the countermeasures against them. Finally it touches upon hurdles to be overcome in technological development. Multilayer ceramic packaging alternatives. JOHNL. SPRAGUE. IEEE Trans. Compon. Hybrids mfg Technol. 13(2), 390 (1990). This paper reviews the current state-of-the-art in multilayer substrates for integrated circuit (IC) packaging. The characteristics, advantages, and disadvantages of the following materials systems are presented: ct-A1203, BeO, AIN, SiC, Si3N4, BN, mullite, cordierite, glass-ceramics, low-K composites, and polymer systems such as polyimide. These are discussed in both single dielectric configurations as well as more complex systems such as the thin film multi-chip module (TFMCM), Si-on-Si wafer-scale integration (SOSWSI), and packaging schemes that incorporate passive components such as capacitors in the substrate. The following conclusions are drawn: (I) the package is less and less just a protective environment and more and more a key functional part of the entire electronic system: (2) the systems manufacturer will play an increasingly important role as the creator of the package; (3) the multichip module (MCM) will slowly be replaced by such schemes as SOSWSI and especially TFMCM; and (4) while A1203 will continue to dominate the materials field, a number of other materials will be increasingly used,
6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S , A new intelligent one-chip microcomputer: the applicationspecific mierocompnter. JEE (Japan), 40 (May 1990). For the
especially AIN and SiC, where thermal dissipation is key, and Cu/polymer systems, where low dielectric constants are required.
Mass production buck-grinding/wafer-thinning technology for GaAs devices. MASANORINISHIGUCHI et al. IEEE Trans. Compon. Hybrids mfg Technol. 13(3), 528 (1990). The first mass production back-grinding technology that is applicable to a fully-automatic wafer-thinning process in GaAs device manufacturing has been successfully developed. Excellent productivity has been realized because the brittleness of GaAs has been overcome. A mirror-like stress-free surface was obtained by utilizing the wafer-rotating downfeed grinding method with slight chemical etching. The thickness of the deformed layer due to back-grinding was evaluated at 0.6/~m. The wafer bow and the changes in electrical characteristics of GaAs devices caused by this layer were eliminated by chemical etching. The threshold voltages of GaAs MESFETs were confirmed to shift negatively by no more than 5 mV. This technology has been successfully demonstrated in several kinds of GaAs device fabrication processes. New development of thin plastic package with high terminal counts. MASANOBUKOHARA et al. IEEE Trans. Comport. Hybrids mfg Technol. 13(2), 401 (1990). A small and thin quad flat package (QFP) type plastic package for logic large scale integrated (LSI) devices with high pin counts has been newly developed. The size of the package with 252 input and output pins is 17.3 by 17.3 mm and the thickness is 1.52 mm. The pitch and the width of the leads are 0.25 and 0.1 mm, respectively. The main technologies for assembly of the packages are tape automated bonding (TAB) interconnection technology which has been developed for bonding of high-terminalcount LSIs, and the molding technology which has also been developed for very small and thin plastic packages. The reliability of the package and the outer lead bonding of the package were evaluated, and it was confirmed that both the package and the bonding have no problem in the pressure cooker test (PCT), the temperature cycle test, and the high-temperature-storage test. On the possibility of internal gettering in commercially available silicon wafers. KRZYSZTOFKUCHARSK1,JAROSLAW JABLONSKI and JERZY WOJCIECHOWSKI. Electron. Technol. 21(3/4), 21 (1988). The results of the study on internal gettering in commercially available, domestic Czochralskigrown (CZ) silicon are presented. The effect of pre-annealing conditions on the parameters of internal getter in reference samples with well-determined interstitial oxygen concentration are discussed as well as the possibility of internal getter formation in silicon wafers with uncontrolled interstitial oxygen concentration used for current IC production. The methodology of internal getter formation and modification of its parameters is presented. The influence of the getter parameters on the effectiveness of contamination removal was studied. The pre-annealing conditions allowing for improvement of subsurface active region parameters in silicon wafers utilized in a manufacturing process were determined. An improvement of material parameters manifesting itself by an increase of minority carrier generation lifetime was observed both for the case of a thermal simulation of the IC fabrication process as well as for the real manufacturing process of integrated circuits produced by CMOS, NMOS and PMOS technologies.
SYSTEMS
AND
EQUIPMENTS
"unseen controller" in consumer electricals, ASIC technology is providing solutions to the market demand for more