- Email: [email protected]
Temperature dependence of TDDB at high frequency in 28FDSOI
Microelectronics Reliability 100–101 (2019) 113422
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Temperature dependence of TDDB at high frequency in 28FDSOI M. Arabi a b c
a,b,c,⁎
a
a
a
b
b
, X. Federspiel , F. Cacho , M. Rafik , A.-P. Nguyen , X. Garros , G. Ghibaudo
T c
STMicroelectronics, 850 Rue Jean Monnet, Crolles, France CEA-LETI, 17 Avenue des Martyrs, Grenoble, France IMEP-LAHC, Minatec, 3 Parvis Louis Néel, Grenoble, France
A B S T R A C T
Time Dependent Dielectric Breakdown (TDDB) experiments are performed in the GHz frequency range on a dedicated test structure to mimic operating conditions. It is shown that TDDB device lifetime can be significantly improved at high frequency in the temperature range from −40 °C to 200 °C. In addition, no effect on voltage acceleration is measured between DC and AC stress modes. This result has strong implications for logic circuit lifetime estimation over extended voltage and temperature ranges and gives new insights on the mechanism responsible for AC TDDB effects.
1. Introduction In advanced CMOS nodes, TDDB remains a key reliability concern [1,2]. Recently, it was shown that AC TDDB can greatly improve lifetime projection in realistic digital operating conditions w.r.t DC [3–5]. In previous works, we have shown a significant TDDB improvement on both NMOS and PMOS of both HK/MG and SiON/Poly based technologies [6] up to 1 MHz and extended to 1GHz using an embedded RO structure (see Fig. 1) [7,8]. In the present work, we analyze the temperature activation of N/P FET TDDB up to 1GHz speed, to refine reliability projections at product level. 2. Test structure and experimental description Performing TDDB at GHz frequency, which partly represents circuit operation conditions, imposes several challenges. The main difficulty consists in delivering a high frequency AC signal to the DUT almost without any transmission line loss and significant signal overshoot/ distortion induced by signal through cables, switching matrices and probe card. To overcome this issue, we have used a test structure embedding a GHz voltage stress source made in HK/MG 28 nm FDSOI technology, which is able to measure TDDB of P/NFETs devices in DC and pulsed AC conditions up to 1GHz. Fig. 1 depicts the structure that integrates a ring oscillator, which can support two stress modes using an “Enable” pin. This structure is able to deliver either a DC or a pulsed square AC signal up to 1GHz to the DUT. For comparison, a pulsed AC 1 MHz stress is also achieved using a transistor reference and an external pulse generator. Tests have been performed at wafer level at several temperatures ranging from −40 °C to 200 °C. Due to the large extent of the
⁎
temperature range, TDDB stresses are made at several biases depending on the temperature and extrapolated at a same VStress of −2.8 V for PMOS and 2.6 V for NMOS. In the following, time to breakdown TBD denotes the cumulated stress time i.e. the time spent at the stress voltage only over an AC period. For a 50% duty factor AC stress, this corresponds to half of the total stress time. 3. Results and discussions In our previous work [7], we demonstrated that TBD of both PMOS & NMOS is significantly improved when performed at GHz frequency with respect to DC (see Fig. 2). a. Voltage acceleration In this paper, we have extended our study to determine if this benefit brought by AC high frequency tests holds for all the temperatures and stress voltages. Therefore, we first evaluated the stability of the TBDAC/TBDDC ratio as the function of stress biases. This parameter is investigated for NMOS at temperature of 165 °C with a stress voltage of 2.4 & 2.6 V. For PMOS, the stress is applied in the range [−2.5 V, −2.8 V] at a temperature of 125 °C. TBD@63% is extracted at DC, 1 MHz and 1GHz (see Figs. 3 & 4). As reported in Fig. 3, voltage acceleration factor (VAF) at 165 °C is n = 57. For NMOS, there is no effect on VAF regardless of temperature. The voltage acceleration factor shown in Fig. 4 for the PMOS is specifically mentioned for only one temperature (125 °C). In fact, the acceleration factor decreases linearly with increasing the temperature. The table below shows the acceleration factors for each temperature in our experimental window.
Corresponding author at: STMicroelectronics, 850 Rue Jean Monnet, Crolles, France. E-mail address: [email protected] (M. Arabi).
https://doi.org/10.1016/j.microrel.2019.113422 Received 13 May 2019; Received in revised form 19 June 2019; Accepted 9 July 2019 Available online 23 September 2019 0026-2714/ © 2019 Elsevier Ltd. All rights reserved.
Microelectronics Reliability 100–101 (2019) 113422
M. Arabi, et al.
Fig. 1. Schematic of the test structure. Ring Oscillator delivers a square AC signal to two pass-gates connected to DUT. This allows switching the DUT gate between VDD & Vstress on AC mode [7,8]. A “Enable” pin is also used to switch off the RO and activate DC.
Fig. 2. State of the art TBDAC/TBDDC ratios on PMOS and NMOS vs frequency. Ratio almost increases linearly with frequency proving that breakdown event is postponed at circuit operation at GHz [7].
T (C°) n
−40 68
0
25
75
125
165
200
57
51
42
35
31
28
Fig. 3. Time to Breakdown TBD@63% versus Gate voltage on 28 nm NMOS stressed at 165 °C in DC and AC conditions.
As for PMOS, Weibull distributions at varied temperatures and frequencies are shown on Figs. 9, 10 and 11, no significant change of Weibull slopes is observed. Likewise, Arrhenius plots depicted in Fig. 12 show only little change of the ratio AC/DC with respect to temperature. This minor change might be within statistical error as higher dispersion is seen on PMOS TBD compared to NMOS (β = 0.9). Finally, the RO test structures allows to extend the experimental frequency range up to 1GHz and to demonstrate a continuous increase of TBD at high frequencies without saturation effect. However, no significant effect of frequency on Weibull slope (β), Voltage dependence (B), and activation energy (Ea) is evidenced (Eq. (1)).
It is observed that TBD@63% improves with rising frequency regardless of stress voltage. Furthermore, voltage acceleration factor (VAF) is the same for all test conditions. b. Temperature dependence Continuing our study in the GHz range, we then investigated how temperature influences the frequency dependency of TBD. TDDB failure distributions of NMOS are reported in Figs. 5, 6 & 7. It can be noticed that Weibull slope remains stable at all temperatures; it means that the temperature has no effect on β parameter. As reported on Fig. 8, activation energy Ea is unchanged regardless the stress mode. This suggests that the physical mechanism responsible for the frequency effect is not affected by temperature.
⎛ ln(− ln(1 − F )) ⎞ β ⎠.
TBD = R (Freq). VG−B. e⎝
e(
−Ea kT
)
(1)
From an industrial point of view, it shows that the benefit of AC TDDB might be expected over a wide range of circuit operation. On the other hand, from a physical understanding point of view it suggests that AC TDDB is due to a frequency dependent defect generation rate or to 2
Microelectronics Reliability 100–101 (2019) 113422
M. Arabi, et al.
Fig. 4. Time to Breakdown TBD@63% extracted on 28 nm PMOS at 125 °C. Voltage acceleration factor is approximatively the same for DC and AC stresses.
Fig. 7. Weibull distributions for NMOS at 165 °C under 1GHz stress. Like 1 MHz, Weibull slope is independent of temperature 125 & 165 °C.
Fig. 5. NMOS TDDB failure distributions measured at several temperatures and same DC stress Vstress = +2.6 V No significant change of β is observed.
Fig. 8. Temperature dependence of TBD for NMOS stressed under DC, 1 MHz and 1GHz. The activation energy remains constant for both modes (DC&AC) from −40 °C to 200 °C.
an indirect mechanism that does not depend on temperature and voltage. In order to describe the physical mechanism responsible for this improvement, hypothesis will be raised and additional measurements will be proposed to confront them with experimental evidences.
4. The physical mechanism responsible for AC effects a. Stress Induced Leakage Current (SILC) SILC has been characterized on reference NMOS devices. We used a B1530 fast measurement unit to record the gate leakage IG at low voltage VG = +1 V during typical DC and AC stress. Fig. 13 reported the SILC evolution vs. stress time. SILC is clearly lower at 100 kHz compared to DC. If we assume that SILC is a direct monitor of the oxide wear-out, it can be deduced that the defect generation rate is lower or that the triggering of defect generation is delayed with increasing the frequency.
Fig. 6. Weibull distributions obtained on NMOS under 1 MHz AC stress. Weibull slope is stable with temperature, DC and AC stress. 3
Microelectronics Reliability 100–101 (2019) 113422
M. Arabi, et al.
Fig. 9. PMOS TDDB failure distributions under DC stress at several temperatures. Like NMOS, β is independent of temperature.
Fig. 11. Weibull distributions obtained on PMOS under 1GHz AC stress. Weibull slopes remain stable for various temperatures.
Fig. 12. Temperature dependence of TBD for PMOS stressed under DC, 1 MHz and 1GHz. The activation energy is almost constant from - 40 °C to 200 °C.
Fig. 10. Weibull distributions of PMOS under 1 MHz stress at several temperatures. Weibull slope remains constant with temperature.
b. BTI trapping A possible explanation for the AC effect is a correlation with trapping/detrapping mechanism [9]. To give insight on this possible correlation, fast AC BTI measurements have been performed under the same stress conditions that are used for TDDB AC conditions. Furthermore, the Id-Vg acquisition for VTH extraction is within 10us to limit recovery. As shown in Fig.14, unlike TDDB, no significant ΔVTH dependence on frequency is observed; proving that there is no straight correlation between the two phenomena. Besides, no trend in TBDAC/ TBDDC vs. ΔVTH plot can be evidenced over a wide range of AC TDDB conditions. Therefore, neither a contribution of defects responsible for trapping/detrapping to breakdown path formation, nor an indirect modulation of electrical field induced by VTH drift can explain AC TDDB observations. c. Local electric field fluctuations Fig. 13. Stress Induced Leakage Current (IG(t)-IG(0)) measured on NMOS vs effective stress time under DC and AC stress at VG stress = +2.6 V.
Among the different physical mechanisms proposed to explain the generation of the defects which are responsible for breakdown, 4
Microelectronics Reliability 100–101 (2019) 113422
M. Arabi, et al.
Fig. 14. Fast PBTI stress and recovery at various frequencies. No direct correlation between Vth shift and TBD is observed. Unlike TDDB, PBTI shift appears frequency independent. Fig. 16. TDDB failure distribution for standard AC stresses with two different Vlow and an AC stress with a 1 μs conditioning step at -2 V.
thermochemical model (E) has been widely discussed [10]. Interestingly, McPherson proposes a description of bond breakage mechanism directly correlated to local field [11]. In this approach, if the switching of the gate voltage during AC stress induce fluctuation of the local field within the oxide, it is likely to explain fluctuations in defect generation rate. Trying to evidence this effect, we propose to add, in the stress sequence, an additional conditioning step prior to typical AC stress stage (see Fig. 15). Its goal is to induce local electrical field fluctuations, by changing the oxide polarization, but at sufficient low voltage to prevent any additional defect creation during this stage. A pre-step of 1us at -2 V is added to a conventional AC stress at -2.8 V/1 MHz. Another configuration with a step at +2 V has also been done. Fig. 16 compares these TDDB results with those from standard AC stress. TDDB distributions at 1 MHz are the same regardless of VLow or the conditioning step. This indicates that the local electrical field fluctuations potentially induced by the conditioning steps did not change significantly the defect generation rate.
NMOS, independently of the temperature, and contributes to extend lifetime in circuit operating condition. Moreover, in this extended study with varying voltage and temperature, it is shown that there is no effect on the acceleration factor over a measured voltage range of 2.4 V to 2.6 V for NMOS and −2.5 V & -2.8 V for PMOS. On the other hand, the temperature dependence is confirmed for AC, with the same activation energy as DC. Finally, it is assumed that the effect of SILC correlates best with our study, whereas BTI and local field effects could be excluded. It can be deduced that the defect generation rate is lower or that the triggering of defect generation is delayed with increasing the frequency. Declaration of Competing Interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
5. Conclusion
Acknowledgements
To conclude, the frequency dependence is significant for PMOS &
The author would like to thank the reliability team of STMicroelectronics and CEA-Leti for their collaboration in this work.
VLow
References [1] S. Knebel, S. Kupke, U. Schroeder, S. Slesazeck, T. Mikolajick, R. Agaiby, M. Trentzsch, Influence of frequency dependent time to breakdown on high-k/metal gate reliability, IEEE Trans. Electron Devices 60 (2013) 2368–2371, https://doi. org/10.1109/TED.2013.2264104. [2] C. Chen, S. Chang, S. Chen, Y.-H. Lee, Y. Lee, D. Huang, J. Shih, K. Wu, The physical mechanism investigation of AC TDDB behavior in advanced gate stackX, Reliab. Phys. Symp. 2014 IEEE Int, IEEE, 2014, pp. 5B–5. [3] T.-Y. Yew, Y.-C. Huang, M.-H. Hsieh, W. Wang, W.-S. Chou, P.-Z. Kang, Y.-H. Lee, K. Wu, The impacts of inverter-like transitions on AC TDDB in a fast switching logic circuit, Integr. Reliab. Workshop Final Rep. IIRW 2014 IEEE Int, IEEE, 2014, pp. 47–50. [4] M. Saliva, F. Cacho, V. Huard, D. Angot, X. Federspiel, M. Durand, M. Parra, A. Bravaix, L. Anghel, New insights about oxide breakdown occurrence at circuit level, Reliab. Phys. Symp. 2014 IEEE Int. IEEE, 2014, pp. 2D–5. [5] K.T. Lee, J. Nam, M. Jin, K. Bae, J. Park, L. Hwang, J. Kim, H. Kim, J. Park, Frequency dependent TDDB behaviors and its reliability qualification in 32nm highk/metal gate CMOSFETs, Reliab. Phys. Symp. IRPS 2011 IEEE Int. IEEE, 2011, pp. 2A–3. [6] M. Rafik, A. Nguyen, X. Garros, M. Arabi, X. Federspiel, C. Diouf, AC TDDB extensive study for an enlargement of its impact and benefit on circuit lifetime assessment, Reliab. Phys. Symp. IRPS 2018 IEEE Int. IEEE, 2018, pp. 4A–3. [7] M. Arabi, X. Federspiel, F. Cacho, M. Rafik, A. Nguyen, X. Garros, G. Ghibaudo, New insights on device level TDDB at GHz speed in advanced CMOS nodes, Integr. Reliab. Workshop Final Rep. IRW 2018 IEEE Int. 2018.
Vpolarization VHigh
Fig. 15. Typical pattern applied on PMOS at “1 MHz” with a -2 V conditioning step before the conventional stress stage at VGstress = −2.8 V. The purpose of this additional step is to change the local oxide electric field, by modifying polarization in the oxide, without affecting defect generation rate. 5
Microelectronics Reliability 100–101 (2019) 113422
M. Arabi, et al.
[10] J.W. McPherson, J. Kim, A. Shanware, H. Mogul, J. Rodriguez, Trends in the ultimate breakdown strength of high dielectric-constant materials, IEEE Trans. Electron Devices 50 (2003) 1771–1778. [11] J. McPherson, Quantum mechanical treatment of Si-O bond breakage in silica under time dependent dielectric breakdown testing, in: 2007 IEEE Int. Reliab. Phys. Symp. Proc. 45th Annu., IEEE, 2007: pp. 209–216.
[8] F. Cacho, D. Nouguier, M. Arabi, X. Federspiel, Y. Carminati, M. Saliva, Integrated test structures for reliability investigation under dynamic stimuli, 2018 IEEE 24th Int. Symp. -Line Test. Robust Syst. Des. IOLTS, IEEE, 2018, pp. 1–5. [9] A. Kerber, A. Vayshenker, D. Lipp, T. Nigam, E. Cartier, Impact of charge trapping on the voltage acceleration of TDDB in metal gate/high-k n-channel MOSFETs, Reliab. Phys. Symp. IRPS 2010 IEEE Int. IEEE, 2010, pp. 369–372.
6
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Temperature dependence of TDDB at high frequency in 28FDSOI M. Arabi a b c
a,b,c,⁎
a
a
a
b
b
, X. Federspiel , F. Cacho , M. Rafik , A.-P. Nguyen , X. Garros , G. Ghibaudo
T c
STMicroelectronics, 850 Rue Jean Monnet, Crolles, France CEA-LETI, 17 Avenue des Martyrs, Grenoble, France IMEP-LAHC, Minatec, 3 Parvis Louis Néel, Grenoble, France
A B S T R A C T
Time Dependent Dielectric Breakdown (TDDB) experiments are performed in the GHz frequency range on a dedicated test structure to mimic operating conditions. It is shown that TDDB device lifetime can be significantly improved at high frequency in the temperature range from −40 °C to 200 °C. In addition, no effect on voltage acceleration is measured between DC and AC stress modes. This result has strong implications for logic circuit lifetime estimation over extended voltage and temperature ranges and gives new insights on the mechanism responsible for AC TDDB effects.
1. Introduction In advanced CMOS nodes, TDDB remains a key reliability concern [1,2]. Recently, it was shown that AC TDDB can greatly improve lifetime projection in realistic digital operating conditions w.r.t DC [3–5]. In previous works, we have shown a significant TDDB improvement on both NMOS and PMOS of both HK/MG and SiON/Poly based technologies [6] up to 1 MHz and extended to 1GHz using an embedded RO structure (see Fig. 1) [7,8]. In the present work, we analyze the temperature activation of N/P FET TDDB up to 1GHz speed, to refine reliability projections at product level. 2. Test structure and experimental description Performing TDDB at GHz frequency, which partly represents circuit operation conditions, imposes several challenges. The main difficulty consists in delivering a high frequency AC signal to the DUT almost without any transmission line loss and significant signal overshoot/ distortion induced by signal through cables, switching matrices and probe card. To overcome this issue, we have used a test structure embedding a GHz voltage stress source made in HK/MG 28 nm FDSOI technology, which is able to measure TDDB of P/NFETs devices in DC and pulsed AC conditions up to 1GHz. Fig. 1 depicts the structure that integrates a ring oscillator, which can support two stress modes using an “Enable” pin. This structure is able to deliver either a DC or a pulsed square AC signal up to 1GHz to the DUT. For comparison, a pulsed AC 1 MHz stress is also achieved using a transistor reference and an external pulse generator. Tests have been performed at wafer level at several temperatures ranging from −40 °C to 200 °C. Due to the large extent of the
⁎
temperature range, TDDB stresses are made at several biases depending on the temperature and extrapolated at a same VStress of −2.8 V for PMOS and 2.6 V for NMOS. In the following, time to breakdown TBD denotes the cumulated stress time i.e. the time spent at the stress voltage only over an AC period. For a 50% duty factor AC stress, this corresponds to half of the total stress time. 3. Results and discussions In our previous work [7], we demonstrated that TBD of both PMOS & NMOS is significantly improved when performed at GHz frequency with respect to DC (see Fig. 2). a. Voltage acceleration In this paper, we have extended our study to determine if this benefit brought by AC high frequency tests holds for all the temperatures and stress voltages. Therefore, we first evaluated the stability of the TBDAC/TBDDC ratio as the function of stress biases. This parameter is investigated for NMOS at temperature of 165 °C with a stress voltage of 2.4 & 2.6 V. For PMOS, the stress is applied in the range [−2.5 V, −2.8 V] at a temperature of 125 °C. TBD@63% is extracted at DC, 1 MHz and 1GHz (see Figs. 3 & 4). As reported in Fig. 3, voltage acceleration factor (VAF) at 165 °C is n = 57. For NMOS, there is no effect on VAF regardless of temperature. The voltage acceleration factor shown in Fig. 4 for the PMOS is specifically mentioned for only one temperature (125 °C). In fact, the acceleration factor decreases linearly with increasing the temperature. The table below shows the acceleration factors for each temperature in our experimental window.
Corresponding author at: STMicroelectronics, 850 Rue Jean Monnet, Crolles, France. E-mail address: [email protected] (M. Arabi).
https://doi.org/10.1016/j.microrel.2019.113422 Received 13 May 2019; Received in revised form 19 June 2019; Accepted 9 July 2019 Available online 23 September 2019 0026-2714/ © 2019 Elsevier Ltd. All rights reserved.
Microelectronics Reliability 100–101 (2019) 113422
M. Arabi, et al.
Fig. 1. Schematic of the test structure. Ring Oscillator delivers a square AC signal to two pass-gates connected to DUT. This allows switching the DUT gate between VDD & Vstress on AC mode [7,8]. A “Enable” pin is also used to switch off the RO and activate DC.
Fig. 2. State of the art TBDAC/TBDDC ratios on PMOS and NMOS vs frequency. Ratio almost increases linearly with frequency proving that breakdown event is postponed at circuit operation at GHz [7].
T (C°) n
−40 68
0
25
75
125
165
200
57
51
42
35
31
28
Fig. 3. Time to Breakdown TBD@63% versus Gate voltage on 28 nm NMOS stressed at 165 °C in DC and AC conditions.
As for PMOS, Weibull distributions at varied temperatures and frequencies are shown on Figs. 9, 10 and 11, no significant change of Weibull slopes is observed. Likewise, Arrhenius plots depicted in Fig. 12 show only little change of the ratio AC/DC with respect to temperature. This minor change might be within statistical error as higher dispersion is seen on PMOS TBD compared to NMOS (β = 0.9). Finally, the RO test structures allows to extend the experimental frequency range up to 1GHz and to demonstrate a continuous increase of TBD at high frequencies without saturation effect. However, no significant effect of frequency on Weibull slope (β), Voltage dependence (B), and activation energy (Ea) is evidenced (Eq. (1)).
It is observed that TBD@63% improves with rising frequency regardless of stress voltage. Furthermore, voltage acceleration factor (VAF) is the same for all test conditions. b. Temperature dependence Continuing our study in the GHz range, we then investigated how temperature influences the frequency dependency of TBD. TDDB failure distributions of NMOS are reported in Figs. 5, 6 & 7. It can be noticed that Weibull slope remains stable at all temperatures; it means that the temperature has no effect on β parameter. As reported on Fig. 8, activation energy Ea is unchanged regardless the stress mode. This suggests that the physical mechanism responsible for the frequency effect is not affected by temperature.
⎛ ln(− ln(1 − F )) ⎞ β ⎠.
TBD = R (Freq). VG−B. e⎝
e(
−Ea kT
)
(1)
From an industrial point of view, it shows that the benefit of AC TDDB might be expected over a wide range of circuit operation. On the other hand, from a physical understanding point of view it suggests that AC TDDB is due to a frequency dependent defect generation rate or to 2
Microelectronics Reliability 100–101 (2019) 113422
M. Arabi, et al.
Fig. 4. Time to Breakdown TBD@63% extracted on 28 nm PMOS at 125 °C. Voltage acceleration factor is approximatively the same for DC and AC stresses.
Fig. 7. Weibull distributions for NMOS at 165 °C under 1GHz stress. Like 1 MHz, Weibull slope is independent of temperature 125 & 165 °C.
Fig. 5. NMOS TDDB failure distributions measured at several temperatures and same DC stress Vstress = +2.6 V No significant change of β is observed.
Fig. 8. Temperature dependence of TBD for NMOS stressed under DC, 1 MHz and 1GHz. The activation energy remains constant for both modes (DC&AC) from −40 °C to 200 °C.
an indirect mechanism that does not depend on temperature and voltage. In order to describe the physical mechanism responsible for this improvement, hypothesis will be raised and additional measurements will be proposed to confront them with experimental evidences.
4. The physical mechanism responsible for AC effects a. Stress Induced Leakage Current (SILC) SILC has been characterized on reference NMOS devices. We used a B1530 fast measurement unit to record the gate leakage IG at low voltage VG = +1 V during typical DC and AC stress. Fig. 13 reported the SILC evolution vs. stress time. SILC is clearly lower at 100 kHz compared to DC. If we assume that SILC is a direct monitor of the oxide wear-out, it can be deduced that the defect generation rate is lower or that the triggering of defect generation is delayed with increasing the frequency.
Fig. 6. Weibull distributions obtained on NMOS under 1 MHz AC stress. Weibull slope is stable with temperature, DC and AC stress. 3
Microelectronics Reliability 100–101 (2019) 113422
M. Arabi, et al.
Fig. 9. PMOS TDDB failure distributions under DC stress at several temperatures. Like NMOS, β is independent of temperature.
Fig. 11. Weibull distributions obtained on PMOS under 1GHz AC stress. Weibull slopes remain stable for various temperatures.
Fig. 12. Temperature dependence of TBD for PMOS stressed under DC, 1 MHz and 1GHz. The activation energy is almost constant from - 40 °C to 200 °C.
Fig. 10. Weibull distributions of PMOS under 1 MHz stress at several temperatures. Weibull slope remains constant with temperature.
b. BTI trapping A possible explanation for the AC effect is a correlation with trapping/detrapping mechanism [9]. To give insight on this possible correlation, fast AC BTI measurements have been performed under the same stress conditions that are used for TDDB AC conditions. Furthermore, the Id-Vg acquisition for VTH extraction is within 10us to limit recovery. As shown in Fig.14, unlike TDDB, no significant ΔVTH dependence on frequency is observed; proving that there is no straight correlation between the two phenomena. Besides, no trend in TBDAC/ TBDDC vs. ΔVTH plot can be evidenced over a wide range of AC TDDB conditions. Therefore, neither a contribution of defects responsible for trapping/detrapping to breakdown path formation, nor an indirect modulation of electrical field induced by VTH drift can explain AC TDDB observations. c. Local electric field fluctuations Fig. 13. Stress Induced Leakage Current (IG(t)-IG(0)) measured on NMOS vs effective stress time under DC and AC stress at VG stress = +2.6 V.
Among the different physical mechanisms proposed to explain the generation of the defects which are responsible for breakdown, 4
Microelectronics Reliability 100–101 (2019) 113422
M. Arabi, et al.
Fig. 14. Fast PBTI stress and recovery at various frequencies. No direct correlation between Vth shift and TBD is observed. Unlike TDDB, PBTI shift appears frequency independent. Fig. 16. TDDB failure distribution for standard AC stresses with two different Vlow and an AC stress with a 1 μs conditioning step at -2 V.
thermochemical model (E) has been widely discussed [10]. Interestingly, McPherson proposes a description of bond breakage mechanism directly correlated to local field [11]. In this approach, if the switching of the gate voltage during AC stress induce fluctuation of the local field within the oxide, it is likely to explain fluctuations in defect generation rate. Trying to evidence this effect, we propose to add, in the stress sequence, an additional conditioning step prior to typical AC stress stage (see Fig. 15). Its goal is to induce local electrical field fluctuations, by changing the oxide polarization, but at sufficient low voltage to prevent any additional defect creation during this stage. A pre-step of 1us at -2 V is added to a conventional AC stress at -2.8 V/1 MHz. Another configuration with a step at +2 V has also been done. Fig. 16 compares these TDDB results with those from standard AC stress. TDDB distributions at 1 MHz are the same regardless of VLow or the conditioning step. This indicates that the local electrical field fluctuations potentially induced by the conditioning steps did not change significantly the defect generation rate.
NMOS, independently of the temperature, and contributes to extend lifetime in circuit operating condition. Moreover, in this extended study with varying voltage and temperature, it is shown that there is no effect on the acceleration factor over a measured voltage range of 2.4 V to 2.6 V for NMOS and −2.5 V & -2.8 V for PMOS. On the other hand, the temperature dependence is confirmed for AC, with the same activation energy as DC. Finally, it is assumed that the effect of SILC correlates best with our study, whereas BTI and local field effects could be excluded. It can be deduced that the defect generation rate is lower or that the triggering of defect generation is delayed with increasing the frequency. Declaration of Competing Interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
5. Conclusion
Acknowledgements
To conclude, the frequency dependence is significant for PMOS &
The author would like to thank the reliability team of STMicroelectronics and CEA-Leti for their collaboration in this work.
VLow
References [1] S. Knebel, S. Kupke, U. Schroeder, S. Slesazeck, T. Mikolajick, R. Agaiby, M. Trentzsch, Influence of frequency dependent time to breakdown on high-k/metal gate reliability, IEEE Trans. Electron Devices 60 (2013) 2368–2371, https://doi. org/10.1109/TED.2013.2264104. [2] C. Chen, S. Chang, S. Chen, Y.-H. Lee, Y. Lee, D. Huang, J. Shih, K. Wu, The physical mechanism investigation of AC TDDB behavior in advanced gate stackX, Reliab. Phys. Symp. 2014 IEEE Int, IEEE, 2014, pp. 5B–5. [3] T.-Y. Yew, Y.-C. Huang, M.-H. Hsieh, W. Wang, W.-S. Chou, P.-Z. Kang, Y.-H. Lee, K. Wu, The impacts of inverter-like transitions on AC TDDB in a fast switching logic circuit, Integr. Reliab. Workshop Final Rep. IIRW 2014 IEEE Int, IEEE, 2014, pp. 47–50. [4] M. Saliva, F. Cacho, V. Huard, D. Angot, X. Federspiel, M. Durand, M. Parra, A. Bravaix, L. Anghel, New insights about oxide breakdown occurrence at circuit level, Reliab. Phys. Symp. 2014 IEEE Int. IEEE, 2014, pp. 2D–5. [5] K.T. Lee, J. Nam, M. Jin, K. Bae, J. Park, L. Hwang, J. Kim, H. Kim, J. Park, Frequency dependent TDDB behaviors and its reliability qualification in 32nm highk/metal gate CMOSFETs, Reliab. Phys. Symp. IRPS 2011 IEEE Int. IEEE, 2011, pp. 2A–3. [6] M. Rafik, A. Nguyen, X. Garros, M. Arabi, X. Federspiel, C. Diouf, AC TDDB extensive study for an enlargement of its impact and benefit on circuit lifetime assessment, Reliab. Phys. Symp. IRPS 2018 IEEE Int. IEEE, 2018, pp. 4A–3. [7] M. Arabi, X. Federspiel, F. Cacho, M. Rafik, A. Nguyen, X. Garros, G. Ghibaudo, New insights on device level TDDB at GHz speed in advanced CMOS nodes, Integr. Reliab. Workshop Final Rep. IRW 2018 IEEE Int. 2018.
Vpolarization VHigh
Fig. 15. Typical pattern applied on PMOS at “1 MHz” with a -2 V conditioning step before the conventional stress stage at VGstress = −2.8 V. The purpose of this additional step is to change the local oxide electric field, by modifying polarization in the oxide, without affecting defect generation rate. 5
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