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Temperature-dependent contact resistance of carrier selective Poly-Si on oxide junctions
Solar Energy Materials and Solar Cells 185 (2018) 425–430
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Temperature-dependent contact resistance of carrier selective Poly-Si on oxide junctions
T
⁎
N. Folcherta, , M. Rienäckera, A.A. Yeoa, B. Mina, R. Peibsta,b, R. Brendela,c a
Institute for Solar Energy Research in Hamelin, Am Ohrberg 1, 31860 Emmerthal, Germany Institute for Electronic Materials and Devices, Leibniz Universität Hannover, 30167 Hannover, Germany c Institute for Solid State Physics, Leibniz Universität Hannover, 30167 Hannover, Germany b
A R T I C LE I N FO
A B S T R A C T
Keywords: Poly-Si Passivating contacts Selective contacts Tunneling POLO Pinhole transport Contact resistance Transfer-length-method
Carrier selective junctions using a poly-silicon/ silicon oxide stack on crystalline silicon feature low recombination currents J0 whilst allowing for low contact resistivity ρC . We describe the limiting current transport mechanism as a combination of homogeneous tunneling through the interfacial silicon oxide layer and transport through pinholes where the interfacial silicon oxide layer is locally disrupted. We present an experimental method and its theoretical basis to discriminate between homogenous tunneling and local pinhole transport mechanisms on n + /n or p + /p junctions by measuring the temperature-dependent contact resistance. Theory predicts opposing trends for the temperature dependencies of tunneling and pinhole transport. This allows identifying the dominant transport path. For the contact resistance of two differently prepared poly-Si/ silicon oxide/ c-Si junctions we either find clear pinhole-type or clear tunneling-type temperature dependence. Pinhole transport contributes more than 94% to the total current for the sample with a 2.1 nm-thick interfacial silicon oxide that we anneal at a temperature of 1050 °C to achieve highest selectivity. In contrast pinhole transport contributes less than 35 % to the total current for the sample with a 1.7 nm-thick silicon oxide that we annealed at only 700 °C in order to avoid pinholes.
1. Introduction One keystone in achieving a high conversion efficiency with solar cells is to form carrier selective contacts to the light absorbing material that allow majority charge carriers to be collected at the contact without hindrance but impede the recombination of minority charge carriers. The selectivity, given as the ratio of the resistance of minority and majority charge carriers on their way to the contact [1] can be expressed as
k T S10 = log10 ⎛⎜ B ⎞⎟ q ⎝ ⋅J0⋅ρC ⎠
(1)
where ρC is the contact resistance and J0 is the dark saturation current density. The maximum efficiency that can be achieved by an otherwise ideal cell increases linearly with S10 and saturates for S10 > 15 to the maximum efficiency of Si solar cells [1]. Highest selectivities of S10 = 16.2 were realized on samples with p- and n-type poly-Si on oxide (POLO) junctions [2] and recently led to an interdigitated back contact solar cell with POLO junctions for both polarities with an independently confirmed energy conversion efficiency of 26.1% for a p-type Si wafer [3].
⁎
Corresponding author. E-mail address: [email protected] (N. Folchert).
https://doi.org/10.1016/j.solmat.2018.05.046 Received 17 March 2018; Received in revised form 22 May 2018; Accepted 23 May 2018 0927-0248/ © 2018 Elsevier B.V. All rights reserved.
Carrier selective junctions with a stack of poly-Si/SiOx/Si were modelled with tunneling transport [4] and with pinhole transport [5,6]. Both models explained the measured contact resistances and passivation qualities of the respective samples, even if the tunneling model has difficulties explaining the electrical properties of electron- and hole collecting poly-Si/SiOx/Si junctions with consistent parameters as pointed out by Peibst et al. [5]. The existence of pinholes was proven for certain samples by structural and electrical analysis after annealing at temperatures as low as 750 °C [7–10]. For other samples strong evidence for tunneling was given [11]. The dominant transport mechanism depends on the type of sample and the preparation conditions. It is possible that technologically important cases show both mechanisms simultaneously as is schematically illustrated in Fig. 1. The interfacial oxide (yellow) is broken up locally to allow pinhole currents from the wafer into the poly-Si layer and allows tunneling currents where the interfacial silicon oxide is intact. During the high temperature anneal dopants can diffuse from the poly-Si layer through the oxide into the c-Si, forming a region with increased dopant density below the oxide, schematically shown as a fading red area in Fig. 1. The dimension of this in-diffused region depends on the type of sample and the annealing conditions.
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radii in the range of 2.5–19 nm [8]. This means that the value of ρB in Eq. (3) must be understood as a weighted average of the specific resistance in a region of at maximum 30 nm below the pinhole. Insertion of the reported pinhole radii into Eq. (3) yields spreading resistances of 10 kΩ to 2 MΩ for a single pinhole as depicted in Fig. 2, assuming a specific resistance ρB of 70 mΩ cm2. This value of ρB corresponds to a donor concentration of NDop = 1.4×1017cm−3 as found for the pinhole sample presented below. The total resistance of a field of pinholes with an areal density NP is [5] Fig. 1. Sketch of the pinhole and tunneling transport as parallel conduction paths in a carrier selective POLO junction.
ρC, P (T ) =
(2)
This work develops an experimental and theoretical framework to extract the contribution of each current type to the global current through a n + /n or p + /p junction from temperature-dependent contact resistance measurements. We thereby quantify the relative significance of both mechanisms in a single sample.
Transport through pinholes is described by means of the semiclassical drift-diffusion model similar to point contacts for solar cells [12–14]. The spreading resistance ⎜
(4)
Current-voltage characteristics of semiconductor insulator metal (MIS) contacts containing a thin insulator for tunneling were studied already in the 1970s [18–21]. Following [11] we treat the highly doped and degenerate poly-Si layer as a metal-like material, enabling the application of Card and Rhoderick's well established theory of an MIS tunneling junction [19]. Four types of currents can play a role in this theory: direct band to band tunneling and tunneling via trap states for majority and minority charge carriers, respectively. We ignore minority currents due to the small minority charge carrier densities expected in our samples for measurements in the dark and under small bias voltages [22]. Note that in the case of p + -type poly-Si/ n-type c-Si or n + -type poly-Si/ p-type -c-Si POLO junctions, minority currents cannot be ignored. However we do not consider such junctions here. Ignoring minority currents leaves us with direct tunneling and trap-assisted tunneling of the respective majority carriers. We will also disregard trap-assisted tunneling because this would require the knowledge of additional parameters that we do not have access to and discuss the case of valence band tunneling only. For conduction band tunneling the same expressions apply with the according parameters. The net current of direct tunneling from the poly Si into the wafer is [19,21,23]
2.1. Pinhole contact resistance
ρB (T ) 2W ⎞ ⋅arctan ⎛ 2πrP ⎝ rP ⎠
.
2.2. Tunneling contact resistance
2. Theory
RSpread (T ) =
NP
The only temperature dependent factor in Eq. (3) is the bulk resistivity ρB . Its absolute value and temperature dependence depends on the dopant density NDop and is well parameterized [15–17]. In the doping and temperature range considered here ρB increases with increasing temperature. The pinhole density NP is a constant for each sample and can range over many orders of magnitude depending on the sample preparation [7].
We consider the global current IG through the junction to be a sum of the current through pinholes (IP ) and through a tunneling barrier (IT ) at all the sites where the oxide is intact:
IG = IP + IT
RSpread (T )
⎟
(3)
between a circular disc-shaped contact and a planar base contact was calculated in Ref. [12]. In the case of a POLO junction, we consider the resistance of a pinhole with radius rP to be that between the poly-Si/ cSi interface in the pinhole and a full area contact at distance W from the pinhole. Here, ρB is an average specific resistivity in the diffused area below the pinhole. The spreading resistance RSpread of a single pinhole generally depends on the distance W. However we find that RSpread saturates with increasing W as illustrated in Fig. 2. The characteristic distance on which this saturation occurs, only depends on the pinhole radius rP and has a maximum value of W = 30 nm for reported pinhole
qV ⎞ ⎤ ΔE JT (V ) = A* T 2PTexp ⎛− S ⎞ ⎡exp ⎛ −1 , n ⋅ kB T ⎠ ⎥ ⎝ kB T ⎠ ⎢ ⎝ ⎣ ⎦ ⎜
⎟
⎜
⎟
(5)
where A* = 4πqm*kB2/ h3 is the effective Richardson constant and
PT = exp ⎛−dox ⎝ ⎜
8mT E ⎞ ℏ2 B ⎠ ⎟
(6)
is the tunneling probability for a symmetric tunneling junction with the hole tunnel mass mT , the effective mass m* of the valence band and an ideality factor n that specifies the change of the surface potential at the oxide/ c-Si interface as a result of the applied voltage V [19]. The tunneling parameters that are shown in the schematic band diagram in Fig. 3 are the barrier height EB of the tunneling barrier, the oxide thickness dox and the difference ΔES between the valence band and the Fermi-level at the oxide/ c-Si interface at zero bias. Eq. (5) was derived using Boltzmann statistics on the wafer side of the barrier. This approximation might not be fulfilled in a poly-Si/c-Si junction with a charge carrier density NDop below the oxide so high that Fermi statistics have to be applied. The corresponding contact resistance at zero voltage is
Fig. 2. Saturation of the spreading resistance with increasing distance from the pinhole site. The specific resistance below the pinhole ρB is set to a reference value of 70 mΩ cm which reflects our pinhole sample. 426
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will therefore refer to this sample as the “pinhole sample”. We measure a dopant density of 2×1020cm−3 in the poly-Si layer using electrochemical capacitance voltage (ECV) profiling. Phosphorus atoms diffuse through the oxide into the wafer. This results in an electron concentration that decreases with depth to a value of 1×1016cm−3 at 400 nm.
3.1.2. Tunneling sample The other sample uses (for no special reason) a p-type wafer with a base resistivity of 2.5 Ω cm. It has a (1.7 ± 0.1)nm thick thermal oxide as measured by spectral ellipsometry, and receives 50 nm of amorphous Si deposited in a low-pressure chemical vapor deposition (LPCVD) furnace and a successive implantation with BF2 with a dose of 6.7×1014cm−2 at 5 keV to form a p+-type poly-Si junction. We anneal the sample at only 700 °C for 30 min which leads to a saturation current density of J0 = 6.7pA/cm2 and a selectivity of S10 = 6.4 . We consider this low temperature budget to be sufficient for the crystallization of the aSi layer but small enough to suppress massive pinhole formation. We thus expect tunneling to be dominant in this sample and will therefore refer to this sample as “tunneling sample”. We apply the same etch method as in refs. [7,9] for the determination of the density of pinholes and find etch pits with a density of (90 ± 12)cm−2 . We do not claim that all these etch pits originate from pinholes and consider this value as an upper limit for the density of pinholes in this sample. We measure a hole density of 5×1019cm−3 in the poly-Si layer by ECV profiling. Within the accuracy of ECV measurement we do not observe in-diffusion of B from the p+-type poly-Si layer into the wafer.
Fig. 3. Schematic band diagram for hole tunneling through a thin oxide barrier of a p+-type poly-Si on an oxidized p-type Si at the contact resistance measurement condition V = 0. −1
dJ n⋅kB ΔE exp ⎛ S ⎞ ρC , T = ⎛ T ⎞ = q⋅A*⋅T ⋅PT k ⎝ dV ⎠V = 0 ⎝ BT ⎠ ⎜
⎟
(7)
The major temperature dependence of the contact resistance stems from the exponential term containing ΔES which is the energy difference between the Fermi-level and the position of the valence band edge at the oxide/ c-Si interface at zero bias [19]. If this quantity was independent from temperature we would find the same temperature dependence as for a Schottky barrier except for the tunneling factor PT. Fermi level pinning could be a reason for this. Neglecting any unknown temperature dependence of ΔES we find from (7) that the resistance ρC , T decreases with increasing temperature, in contrast to the pinhole contact resistance. Eq. (7) of the MIS theory does not directly describe the current measured on samples prepared for the transfer- length method (TLM). In a TLM setup the current passes two contacts, one in forward and one in reverse direction. We therefore evaluate current-voltage curves by applying the condition
JT (V1) + JT (−V2) = 0
3.1.3. Transfer length measurement (TLM) Finally we process a TLM structure as described in Ref. [2]. Starting with an HF dip we evaporate 1 μm of Al that is then photo-lithographically structured. The poly-Si layer, any in-diffused region below the junction and layers on the back side of the sample are removed in the non-contacted regions by reactive ion etching, using the Al contacts of the TLM pattern as a mask. Fig. 4 shows a sketch of the resulting TLM sample cross-sections. The pads have a dimension of 0.1 × 3mm2 and a spacing ranging from 300 µm to 900 µm . Before measuring the sample at temperatures between 25 °C and 90 °C, we rule out thermal degradation of the junction during the measurement by heating the sample to 110 °C. We ensure that the polySi layer stays intact during the metallization process and any postmetallization annealing used here [2]. TLM measurements are performed using a Süss PA 200 Probe station with a heatable chuck. We evaluate the contact resistances using a correction for the 2-dimensional current flow pattern between two pads [24].
(8)
of equal currents through two inversely biased contacts. Here, V1 and V2 are the voltage drops across each of the tunneling junctions. Given the applied bias voltage V and the voltage drop Vbulk due to lateral current flow between the contacts we evaluate V2 as
V2 = V − Vbulk − V1.
(9)
For large contact resistances compared to the sheet resistance, Vbulk can be neglected. We find the tunneling current by inserting Eq. (9) into Eq. (8) and solving it with respect to V1. 3. Experimental details 3.1. Sample preparation and measurement We prepare one sample for which we expect dominant pinhole transport and a second sample for which we expect dominant tunneling transport. The purpose of these samples is to verify the two models explained above before applying them to samples with mixed transport. 3.1.1. Pinhole sample The sample with an n+-type poly-Si- junction uses an n-type wafer with a resistivity of 2.3 Ω cm. The poly-Si junction processing is described in detail in ref. [2]. It features a 2.1 nm-thick thermal oxide with a P-implanted poly-Si layer. The junction formation was carried out for 30 min at 1050 °C and led to saturation current densities J0 of 2.7 fA/ cm2 and a selectivity of S10 = 15. Pinhole densities of NP = 6.6×106cm−2 were reported for this sample [7]. We expect pinhole transport to dominate here due to the thick oxide and the high pinhole density and
Fig. 4. Schematic cross-section of the TLM samples showing the over-etching into the wafer to remove the in-diffused region. The red color indicates n+-type doping, green p+-type doping of the poly-Si. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.). 427
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Fig. 5. Current voltage curves across the first two Al- pads of the pinhole sample (a) and the tunneling sample (b). The distance of the pads is ~300µm . Fits (lines) to the measured data (symbols) are performed using linear regression for the pinhole sample and Eq. (8) for the tunneling sample.
uncertainty distributions, using the systematic uncertainties of our measurement (e.g. sample dimensions). The contact resistances of around 4.5 mΩ cm2 are orders of magnitude larger than the values published for the Al/poly-Si contact of 0.03 mΩ cm2 for n+-type poly-Si contact [2]. We thus identify the measured contact resistance as that of the poly-Si/c-Si junction. As expected the resistance increases with temperature. For modelling we use our measured doping profile depth W = 400 nm and the pinhole density NP = 6.6×106cm−2 as reported for that sample [7] and vary the pinhole radius rP and the dopant density NDop for a least-square fit to the experiment using Eq. (4). We take into account the incomplete ionization of dopants using the parameterization of ρB of ref. [15] and the temperature dependence of the electron mobility using Refs. [16,17]. The best fit is shown as a solid line in Fig. 6(a) and results in a dopant density of NDop = 1.4×1017cm−3 which is, as expected, in between the dopant density in the poly-Si layer and the doping density of the c-Si bulk. The pinhole radius rP of 6.4 nm is in agreement with the pinhole radii of 2.5–19 nm reported in Ref. [8]. It is therefore conclusive and consistent with previous results that this sample is dominated by pinhole transport. This is not a surprising result given the nominal oxide thickness of 2.1 nm and the reported large pinhole density.
3.2. Experimental results 3.2.1. Current-voltage analysis 3.2.1.1. Pinhole sample. Fig. 5(a) shows the measured (symbols) and calculated (lines) current-voltage curves for different temperatures between two pads with a distance of about 300 nm on the pinhole sample. The current-voltage relations are linear at all temperatures and contact distances. The ohmic behavior is expected for drift-diffusion currents. 3.2.1.2. Tunneling sample. The symbols in Fig. 5(b) show current voltage curves between the first two TLM-pads of the tunneling sample having a distance of 300 µm. The current-voltage relations are non-linear as expected from the MIS theory. We assume that the barrier height for hole tunneling is given by the difference of valence bands of bulk Si and SiO2 (4.8 eV) and that the oxide thickness dox has the same value of 1.7 nm as measured before the a-Si deposition and succeeding junction formation steps. With these values we fit Eq. (8) to the measurements, assuming a negligible lateral voltage drop Vbulk and varying the n-factor, the tunnel mass mT and ΔES . We reach a good match to the experiment with the values of n = 2.0 ± 0.2 , ΔES = (215 ± 5)meV and a tunnel mass of mT = (0.23 ± 0.01) m 0 . The given confidence intervals span the range of input parameters that lead to a normalized root mean square deviation of less than 5%. This match shows that a temperature-independent ΔES does not contradict the measurements. The coincidence of ΔES and the difference of the equilibrium Fermi-level and valence band in the wafer (which we calculate as 217 meV from the specific resistivity) implies almost flat bands at the oxide/ c-Si interface. This indicates strong charge effects at the silicon oxide/ silicon interfaces such as high fixed charge densities or Fermi level pinning. Card and Rhoderick interpret high ideality factors with high interface trap densities at the oxide/ c-Si interface [19]. Following their argumentation, our value of n = 2 implies high interface trap densities above 1×1013cm−2eV−1. High saturation current densities of 6700 fA/cm2, as determined by photo conductance decay measurements, support the interpretation of high trap densities and flat bands at the oxide/ c-Si interface. However, further investigations would be needed to obtain these properties in detail.
3.2.2.2. Tunneling sample. Fig. 6(b) shows the temperature dependence of contact resistances ρC as measured on the tunneling sample. All contact resistances have been deduced from linear regression in the range of the 4 nearest data points to V = 0 (the largest bias voltage is 44 mV for the measurement at 25 °C). We do not measure an increase of the resistance with increasing pad distance as the measured resistance is orders of magnitude larger than the resistance of the lateral transport in the wafer. From this we conclude that the lateral contribution can be neglected and derive the contact resistance from the mean value of all pads measured. The error bars originate from the standard deviation of the averaged contact resistance values and a propagation of the systematic measurement uncertainties. The contact resistances values of around 800 Ω cm2 are orders of magnitude larger than the value of 2 mΩ cm2 that was published for the Al/ p+-type poly-Si contact [2]. We therefore consider the measured contact resistance as that of the poly-Si/c-Si junction. As expected the resistance decreases with increasing temperature. We model the contact resistance using Eqs. (5)-(7) assuming the above mentioned tunnel barrier height EB = 4.8 eV and an oxide thickness of 1.7 nm. We vary the barrier ΔES and the tunnel mass mT to achieve the fit shown in Fig. 6(b) as a solid line. The tunnel mass is again 0.23m 0 and ΔES = 215meV which is in perfect agreement with the values obtained by current-voltage analysis. The tunnel mass is similar
3.2.2. Contact resistance analysis 3.2.2.1. Pinhole sample. Fig. 6(a) shows the measured temperature dependence of contact resistances ρC for the pinhole sample. All contact resistances are deduced from a linear regression over the whole voltage range of the measurement and using a correction for the 2-dimensional current flow between two pads [24]. The error bars are derived by a Monte Carlo simulation of the propagation of 428
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Fig. 6. Contact resistances obtained by TLM method for the pinhole sample annealed at 1050 °C (a) and the tunneling sample annealed at 700 °C (b). Solid lines show the best fits using the pinhole model of Eq. (4) or the MIS-model of Eq. (7) respectively.
both samples we restrict the pinhole radius to the range of 2.5–19 nm, as reported by Ref. [8]. For the pinhole sample we assume the dopant density below the pinhole as deduced above (NDop = 1.4×1017cm−3 ) and the pinhole density of NP = 6.6×106cm−2 as reported by Ref. [7]. For the tunneling sample the dopant density below the pinhole is chosen to have the value of the c-Si bulk (5.7×1015cm−3) , given the absence of indiffusion from the poly-Si layer. The pinhole density is limited to a range below the experimentally determined upper bound of 102 cm−2. We then calculate ρC (T ) -curves and their fP (300 K) and fT (300 K) using Eq. (11) for all parameter variations within these ranges using Eq. (10) and dismiss all cases that are not within the confidence ranges of the respective contact resistance measurement. This approach leaves us with a set of model parameters that are in agreement with the measurements, each having its values for fP and fT = 1– fP . We therefrom obtain the maximum pinhole and tunneling current fractions fP or fT , respectively. Note that for the pinhole sample, fP is rather limited by the accepted range of input parameters than by the confidence interval of the measurement. The result of this procedure is depicted in Fig. 7(a) for the pinhole sample and Fig. 7(b) for the tunneling sample. We find a maximum tunneling contribution fT , max in the pinhole sample of 6% and a maximum pinhole current contribution fP, max in the tunneling sample of 35%. The comparably high value of fP, max in the tunneling sample shows that for our sample it is not possible to rule out pinhole currents.
to the value of 0.25m 0 that was recently reported on another type of POLO junction [11]. 4. Combined pinhole and tunneling transport Our two samples are well described by only the pinhole model and by only the MIS-model, respectively. This was expected from the way of fabricating the samples. Knowing that Eqs. (4) and (7) describe the two extreme cases, we are now able to consider the more general case as being a superposition of both transport paths in a parallel circuit of their respective resistances. The resulting contact resistance thus is −1
1 1 ⎞ ρC (T ) = ⎜⎛ + ⎟ . ρ ( T ) ρ C , T (T ) ⎠ ⎝ C,P
(10)
The fractions of pinhole and tunneling currents to the total junction current is thus given by
fP (T ) =
ρ (T ) ρC (T ) and fT (T ) = C ρC , T (T ) ρC , P (T )
(11)
and can be obtained by comparing Eq. (10) with measurement data. Note that fP (T ) and fT (T ) are functions of temperature due to the different temperature dependences of ρC , T (T ) and ρC , P (T ) . In the following, any given numbers for fP or fT are evaluated at T = 300 K and at zero bias voltage. We now use Eq. (10) to clarify how much of the tunneling transport is present in our pinhole sample and how much pinhole transport is possible in the tunneling sample without contradicting the measurements. Here we encounter a difficulty: For a sample with a high density of pinholes the experimental extraction of tunneling parameters from the measurements is too ambiguous. The situation is the very same for a tunneling sample where the measurement sensitivity is insufficient for determining the specific resistance ρB and the pinholes radius rP . We therefore assume plausible ranges for all unknown parameters to find limits on fP and fT that are still in agreement with the measurements. The ranges we consider are as follows: The tunnel mass is varied in between the lowest value reported for SiO2, which is mT = 0.23m 0 from this work and mT = 1 as an upper limit. For the oxide thickness we use an interval of twice the standard deviation which amounts to ±0.2nm around the measured value. For the value of ΔES we only make the restriction that it is greater than zero and we use the conduction/ valence band difference of bulk Si and SiO2 (3.2eV / 4.8eV ) as the tunneling barrier height EB for the n-type and p-type case, respectively. For
5. Conclusions We demonstrated an approach for the discrimination between pinhole current and tunneling current exploiting their opposite temperature trends of the contact resistance. We show that the models for pinhole and tunneling transport are in good agreement with the contact resistance measurements of two reference samples showing predominantly tunneling and pinhole currents, respectively. Applying our approach we derive an upper limit of fT , max = 6% for tunneling in our pinhole dominated sample and an upper limit of fP, max = 35% for pinhole transport in our tunneling sample. Besides the two extreme cases measured here, we plan to also apply our method to samples with an intermediate fraction of pinhole transport, i.e., on samples with a rather thin interfacial oxide annealed at moderate temperatures.
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Fig. 7. Maximum fraction of tunneling current in the pinhole sample (a) and maximum fraction of pinhole current in the tunneling sample (b). Red dashed lines correspond to calculations assuming Eq. (11) and fP, max and fT , max as described in the text.
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We thank Guido Glowatzki, Heike Kohlenberger and Sabine Schmidt for their help with sample processing and Manuel Stratmann for the analysis of pinhole densities. We gratefully thank Tobias Wietler (ISFH) and Prof. Uwe Rau (FZ Jülich) for helpful discussions and hints. This work was supported by the Ministry for Science and Culture of lower Saxony in the framework of the project vOx and has also received funding from the European Union's Horizon 2020 research and innovation program under grant agreement No 727529 (DISC). Appendix A. Supporting information Supplementary data associated with this article can be found in the online version at http://dx.doi.org/10.1016/j.solmat.2018.05.046. References [1] R. Brendel, R. Peibst, Contact selectivity and efficiency in crystalline silicon photovoltaics, IEEE J. Photovolt. 6 (2016) 1413–1420, http://dx.doi.org/10.1109/ JPHOTOV.2016.2598267. [2] M. Rienäcker, M. Bossmeyer, A. Merkle, U. Römer, F. Haase, J. Krügener, R. Brendel, R. Peibst, Junction resistivity of carrier-selective polysilicon on oxide junctions and its impact on solar cell performance, IEEE J. Photovolt. 7 (2017) 11–18, http://dx.doi.org/10.1109/JPHOTOV.2016.2614123. [3] F. Haase, C. Klamt, S. Schäfer, A. Merkle, M. Rienäcker, J. Krügener, R. Brendel, R. Peibst, Laser contact openings for local poly-Si-metal contacts enabling 26.1%efficient POLO-IBC solar cells, Sol. Energy Mater. Sol. Cells (2018&;) (Submitted for publication). [4] H. Steinkemper, F. Feldmann, M. Bivour, M. Hermle, Theoretical investigation of carrier-selective contacts featuring tunnel oxides by means of numerical device simulation, Energy Procedia 5 (2015) 195–201, http://dx.doi.org/10.1016/j.egypro. 2015.07.027. [5] R. Peibst, U. Römer, K.R. Hofmann, B. Lim, T.F. Wietler, J. Krügener, N.-P. Harder, R. Brendel, A simple model describing the symmetric I-V characteristics of p polycrystalline Si/n monocrystalline Si, and n polycrystalline Si/p monocrystalline Si junctions, IEEE J. Photovolt. 4 (2014) 841–850, http://dx.doi.org/10.1109/ JPHOTOV.2014.2310740. [6] R. Peibst, U. Römer, Y. Larionova, M. Rienäcker, A. Merkle, N. Folchert, S. Reiter, M. Turcu, B. Min, J. Krügener, D. Tetzlaff, E. Bugiel, T. Wietler, R. Brendel, Working principle of carrier selective poly-Si/c-Si junctions: is tunnelling the whole story? Sol. Energy Mater. Sol. Cells 158 (2016) 60–67, http://dx.doi.org/10.1016/j. solmat.2016.05.045. [7] T.F. Wietler, D. Tetzlaff, J. Krügener, M. Rienäcker, F. Haase, Y. Larionova, R. Brendel, R. Peibst, Pinhole density and contact resistivity of carrier selective junctions with polycrystalline silicon on oxide, Appl. Phys. Lett. 110 (2017)
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Solar Energy Materials and Solar Cells journal homepage: www.elsevier.com/locate/solmat
Temperature-dependent contact resistance of carrier selective Poly-Si on oxide junctions
T
⁎
N. Folcherta, , M. Rienäckera, A.A. Yeoa, B. Mina, R. Peibsta,b, R. Brendela,c a
Institute for Solar Energy Research in Hamelin, Am Ohrberg 1, 31860 Emmerthal, Germany Institute for Electronic Materials and Devices, Leibniz Universität Hannover, 30167 Hannover, Germany c Institute for Solid State Physics, Leibniz Universität Hannover, 30167 Hannover, Germany b
A R T I C LE I N FO
A B S T R A C T
Keywords: Poly-Si Passivating contacts Selective contacts Tunneling POLO Pinhole transport Contact resistance Transfer-length-method
Carrier selective junctions using a poly-silicon/ silicon oxide stack on crystalline silicon feature low recombination currents J0 whilst allowing for low contact resistivity ρC . We describe the limiting current transport mechanism as a combination of homogeneous tunneling through the interfacial silicon oxide layer and transport through pinholes where the interfacial silicon oxide layer is locally disrupted. We present an experimental method and its theoretical basis to discriminate between homogenous tunneling and local pinhole transport mechanisms on n + /n or p + /p junctions by measuring the temperature-dependent contact resistance. Theory predicts opposing trends for the temperature dependencies of tunneling and pinhole transport. This allows identifying the dominant transport path. For the contact resistance of two differently prepared poly-Si/ silicon oxide/ c-Si junctions we either find clear pinhole-type or clear tunneling-type temperature dependence. Pinhole transport contributes more than 94% to the total current for the sample with a 2.1 nm-thick interfacial silicon oxide that we anneal at a temperature of 1050 °C to achieve highest selectivity. In contrast pinhole transport contributes less than 35 % to the total current for the sample with a 1.7 nm-thick silicon oxide that we annealed at only 700 °C in order to avoid pinholes.
1. Introduction One keystone in achieving a high conversion efficiency with solar cells is to form carrier selective contacts to the light absorbing material that allow majority charge carriers to be collected at the contact without hindrance but impede the recombination of minority charge carriers. The selectivity, given as the ratio of the resistance of minority and majority charge carriers on their way to the contact [1] can be expressed as
k T S10 = log10 ⎛⎜ B ⎞⎟ q ⎝ ⋅J0⋅ρC ⎠
(1)
where ρC is the contact resistance and J0 is the dark saturation current density. The maximum efficiency that can be achieved by an otherwise ideal cell increases linearly with S10 and saturates for S10 > 15 to the maximum efficiency of Si solar cells [1]. Highest selectivities of S10 = 16.2 were realized on samples with p- and n-type poly-Si on oxide (POLO) junctions [2] and recently led to an interdigitated back contact solar cell with POLO junctions for both polarities with an independently confirmed energy conversion efficiency of 26.1% for a p-type Si wafer [3].
⁎
Corresponding author. E-mail address: [email protected] (N. Folchert).
https://doi.org/10.1016/j.solmat.2018.05.046 Received 17 March 2018; Received in revised form 22 May 2018; Accepted 23 May 2018 0927-0248/ © 2018 Elsevier B.V. All rights reserved.
Carrier selective junctions with a stack of poly-Si/SiOx/Si were modelled with tunneling transport [4] and with pinhole transport [5,6]. Both models explained the measured contact resistances and passivation qualities of the respective samples, even if the tunneling model has difficulties explaining the electrical properties of electron- and hole collecting poly-Si/SiOx/Si junctions with consistent parameters as pointed out by Peibst et al. [5]. The existence of pinholes was proven for certain samples by structural and electrical analysis after annealing at temperatures as low as 750 °C [7–10]. For other samples strong evidence for tunneling was given [11]. The dominant transport mechanism depends on the type of sample and the preparation conditions. It is possible that technologically important cases show both mechanisms simultaneously as is schematically illustrated in Fig. 1. The interfacial oxide (yellow) is broken up locally to allow pinhole currents from the wafer into the poly-Si layer and allows tunneling currents where the interfacial silicon oxide is intact. During the high temperature anneal dopants can diffuse from the poly-Si layer through the oxide into the c-Si, forming a region with increased dopant density below the oxide, schematically shown as a fading red area in Fig. 1. The dimension of this in-diffused region depends on the type of sample and the annealing conditions.
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radii in the range of 2.5–19 nm [8]. This means that the value of ρB in Eq. (3) must be understood as a weighted average of the specific resistance in a region of at maximum 30 nm below the pinhole. Insertion of the reported pinhole radii into Eq. (3) yields spreading resistances of 10 kΩ to 2 MΩ for a single pinhole as depicted in Fig. 2, assuming a specific resistance ρB of 70 mΩ cm2. This value of ρB corresponds to a donor concentration of NDop = 1.4×1017cm−3 as found for the pinhole sample presented below. The total resistance of a field of pinholes with an areal density NP is [5] Fig. 1. Sketch of the pinhole and tunneling transport as parallel conduction paths in a carrier selective POLO junction.
ρC, P (T ) =
(2)
This work develops an experimental and theoretical framework to extract the contribution of each current type to the global current through a n + /n or p + /p junction from temperature-dependent contact resistance measurements. We thereby quantify the relative significance of both mechanisms in a single sample.
Transport through pinholes is described by means of the semiclassical drift-diffusion model similar to point contacts for solar cells [12–14]. The spreading resistance ⎜
(4)
Current-voltage characteristics of semiconductor insulator metal (MIS) contacts containing a thin insulator for tunneling were studied already in the 1970s [18–21]. Following [11] we treat the highly doped and degenerate poly-Si layer as a metal-like material, enabling the application of Card and Rhoderick's well established theory of an MIS tunneling junction [19]. Four types of currents can play a role in this theory: direct band to band tunneling and tunneling via trap states for majority and minority charge carriers, respectively. We ignore minority currents due to the small minority charge carrier densities expected in our samples for measurements in the dark and under small bias voltages [22]. Note that in the case of p + -type poly-Si/ n-type c-Si or n + -type poly-Si/ p-type -c-Si POLO junctions, minority currents cannot be ignored. However we do not consider such junctions here. Ignoring minority currents leaves us with direct tunneling and trap-assisted tunneling of the respective majority carriers. We will also disregard trap-assisted tunneling because this would require the knowledge of additional parameters that we do not have access to and discuss the case of valence band tunneling only. For conduction band tunneling the same expressions apply with the according parameters. The net current of direct tunneling from the poly Si into the wafer is [19,21,23]
2.1. Pinhole contact resistance
ρB (T ) 2W ⎞ ⋅arctan ⎛ 2πrP ⎝ rP ⎠
.
2.2. Tunneling contact resistance
2. Theory
RSpread (T ) =
NP
The only temperature dependent factor in Eq. (3) is the bulk resistivity ρB . Its absolute value and temperature dependence depends on the dopant density NDop and is well parameterized [15–17]. In the doping and temperature range considered here ρB increases with increasing temperature. The pinhole density NP is a constant for each sample and can range over many orders of magnitude depending on the sample preparation [7].
We consider the global current IG through the junction to be a sum of the current through pinholes (IP ) and through a tunneling barrier (IT ) at all the sites where the oxide is intact:
IG = IP + IT
RSpread (T )
⎟
(3)
between a circular disc-shaped contact and a planar base contact was calculated in Ref. [12]. In the case of a POLO junction, we consider the resistance of a pinhole with radius rP to be that between the poly-Si/ cSi interface in the pinhole and a full area contact at distance W from the pinhole. Here, ρB is an average specific resistivity in the diffused area below the pinhole. The spreading resistance RSpread of a single pinhole generally depends on the distance W. However we find that RSpread saturates with increasing W as illustrated in Fig. 2. The characteristic distance on which this saturation occurs, only depends on the pinhole radius rP and has a maximum value of W = 30 nm for reported pinhole
qV ⎞ ⎤ ΔE JT (V ) = A* T 2PTexp ⎛− S ⎞ ⎡exp ⎛ −1 , n ⋅ kB T ⎠ ⎥ ⎝ kB T ⎠ ⎢ ⎝ ⎣ ⎦ ⎜
⎟
⎜
⎟
(5)
where A* = 4πqm*kB2/ h3 is the effective Richardson constant and
PT = exp ⎛−dox ⎝ ⎜
8mT E ⎞ ℏ2 B ⎠ ⎟
(6)
is the tunneling probability for a symmetric tunneling junction with the hole tunnel mass mT , the effective mass m* of the valence band and an ideality factor n that specifies the change of the surface potential at the oxide/ c-Si interface as a result of the applied voltage V [19]. The tunneling parameters that are shown in the schematic band diagram in Fig. 3 are the barrier height EB of the tunneling barrier, the oxide thickness dox and the difference ΔES between the valence band and the Fermi-level at the oxide/ c-Si interface at zero bias. Eq. (5) was derived using Boltzmann statistics on the wafer side of the barrier. This approximation might not be fulfilled in a poly-Si/c-Si junction with a charge carrier density NDop below the oxide so high that Fermi statistics have to be applied. The corresponding contact resistance at zero voltage is
Fig. 2. Saturation of the spreading resistance with increasing distance from the pinhole site. The specific resistance below the pinhole ρB is set to a reference value of 70 mΩ cm which reflects our pinhole sample. 426
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will therefore refer to this sample as the “pinhole sample”. We measure a dopant density of 2×1020cm−3 in the poly-Si layer using electrochemical capacitance voltage (ECV) profiling. Phosphorus atoms diffuse through the oxide into the wafer. This results in an electron concentration that decreases with depth to a value of 1×1016cm−3 at 400 nm.
3.1.2. Tunneling sample The other sample uses (for no special reason) a p-type wafer with a base resistivity of 2.5 Ω cm. It has a (1.7 ± 0.1)nm thick thermal oxide as measured by spectral ellipsometry, and receives 50 nm of amorphous Si deposited in a low-pressure chemical vapor deposition (LPCVD) furnace and a successive implantation with BF2 with a dose of 6.7×1014cm−2 at 5 keV to form a p+-type poly-Si junction. We anneal the sample at only 700 °C for 30 min which leads to a saturation current density of J0 = 6.7pA/cm2 and a selectivity of S10 = 6.4 . We consider this low temperature budget to be sufficient for the crystallization of the aSi layer but small enough to suppress massive pinhole formation. We thus expect tunneling to be dominant in this sample and will therefore refer to this sample as “tunneling sample”. We apply the same etch method as in refs. [7,9] for the determination of the density of pinholes and find etch pits with a density of (90 ± 12)cm−2 . We do not claim that all these etch pits originate from pinholes and consider this value as an upper limit for the density of pinholes in this sample. We measure a hole density of 5×1019cm−3 in the poly-Si layer by ECV profiling. Within the accuracy of ECV measurement we do not observe in-diffusion of B from the p+-type poly-Si layer into the wafer.
Fig. 3. Schematic band diagram for hole tunneling through a thin oxide barrier of a p+-type poly-Si on an oxidized p-type Si at the contact resistance measurement condition V = 0. −1
dJ n⋅kB ΔE exp ⎛ S ⎞ ρC , T = ⎛ T ⎞ = q⋅A*⋅T ⋅PT k ⎝ dV ⎠V = 0 ⎝ BT ⎠ ⎜
⎟
(7)
The major temperature dependence of the contact resistance stems from the exponential term containing ΔES which is the energy difference between the Fermi-level and the position of the valence band edge at the oxide/ c-Si interface at zero bias [19]. If this quantity was independent from temperature we would find the same temperature dependence as for a Schottky barrier except for the tunneling factor PT. Fermi level pinning could be a reason for this. Neglecting any unknown temperature dependence of ΔES we find from (7) that the resistance ρC , T decreases with increasing temperature, in contrast to the pinhole contact resistance. Eq. (7) of the MIS theory does not directly describe the current measured on samples prepared for the transfer- length method (TLM). In a TLM setup the current passes two contacts, one in forward and one in reverse direction. We therefore evaluate current-voltage curves by applying the condition
JT (V1) + JT (−V2) = 0
3.1.3. Transfer length measurement (TLM) Finally we process a TLM structure as described in Ref. [2]. Starting with an HF dip we evaporate 1 μm of Al that is then photo-lithographically structured. The poly-Si layer, any in-diffused region below the junction and layers on the back side of the sample are removed in the non-contacted regions by reactive ion etching, using the Al contacts of the TLM pattern as a mask. Fig. 4 shows a sketch of the resulting TLM sample cross-sections. The pads have a dimension of 0.1 × 3mm2 and a spacing ranging from 300 µm to 900 µm . Before measuring the sample at temperatures between 25 °C and 90 °C, we rule out thermal degradation of the junction during the measurement by heating the sample to 110 °C. We ensure that the polySi layer stays intact during the metallization process and any postmetallization annealing used here [2]. TLM measurements are performed using a Süss PA 200 Probe station with a heatable chuck. We evaluate the contact resistances using a correction for the 2-dimensional current flow pattern between two pads [24].
(8)
of equal currents through two inversely biased contacts. Here, V1 and V2 are the voltage drops across each of the tunneling junctions. Given the applied bias voltage V and the voltage drop Vbulk due to lateral current flow between the contacts we evaluate V2 as
V2 = V − Vbulk − V1.
(9)
For large contact resistances compared to the sheet resistance, Vbulk can be neglected. We find the tunneling current by inserting Eq. (9) into Eq. (8) and solving it with respect to V1. 3. Experimental details 3.1. Sample preparation and measurement We prepare one sample for which we expect dominant pinhole transport and a second sample for which we expect dominant tunneling transport. The purpose of these samples is to verify the two models explained above before applying them to samples with mixed transport. 3.1.1. Pinhole sample The sample with an n+-type poly-Si- junction uses an n-type wafer with a resistivity of 2.3 Ω cm. The poly-Si junction processing is described in detail in ref. [2]. It features a 2.1 nm-thick thermal oxide with a P-implanted poly-Si layer. The junction formation was carried out for 30 min at 1050 °C and led to saturation current densities J0 of 2.7 fA/ cm2 and a selectivity of S10 = 15. Pinhole densities of NP = 6.6×106cm−2 were reported for this sample [7]. We expect pinhole transport to dominate here due to the thick oxide and the high pinhole density and
Fig. 4. Schematic cross-section of the TLM samples showing the over-etching into the wafer to remove the in-diffused region. The red color indicates n+-type doping, green p+-type doping of the poly-Si. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.). 427
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Fig. 5. Current voltage curves across the first two Al- pads of the pinhole sample (a) and the tunneling sample (b). The distance of the pads is ~300µm . Fits (lines) to the measured data (symbols) are performed using linear regression for the pinhole sample and Eq. (8) for the tunneling sample.
uncertainty distributions, using the systematic uncertainties of our measurement (e.g. sample dimensions). The contact resistances of around 4.5 mΩ cm2 are orders of magnitude larger than the values published for the Al/poly-Si contact of 0.03 mΩ cm2 for n+-type poly-Si contact [2]. We thus identify the measured contact resistance as that of the poly-Si/c-Si junction. As expected the resistance increases with temperature. For modelling we use our measured doping profile depth W = 400 nm and the pinhole density NP = 6.6×106cm−2 as reported for that sample [7] and vary the pinhole radius rP and the dopant density NDop for a least-square fit to the experiment using Eq. (4). We take into account the incomplete ionization of dopants using the parameterization of ρB of ref. [15] and the temperature dependence of the electron mobility using Refs. [16,17]. The best fit is shown as a solid line in Fig. 6(a) and results in a dopant density of NDop = 1.4×1017cm−3 which is, as expected, in between the dopant density in the poly-Si layer and the doping density of the c-Si bulk. The pinhole radius rP of 6.4 nm is in agreement with the pinhole radii of 2.5–19 nm reported in Ref. [8]. It is therefore conclusive and consistent with previous results that this sample is dominated by pinhole transport. This is not a surprising result given the nominal oxide thickness of 2.1 nm and the reported large pinhole density.
3.2. Experimental results 3.2.1. Current-voltage analysis 3.2.1.1. Pinhole sample. Fig. 5(a) shows the measured (symbols) and calculated (lines) current-voltage curves for different temperatures between two pads with a distance of about 300 nm on the pinhole sample. The current-voltage relations are linear at all temperatures and contact distances. The ohmic behavior is expected for drift-diffusion currents. 3.2.1.2. Tunneling sample. The symbols in Fig. 5(b) show current voltage curves between the first two TLM-pads of the tunneling sample having a distance of 300 µm. The current-voltage relations are non-linear as expected from the MIS theory. We assume that the barrier height for hole tunneling is given by the difference of valence bands of bulk Si and SiO2 (4.8 eV) and that the oxide thickness dox has the same value of 1.7 nm as measured before the a-Si deposition and succeeding junction formation steps. With these values we fit Eq. (8) to the measurements, assuming a negligible lateral voltage drop Vbulk and varying the n-factor, the tunnel mass mT and ΔES . We reach a good match to the experiment with the values of n = 2.0 ± 0.2 , ΔES = (215 ± 5)meV and a tunnel mass of mT = (0.23 ± 0.01) m 0 . The given confidence intervals span the range of input parameters that lead to a normalized root mean square deviation of less than 5%. This match shows that a temperature-independent ΔES does not contradict the measurements. The coincidence of ΔES and the difference of the equilibrium Fermi-level and valence band in the wafer (which we calculate as 217 meV from the specific resistivity) implies almost flat bands at the oxide/ c-Si interface. This indicates strong charge effects at the silicon oxide/ silicon interfaces such as high fixed charge densities or Fermi level pinning. Card and Rhoderick interpret high ideality factors with high interface trap densities at the oxide/ c-Si interface [19]. Following their argumentation, our value of n = 2 implies high interface trap densities above 1×1013cm−2eV−1. High saturation current densities of 6700 fA/cm2, as determined by photo conductance decay measurements, support the interpretation of high trap densities and flat bands at the oxide/ c-Si interface. However, further investigations would be needed to obtain these properties in detail.
3.2.2.2. Tunneling sample. Fig. 6(b) shows the temperature dependence of contact resistances ρC as measured on the tunneling sample. All contact resistances have been deduced from linear regression in the range of the 4 nearest data points to V = 0 (the largest bias voltage is 44 mV for the measurement at 25 °C). We do not measure an increase of the resistance with increasing pad distance as the measured resistance is orders of magnitude larger than the resistance of the lateral transport in the wafer. From this we conclude that the lateral contribution can be neglected and derive the contact resistance from the mean value of all pads measured. The error bars originate from the standard deviation of the averaged contact resistance values and a propagation of the systematic measurement uncertainties. The contact resistances values of around 800 Ω cm2 are orders of magnitude larger than the value of 2 mΩ cm2 that was published for the Al/ p+-type poly-Si contact [2]. We therefore consider the measured contact resistance as that of the poly-Si/c-Si junction. As expected the resistance decreases with increasing temperature. We model the contact resistance using Eqs. (5)-(7) assuming the above mentioned tunnel barrier height EB = 4.8 eV and an oxide thickness of 1.7 nm. We vary the barrier ΔES and the tunnel mass mT to achieve the fit shown in Fig. 6(b) as a solid line. The tunnel mass is again 0.23m 0 and ΔES = 215meV which is in perfect agreement with the values obtained by current-voltage analysis. The tunnel mass is similar
3.2.2. Contact resistance analysis 3.2.2.1. Pinhole sample. Fig. 6(a) shows the measured temperature dependence of contact resistances ρC for the pinhole sample. All contact resistances are deduced from a linear regression over the whole voltage range of the measurement and using a correction for the 2-dimensional current flow between two pads [24]. The error bars are derived by a Monte Carlo simulation of the propagation of 428
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Fig. 6. Contact resistances obtained by TLM method for the pinhole sample annealed at 1050 °C (a) and the tunneling sample annealed at 700 °C (b). Solid lines show the best fits using the pinhole model of Eq. (4) or the MIS-model of Eq. (7) respectively.
both samples we restrict the pinhole radius to the range of 2.5–19 nm, as reported by Ref. [8]. For the pinhole sample we assume the dopant density below the pinhole as deduced above (NDop = 1.4×1017cm−3 ) and the pinhole density of NP = 6.6×106cm−2 as reported by Ref. [7]. For the tunneling sample the dopant density below the pinhole is chosen to have the value of the c-Si bulk (5.7×1015cm−3) , given the absence of indiffusion from the poly-Si layer. The pinhole density is limited to a range below the experimentally determined upper bound of 102 cm−2. We then calculate ρC (T ) -curves and their fP (300 K) and fT (300 K) using Eq. (11) for all parameter variations within these ranges using Eq. (10) and dismiss all cases that are not within the confidence ranges of the respective contact resistance measurement. This approach leaves us with a set of model parameters that are in agreement with the measurements, each having its values for fP and fT = 1– fP . We therefrom obtain the maximum pinhole and tunneling current fractions fP or fT , respectively. Note that for the pinhole sample, fP is rather limited by the accepted range of input parameters than by the confidence interval of the measurement. The result of this procedure is depicted in Fig. 7(a) for the pinhole sample and Fig. 7(b) for the tunneling sample. We find a maximum tunneling contribution fT , max in the pinhole sample of 6% and a maximum pinhole current contribution fP, max in the tunneling sample of 35%. The comparably high value of fP, max in the tunneling sample shows that for our sample it is not possible to rule out pinhole currents.
to the value of 0.25m 0 that was recently reported on another type of POLO junction [11]. 4. Combined pinhole and tunneling transport Our two samples are well described by only the pinhole model and by only the MIS-model, respectively. This was expected from the way of fabricating the samples. Knowing that Eqs. (4) and (7) describe the two extreme cases, we are now able to consider the more general case as being a superposition of both transport paths in a parallel circuit of their respective resistances. The resulting contact resistance thus is −1
1 1 ⎞ ρC (T ) = ⎜⎛ + ⎟ . ρ ( T ) ρ C , T (T ) ⎠ ⎝ C,P
(10)
The fractions of pinhole and tunneling currents to the total junction current is thus given by
fP (T ) =
ρ (T ) ρC (T ) and fT (T ) = C ρC , T (T ) ρC , P (T )
(11)
and can be obtained by comparing Eq. (10) with measurement data. Note that fP (T ) and fT (T ) are functions of temperature due to the different temperature dependences of ρC , T (T ) and ρC , P (T ) . In the following, any given numbers for fP or fT are evaluated at T = 300 K and at zero bias voltage. We now use Eq. (10) to clarify how much of the tunneling transport is present in our pinhole sample and how much pinhole transport is possible in the tunneling sample without contradicting the measurements. Here we encounter a difficulty: For a sample with a high density of pinholes the experimental extraction of tunneling parameters from the measurements is too ambiguous. The situation is the very same for a tunneling sample where the measurement sensitivity is insufficient for determining the specific resistance ρB and the pinholes radius rP . We therefore assume plausible ranges for all unknown parameters to find limits on fP and fT that are still in agreement with the measurements. The ranges we consider are as follows: The tunnel mass is varied in between the lowest value reported for SiO2, which is mT = 0.23m 0 from this work and mT = 1 as an upper limit. For the oxide thickness we use an interval of twice the standard deviation which amounts to ±0.2nm around the measured value. For the value of ΔES we only make the restriction that it is greater than zero and we use the conduction/ valence band difference of bulk Si and SiO2 (3.2eV / 4.8eV ) as the tunneling barrier height EB for the n-type and p-type case, respectively. For
5. Conclusions We demonstrated an approach for the discrimination between pinhole current and tunneling current exploiting their opposite temperature trends of the contact resistance. We show that the models for pinhole and tunneling transport are in good agreement with the contact resistance measurements of two reference samples showing predominantly tunneling and pinhole currents, respectively. Applying our approach we derive an upper limit of fT , max = 6% for tunneling in our pinhole dominated sample and an upper limit of fP, max = 35% for pinhole transport in our tunneling sample. Besides the two extreme cases measured here, we plan to also apply our method to samples with an intermediate fraction of pinhole transport, i.e., on samples with a rather thin interfacial oxide annealed at moderate temperatures.
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Fig. 7. Maximum fraction of tunneling current in the pinhole sample (a) and maximum fraction of pinhole current in the tunneling sample (b). Red dashed lines correspond to calculations assuming Eq. (11) and fP, max and fT , max as described in the text.
Acknowledgements
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