- Email: [email protected]
Au–Sb structure with ZnO interface layer grown on n-Si substrate by SILAR method
Microelectronic Engineering 88 (2011) 3075–3079
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Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Temperature dependent current–voltage characteristics of the Zn/ZnO/n-Si/Au–Sb structure with ZnO interface layer grown on n-Si substrate by SILAR method M. Ali Yıldırım a,⇑, B. Güzeldir b, A. Atesß b,c, M. Sag˘lam b a
Department of Physics, Science and Art Faculty, Erzincan University, Erzincan, Turkey Department of Physics, Science Faculty, Atatürk University, Erzurum, Turkey c Department of Material Engineering, Engineering and Natural Sciences Faculty, Yıldırım Beyazıt University, Ankara, Turkey b
a r t i c l e
i n f o
Article history: Received 31 December 2010 Received in revised form 29 April 2011 Accepted 25 May 2011 Available online 31 May 2011 Keywords: ZnO SILAR Sandwich structure Interface layer Barrier inhomogeneity
a b s t r a c t This is the first time; it was employed Successive Ionic Layer Adsorption and Reaction (SILAR) method in order to prepare Zn/ZnO/n-Si/Au–Sb sandwich structure. The ZnO interface layer was directly formed on n-type Si substrate using SILAR method. The X-ray diffraction (XRD) and scanning electron microscopy (SEM) studies were showed that the film is covered well on n-type Si substrate and have polycrystalline structure. An Au–Sb electrode was used as an ohmic contact. The Zn/ZnO/n-Si/Au–Sb sandwich structure demonstrated clearly rectifying behavior by the current–voltage (I–V) curves studied at room temperature. The sample temperature effect on the current–voltage (I–V) characteristics of Zn/ZnO/n-Si/Au–Sb structure was investigated in temperature range 80–320 K by steps of 20 K. The parameters such as barrier height, ideality factor and series resistance of this structure were calculated from the forward bias I–V characteristics as a function of sample temperature. It was seen that the ideality factor and series resistance were decreased; the barrier height were increased with increasing temperature. The experimental values of barrier height and ideality factor for this device were calculated as 0.808 eV and 1.519 at 320 K; 0.220 eV and 4.961 at 80 K, respectively. These abnormal behaviors can be explained by the barrier inhomogeneities at the metal–semiconductor (M–S) interface. Ó 2011 Elsevier B.V. All rights reserved.
1. Introduction Transparent Conducting Oxides (TCOs), such as zinc oxide, cadmium oxide, indium oxide, tin oxide, etc. have widely been studied for their use in optoelectronic device technology. Due to their optical and electrical properties, TCOs are used for photovoltaic solar cells, phototransistors, liquid crystal display, optical heaters, gas sensors, transparent electrodes and other optoelectronic devices [1]. Of these TCOs, zinc oxide (ZnO) has attracted most attention for various applications such as solar cells, transparent conducting films, chemical sensors, varistors, light-emitting diodes, UV photo detectors, laser diodes [2–5], and gas sensors [6,7]. ZnO is n-type, wide direct band gap material that is sensitive to UV region. The large exciton-binding energy of 60 meV and wide band gap energy of 3.37 eV at room temperature make ZnO a promising photonic material for optoelectronic device technology [8]. It is well known that interface layer have a dominant influence on the device performance, reliability and stability. Therefore, metal-interfacial layer-semiconductor sandwich structures are of essential importance in the device modification applications of semiconductor devices. Such sandwich structures with very thin ⇑ Corresponding author. Tel.: +90 446 2243097; fax: +90 446 2243016. E-mail address: [email protected] (M. Ali Yıldırım). 0167-9317/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.05.025
interlayer behave electrically like Schottky contacts. Barrier height and ideality factor are the fundamental parameters of Schottky contact. The barrier heights of such devices depend on the nature of the interfacial layer, its thickness, and the specific metal used [9]. Analysis of the I–V characteristics of Schottky barrier diodes at room temperature does not only give detailed information about their conduction process or the nature of barrier formation at the M–S interface. The current–voltage measurements as a function of temperature [I(V,T)] are commonly used in the characterization of M–S interface [10]. All of the electrical anomalies in the Schottky barrier diodes may be attributed to the presence of Schottky barrier height inhomogeneity [11–12]. In the past, there has been no report on preparation of such structures by means of SILAR method. We report here how Zn/ZnO/n-Si/Au–Sb sandwich structure have prepared and calculated the characteristic parameters of this structure as a function of temperature. The SILAR method, introduced by Nicolau [13], is a unique method by which thin films of compound semiconductors can be deposited alternately by means of the dipping substrate into the aqueous solutions of containing ions for each component. The thickness of the film can easily be controlled by the number of growth cycles used [14,15]. In this paper, the structural and morphological properties of ZnO interface layer deposited by the SILAR method have been investigated by the XRD and SEM studies, respectively. I–V characteristics
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of Zn/ZnO/n-Si/Au–Sb sandwich structure have been measured over the temperature range of 80–320 K by steps of 20 K. 2. Experimental procedure In this study, n-type Si (100) wafer of resistivity 1–10 X-cm was used to fabricate Zn/ZnO/n-Si/Au–Sb sandwich structure (see Fig. 1). The wafer was chemically cleaned using the RCA cleaning procedure (i.e. 10 min boil in NH3 + H2O2 + 6H2O followed by a 10 min HCl + H2O2 + 6H2O at 60 °C). The native oxide on the front surface of the n-Si substrate was removed in HF:H2O (1:10) solution for 30 s and finally the wafer was rinsed in de-ionised water for 30 s and was dried. Then, low resistivity ohmic back contact to n-type Si (1 0 0) was made by evaporating Au–Sb alloy, followed by a temperature treatment at 420 °C for 3 min in N2 atmosphere. After ohmic contact made, the ohmic contact side and the edges of the n-Si semiconductor substrate was covered by wax so that the polished and cleaned front side of the sample. Aqueous zincammonia complex ions ð½ZnðNH3 Þ4 2þ Þ were chosen for the cation precursor, in which using analytical reagents of ZnCl2 and concentrated ammonia (NH3) (25–28%) were used. The concentration values defined for the zinc solution was as 0.1 M and the molar ratio of Zn:NH3 is 10:1 obtained as a result of several experiments. To deposit ZnO, one SILAR growth cycle involves the four following steps: (1) immersing the substrate in the precursor solution for 15 s to create a thin liquid film containing ½ZnðNH3 Þ4 2þ on the substrate; (2) immersing immediately the withdrawn substrates in hot water (90 °C) for 7 s to form a ZnO layer; (3) drying the substrate in the air for 60 s and (4) rinsing the substrate in a separate beaker for 30 s to remove large and loosely bonded ZnO particles. The film thickness was defined as 60 nm by repeating 25 SILAR growth cycle. Fig. 2 shows the scheme of SILAR method for the deposition of ZnO film. We made full use of the thermal decomposition of ½ZnðNH3 Þ4 2þ in a neutral aqueous solution, which released ions of Zn2+ into the solution and was resulted in the formation of ZnO or Zn(OH)2 particles. Eqs. (1)–(4) illustrate the chemical reactions related to the process.
ZnCl2 þ 2NH4 OH $ ZnðOHÞ2 þ 2NHþ4 þ 2Cl
ð1Þ
ZnðOHÞ2 þ 4NHþ4 $ ½ZnðNH3 Þ4 2þ þ 2H2 O þ 2Hþ During the reaction process in hot water, ½ZnðNH3 Þ4 decomposes and Zn(OH)2 precipitation forms:
½ZnðNH3 Þ4 2þ þ 4H2 O ! ZnðOHÞ2 ðsÞ þ 4NHþ4 þ 2OH
ZnðOHÞ2 ðsÞ ! ZnOðsÞ þ H2 O
ð4Þ
As a result, ZnO thin film was grown on glass substrate after these processes. After this process, a homogeneous thin film layer was formed over the substrate. Then, Zn dots with diameter of about 1.0 mm (the contact area = 7.85 103 cm2) were evaporated on the ZnO layer by thermal resistive heating technique. Au–Sb/n-Si and ZnO/n-Si junctions are demonstrated clearly ohmic and rectifying behavior respectively in this structure. For calculating the parameters of this structure from the I–V characteristics, diode area must be used. Thus, Zn dots are evaporated on ZnO layer for determined the diode area. All evaporation processes were carried out in a turbo molecular vacuum coating unit at about 107 torr. In this way, the Zn/ZnO/n-Si/Au–Sb sandwich structure was obtained. For structural studies, a Rigaku 2200D/Max, X-ray Diffractometer using Cu Ka (k = 1.5405 Å) radiation with 2h of 20°–70° was used. Surface morphology was studied using the Zeiss Supra 50 VP model SEM. I–V characteristics of device were measured in the temperature range of 80–320 K by using a temperature controlled Leybold Heraeus closed-cycle helium cryostat and HP4140B picoampermeter under dark conditions. 3. Results and discussion 3.1. Structural and morphological analysis The structural analysis of ZnO film was carried out by using XRD varying the diffraction angle, 2h from 20° to 70°. The XRD pattern of the ZnO film grown on n-type Si wafer is shown in Fig. 3. The XRD patterns of the film indicate the existence of a ZnO single phase with a hexagonal wurtzite structure. As seen in Fig. 3, ZnO film has polycrystalline structure with orientation along with (1 0 0), (0 0 2), (1 0 1), (1 1 0) and (1 0 3) planes [5,16]. (1 1 1) peak belongs to n-type Si wafer. It is known that the surface properties of the TCO films influence their optical and electrical properties which are important factors in applications to optoelectronic devices. Fig. 4 shows the SEM micrographs of as-deposited ZnO thin films. It is obvious from Fig. 4 that the ZnO film has a smooth and homogeneous surface morphology without holes and cracks. The film is compact, uniform, dense, smooth and well-adhered to the wafer.
ð2Þ 2þ
complex
ð3Þ
As-deposited Zn(OH)2 will transform to ZnO in an aqueous solution at temperatures over 50 °C [16]:
3.2. Current–voltage (I–V) characteristics of the Zn/ZnO/n-Si/Au–Sb sandwich structure Such metal-thin interfacial layer-semiconductor structures behave electrically like Schottky contacts. If a Schottky diode with a series resistance (Rs) is considered, it is assumed that the forward bias-thermionic emission current of the device can be expressed as [17]
I ¼ I0 exp
qðV IRs Þ qðV IRs Þ 1 exp nkT kT
ð5Þ
where I0 is the saturation current and is equal to,
qUb I0 ¼ AA T 2 exp kT
Fig. 1. The structure diagram of the fabricated device.
ð6Þ
where Ub is barrier height at zero bias, Rs is the series resistance of the neutral region and IRs is the voltage drop across the series resistance, q is the electron charge, V is the applied voltage, k is the Boltzmann constant, T is the absolute temperature, A for the rectifier contact area, A⁄ for the effective Richardson constant (A⁄ = 112 A/ cm2 K2 for n-type Si) [17], n is the ideality factor. If ideality factor n is equal to one, pure thermionic emission is occurring. However, n usually has a value greater than unity and it is determined from
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Fig. 2. Experimental scheme for the deposition of ZnO thin films.
1500
Si (111)
Intensity (arb. units)
ZnO
1200
900
(002) 600
(100)
(101) (103)
(110)
300 20
30
40
50
60
70
2 θ (degrees) Fig. 3. The XRD pattern of ZnO thin film.
The saturation current I0, deduced from the I–V data by extrapolating the curves toward V = 0, is used to obtain the zero bias barrier height Ub0 ¼ ðkT=qÞ lnðAA T 2 =I0 Þ. Fig. 5 shows the semi-logarithmic forward bias I–V characteristics of the Zn/ZnO/n-Si/Au–Sb structure in the temperature range of 80–320 K by the steps of 20 K. The experimental values of the barrier height and the ideality factor for the device were determined from intercepts and slopes of the forward-bias ln I versus V plot at each temperature, respectively. The experimental values of barrier height, ideality factor and saturation current were calculated as 0.808 eV, 1.519 and 2.77 109 A at 320 K and 0.220 eV, 4.961 and 1.17 1011 A at 80 K, respectively. These values are given in Table 1. The high values of n can be attributed to effects of the bias voltage drop across the interfacial layer and series resistance, therefore, of the bias voltage dependence of the barrier height. On the other hand, the Schottky effect, leakage current, the presence of a thin interface layer, probably an native oxide layer at ZnO and n-type Si interface, inhomogeneous Schottky barrier heights [18,19] can be the most important cause of non-ideal behavior. Several methods to extract the series resistance Rs of a device have been suggested [20,21]. In our case, in order to calculate ser1.0E-3
Zn/ZnO/n-Si/Au-Sb T=20 K
1.0E-4
1.0E-5
1.0E-6
I (A)
320 K
1.0E-7
80 K
1.0E-8
1.0E-9
Fig. 4. SEM image of ZnO thin film.
the slope of the straight-line region of the semi-log forward bias I–V characteristics through the relation,
n¼
q dV kT dðln IÞ
ð7Þ
1.0E-10 -0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V (Volts) Fig. 5. The semi-log forward bias current–voltage characteristics of Zn/ZnO/n-Si/ Au–Sb sandwich structure at various temperature.
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Table 1 The experimentally obtained from different methods n, Ub, Rs values as a function of sample temperature for the Zn/ZnO/n-Si/Au–Sb sandwich structure. Zn/ZnO/n-Si/Au–Sb
I–V method
Chung method dV/d(In I)–I
H(I)–I
Temperature (K)
n
Ub (eV)
n
Rs (X)
Ub (eV)
Rs (X)
320 300 280 260 240 220 200 180 160 140 120 100 80
1.519 1.583 1.566 1.690 1.773 2.021 2.172 2.362 2.476 3.049 3.605 4.083 4.961
0.808 0.768 0.740 0.699 0.658 0.604 0.566 0.503 0.455 0.393 0.331 0.280 0.220
1.695 1.929 1.886 1.950 2.060 2.372 2.954 3.210 3.316 3.950 4.465 4.985 –
3238.1 2669.5 2849.1 2954.7 3084.9 3148.8 3112.3 3718.9 4551.7 5976.9 6365.1 7047.2 –
0.818 0.814 0.800 0.773 0.701 0.622 0.571 0.535 0.512 0.416 0.352 0.311 –
3382.4 3060.7 3207.5 3097.5 2924.4 3437.0 4075.8 4289.3 6170.6 8110.8 8454.1 9697.8 –
ies resistance in the device with high ideality factor and series resistance, we used Cheung method developed by Cheung [20] using Eq. (5). Cheung’s functions can be written as follow:
dV kT ¼ IRs þ n dðln IÞ q
ð8Þ
kT I HðIÞ ¼ V n ln q AA T 2
ð9Þ
HðIÞ ¼ IRs þ nUb
ð10Þ
Eq. (8) should give a straight line for the data of downward curvature region in the semi-log forward bias I–V characteristics. Thus, the slope of the linear plot of the dV/d(ln I) versus I will give Rs and its y-axis intercept will give nq/kT. Using the n value determined from Eq. (8) and the data of downward curvature region in the semi-log forward bias I–V characteristics in Eq. (9), a plot of H(I) versus I according to Eq. (10) will also give a straight line with y-axis intercept equal to nUb. The plots associated with these functions are given in Figs. 6 and 7 as a function of sample temperature. The three contact parameters (n, Ub and Rs) are given in Table 1. It is seen that there is a good agreement between the values of the series resistance obtained from two Cheung plots. However, it
Fig. 7. Experimental H(I)–I curves of Zn/ZnO/n-Si/Au–Sb sandwich structure as a function of sample temperature.
can clearly be seen that there is a relatively difference between the values of the ideality factor obtained from the downward curvature region of forward bias I–V plots and from the linear regions of the same characteristics. The reason for this difference can be attributed to the existence of effects such as the series resistance and the bias dependence of the Schottky barrier height, according to the voltage drop across the interfacial layer and charge of the interface states with bias in this concave region of the I–V plot. The series resistance is an important parameter on the electrical characteristics of the rectifying contacts or junctions. This parameter is influenced by the presence of the interface layer between the metal and the semiconductor and leads to non-ideal forward bias current–voltage. The increase of series resistance with decreasing temperature is believed to result due to factors responsible for increase of n and/or lack of free carrier concentration at low temperature. The values of n and Ub parameters versus temperature are shown in Figs. 8 and 9, respectively. Both parameters exhibit strong temperature dependence. While n decreases with an increase in tempera-
5.5
5.0
Zn/ZnO/n-Si/Au-Sb
4.5
I-V Method
Ideality factor , n
4.0
Cheung Method 3.5
3.0
2.5
2.0
1.5
50
100
150
200
250
300
350
T (K) Fig. 6. Experimental dV/d(ln I)–I curves of Zn/ZnO/n-Si/Au–Sb sandwich structure as a function of sample temperature.
Fig. 8. Temperature dependence of the ideality factor for Zn/ZnO/n-Si/Au–Sb sandwich structure.
M. Ali Yıldırım et al. / Microelectronic Engineering 88 (2011) 3075–3079
morphological and electrical properties of this structure with XRD, SEM and I–V measurements, respectively. I–V measurements were carried out in the temperature range of 80–320 K by the steps of 20 K. The XRD and SEM studies were showed that the ZnO film is covered well on n-type Si substrate and have polycrystalline structure. The parameters such as barrier height, ideality factor and series resistance of this structure were calculated from the forward bias I–V characteristics as a function of sample temperature. It was seen that the ideality factor and series resistance were decreased; the barrier height were increased with increasing sample temperature. In summary, it was shown that ZnO thin film interface layer grown by means of SILAR method can be confidently used in the Zn/n-Si metal–semiconductor contacts as alternatively other very expensive and difficult methods.
0.90
0.80
Barrier Height (eV)
0.70
0.60
0.50
Zn/ZnO/n-Si/Au-Sb
0.40
I-V Method 0.30
3079
Cheung Method
Acknowledgement 0.20
We would like to acknowledge the financial support given by _ the TUBITAK Foundation, Project Nos. 107T097 and 108T500.
0.10 50
100
150
200
250
300
350
400
T (K) Fig. 9. Temperature dependence of the barrier height for Zn/ZnO/n-Si/Au–Sb sandwich structure.
ture, Ub increases, as seen from Figs. 8 and 9. Since current transport across the M–S interface is a temperature activated process, electrons at low temperatures are able to surmount the lower barriers and therefore current transport will be dominated by current flowing through the patches of lower Schottky barrier height [22]. When the temperature increases, more and more electrons have sufficient energy to surmount the higher barrier. As a result, the dominant barrier height will increase with the temperature and bias voltage. Therefore, the current flow through the lower Schottky barrier height and a larger ideality factor will dominate current transport. In the other words, more electrons have sufficient energy to overcome the higher barrier when barrier height builds up with increasing temperature and bias voltage. An apparent increase in the ideality factor and a decrease in the barrier height at low temperatures result from possibly by other effects, such as inhomogeneities of thickness and non-uniformity of the interfacial charges [23]. 4. Conclusions In this study, we prepared Zn/ZnO/n-Si/Au–Sb sandwich structure by means of SILAR method and investigated the structural,
References [1] R.K. Gupta, K. Ghosh, R. Patel, S.R. Mishra, P.K. Kahol, Mater. Lett. 62 (2008) 3373–3375. [2] W.J. Jeong, S.K. Kim, G.C. Park, Thin Solid Films 506 (2006) 180. [3] M. Mikawa, T. Moriga, Y. Sakakibara, Y. Misaki, K. Murai, I. Nakabayashi, K. Tominaga, Mater. Res. Bull. 40 (2005) 1052. [4] S. Lee, E. Shim, H. Kang, S. Pang, J. Kang, Thin Solid Films 473 (2005) 31. [5] F. Yakuphanoglu, Y. Caglar, S. Ilican, M. Caglar, Physica B 394 (2007) 86–92. [6] P. Mitra, A.P. Chatterjee, H.S. Maiti, Mater. Lett. 35 (1998) 33. [7] B.B. Rao, Mater. Chem. Phys. 64 (2000) 62. [8] S.J. Young, L.W. Ji, S.J. Chang, Y.K. Su, J. Crystal, Growth 293 (2006) 43–47. [9] W. Mönch, Semicond. Surf. Interfaces, Third edition, Springer-Verlag Press, 2001. [10] W. Mönch, J. Vac. Sci. Technol., B 17 (1999) 1867. [11] E.H. Rhoderick, R.H. Williams, Metal-Semiconductor Contacts, Clerendon Press, Oxford, 1988. [12] S. Chand, S. Bala, Appl. Surf. Sci. 252 (2005) 358. [13] Nicolau YF., Appl. Surf. Sci. 1985; 22/23:1061. [14] V.R. Shinde, C.D. Lokhande, R.S. Mane, Sung-Hwan Han, Appl. Surf. Sci. 245 (2005) 407–413. [15] A. Atesß, M. Ali Yıldırım, M. Kundakcı, A. Astam, Mater. Sci. Semicond. Process. 10 (2007) 281–286. [16] M. Ali Yıldırım, Aytunç Atesß, Opt. Commun. 283 (2010) 1370–1377. [17] S.M. Sze, Phys. Semicond. Devices, second ed., Wiley, New York, 1981. [18] A. Türüt, M. Sag˘lam, H. Efeog˘lu, N. Yalçın, M. Yıldırım, B. Abay, Physica B 205 (1905) 41. [19] M. Sag˘lam, A. Atesß, M.A. Yıldırım, B. Güzeldir, A. Astam, Curr. Appl. Phys. 10 (2010) 513–520. [20] S.K. Cheung, N.W. Cheung, Appl. Phys. Lett. 49 (1986) 85. [21] K.E. Bohlin, J. Appl. Phys. 60 (1986) 1223. [22] R.T. Tung, Phys. Rev. B 45 (1992) 1509. [23] M. Biber, Physica B 325 (2003) 138.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Temperature dependent current–voltage characteristics of the Zn/ZnO/n-Si/Au–Sb structure with ZnO interface layer grown on n-Si substrate by SILAR method M. Ali Yıldırım a,⇑, B. Güzeldir b, A. Atesß b,c, M. Sag˘lam b a
Department of Physics, Science and Art Faculty, Erzincan University, Erzincan, Turkey Department of Physics, Science Faculty, Atatürk University, Erzurum, Turkey c Department of Material Engineering, Engineering and Natural Sciences Faculty, Yıldırım Beyazıt University, Ankara, Turkey b
a r t i c l e
i n f o
Article history: Received 31 December 2010 Received in revised form 29 April 2011 Accepted 25 May 2011 Available online 31 May 2011 Keywords: ZnO SILAR Sandwich structure Interface layer Barrier inhomogeneity
a b s t r a c t This is the first time; it was employed Successive Ionic Layer Adsorption and Reaction (SILAR) method in order to prepare Zn/ZnO/n-Si/Au–Sb sandwich structure. The ZnO interface layer was directly formed on n-type Si substrate using SILAR method. The X-ray diffraction (XRD) and scanning electron microscopy (SEM) studies were showed that the film is covered well on n-type Si substrate and have polycrystalline structure. An Au–Sb electrode was used as an ohmic contact. The Zn/ZnO/n-Si/Au–Sb sandwich structure demonstrated clearly rectifying behavior by the current–voltage (I–V) curves studied at room temperature. The sample temperature effect on the current–voltage (I–V) characteristics of Zn/ZnO/n-Si/Au–Sb structure was investigated in temperature range 80–320 K by steps of 20 K. The parameters such as barrier height, ideality factor and series resistance of this structure were calculated from the forward bias I–V characteristics as a function of sample temperature. It was seen that the ideality factor and series resistance were decreased; the barrier height were increased with increasing temperature. The experimental values of barrier height and ideality factor for this device were calculated as 0.808 eV and 1.519 at 320 K; 0.220 eV and 4.961 at 80 K, respectively. These abnormal behaviors can be explained by the barrier inhomogeneities at the metal–semiconductor (M–S) interface. Ó 2011 Elsevier B.V. All rights reserved.
1. Introduction Transparent Conducting Oxides (TCOs), such as zinc oxide, cadmium oxide, indium oxide, tin oxide, etc. have widely been studied for their use in optoelectronic device technology. Due to their optical and electrical properties, TCOs are used for photovoltaic solar cells, phototransistors, liquid crystal display, optical heaters, gas sensors, transparent electrodes and other optoelectronic devices [1]. Of these TCOs, zinc oxide (ZnO) has attracted most attention for various applications such as solar cells, transparent conducting films, chemical sensors, varistors, light-emitting diodes, UV photo detectors, laser diodes [2–5], and gas sensors [6,7]. ZnO is n-type, wide direct band gap material that is sensitive to UV region. The large exciton-binding energy of 60 meV and wide band gap energy of 3.37 eV at room temperature make ZnO a promising photonic material for optoelectronic device technology [8]. It is well known that interface layer have a dominant influence on the device performance, reliability and stability. Therefore, metal-interfacial layer-semiconductor sandwich structures are of essential importance in the device modification applications of semiconductor devices. Such sandwich structures with very thin ⇑ Corresponding author. Tel.: +90 446 2243097; fax: +90 446 2243016. E-mail address: [email protected] (M. Ali Yıldırım). 0167-9317/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.05.025
interlayer behave electrically like Schottky contacts. Barrier height and ideality factor are the fundamental parameters of Schottky contact. The barrier heights of such devices depend on the nature of the interfacial layer, its thickness, and the specific metal used [9]. Analysis of the I–V characteristics of Schottky barrier diodes at room temperature does not only give detailed information about their conduction process or the nature of barrier formation at the M–S interface. The current–voltage measurements as a function of temperature [I(V,T)] are commonly used in the characterization of M–S interface [10]. All of the electrical anomalies in the Schottky barrier diodes may be attributed to the presence of Schottky barrier height inhomogeneity [11–12]. In the past, there has been no report on preparation of such structures by means of SILAR method. We report here how Zn/ZnO/n-Si/Au–Sb sandwich structure have prepared and calculated the characteristic parameters of this structure as a function of temperature. The SILAR method, introduced by Nicolau [13], is a unique method by which thin films of compound semiconductors can be deposited alternately by means of the dipping substrate into the aqueous solutions of containing ions for each component. The thickness of the film can easily be controlled by the number of growth cycles used [14,15]. In this paper, the structural and morphological properties of ZnO interface layer deposited by the SILAR method have been investigated by the XRD and SEM studies, respectively. I–V characteristics
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M. Ali Yıldırım et al. / Microelectronic Engineering 88 (2011) 3075–3079
of Zn/ZnO/n-Si/Au–Sb sandwich structure have been measured over the temperature range of 80–320 K by steps of 20 K. 2. Experimental procedure In this study, n-type Si (100) wafer of resistivity 1–10 X-cm was used to fabricate Zn/ZnO/n-Si/Au–Sb sandwich structure (see Fig. 1). The wafer was chemically cleaned using the RCA cleaning procedure (i.e. 10 min boil in NH3 + H2O2 + 6H2O followed by a 10 min HCl + H2O2 + 6H2O at 60 °C). The native oxide on the front surface of the n-Si substrate was removed in HF:H2O (1:10) solution for 30 s and finally the wafer was rinsed in de-ionised water for 30 s and was dried. Then, low resistivity ohmic back contact to n-type Si (1 0 0) was made by evaporating Au–Sb alloy, followed by a temperature treatment at 420 °C for 3 min in N2 atmosphere. After ohmic contact made, the ohmic contact side and the edges of the n-Si semiconductor substrate was covered by wax so that the polished and cleaned front side of the sample. Aqueous zincammonia complex ions ð½ZnðNH3 Þ4 2þ Þ were chosen for the cation precursor, in which using analytical reagents of ZnCl2 and concentrated ammonia (NH3) (25–28%) were used. The concentration values defined for the zinc solution was as 0.1 M and the molar ratio of Zn:NH3 is 10:1 obtained as a result of several experiments. To deposit ZnO, one SILAR growth cycle involves the four following steps: (1) immersing the substrate in the precursor solution for 15 s to create a thin liquid film containing ½ZnðNH3 Þ4 2þ on the substrate; (2) immersing immediately the withdrawn substrates in hot water (90 °C) for 7 s to form a ZnO layer; (3) drying the substrate in the air for 60 s and (4) rinsing the substrate in a separate beaker for 30 s to remove large and loosely bonded ZnO particles. The film thickness was defined as 60 nm by repeating 25 SILAR growth cycle. Fig. 2 shows the scheme of SILAR method for the deposition of ZnO film. We made full use of the thermal decomposition of ½ZnðNH3 Þ4 2þ in a neutral aqueous solution, which released ions of Zn2+ into the solution and was resulted in the formation of ZnO or Zn(OH)2 particles. Eqs. (1)–(4) illustrate the chemical reactions related to the process.
ZnCl2 þ 2NH4 OH $ ZnðOHÞ2 þ 2NHþ4 þ 2Cl
ð1Þ
ZnðOHÞ2 þ 4NHþ4 $ ½ZnðNH3 Þ4 2þ þ 2H2 O þ 2Hþ During the reaction process in hot water, ½ZnðNH3 Þ4 decomposes and Zn(OH)2 precipitation forms:
½ZnðNH3 Þ4 2þ þ 4H2 O ! ZnðOHÞ2 ðsÞ þ 4NHþ4 þ 2OH
ZnðOHÞ2 ðsÞ ! ZnOðsÞ þ H2 O
ð4Þ
As a result, ZnO thin film was grown on glass substrate after these processes. After this process, a homogeneous thin film layer was formed over the substrate. Then, Zn dots with diameter of about 1.0 mm (the contact area = 7.85 103 cm2) were evaporated on the ZnO layer by thermal resistive heating technique. Au–Sb/n-Si and ZnO/n-Si junctions are demonstrated clearly ohmic and rectifying behavior respectively in this structure. For calculating the parameters of this structure from the I–V characteristics, diode area must be used. Thus, Zn dots are evaporated on ZnO layer for determined the diode area. All evaporation processes were carried out in a turbo molecular vacuum coating unit at about 107 torr. In this way, the Zn/ZnO/n-Si/Au–Sb sandwich structure was obtained. For structural studies, a Rigaku 2200D/Max, X-ray Diffractometer using Cu Ka (k = 1.5405 Å) radiation with 2h of 20°–70° was used. Surface morphology was studied using the Zeiss Supra 50 VP model SEM. I–V characteristics of device were measured in the temperature range of 80–320 K by using a temperature controlled Leybold Heraeus closed-cycle helium cryostat and HP4140B picoampermeter under dark conditions. 3. Results and discussion 3.1. Structural and morphological analysis The structural analysis of ZnO film was carried out by using XRD varying the diffraction angle, 2h from 20° to 70°. The XRD pattern of the ZnO film grown on n-type Si wafer is shown in Fig. 3. The XRD patterns of the film indicate the existence of a ZnO single phase with a hexagonal wurtzite structure. As seen in Fig. 3, ZnO film has polycrystalline structure with orientation along with (1 0 0), (0 0 2), (1 0 1), (1 1 0) and (1 0 3) planes [5,16]. (1 1 1) peak belongs to n-type Si wafer. It is known that the surface properties of the TCO films influence their optical and electrical properties which are important factors in applications to optoelectronic devices. Fig. 4 shows the SEM micrographs of as-deposited ZnO thin films. It is obvious from Fig. 4 that the ZnO film has a smooth and homogeneous surface morphology without holes and cracks. The film is compact, uniform, dense, smooth and well-adhered to the wafer.
ð2Þ 2þ
complex
ð3Þ
As-deposited Zn(OH)2 will transform to ZnO in an aqueous solution at temperatures over 50 °C [16]:
3.2. Current–voltage (I–V) characteristics of the Zn/ZnO/n-Si/Au–Sb sandwich structure Such metal-thin interfacial layer-semiconductor structures behave electrically like Schottky contacts. If a Schottky diode with a series resistance (Rs) is considered, it is assumed that the forward bias-thermionic emission current of the device can be expressed as [17]
I ¼ I0 exp
qðV IRs Þ qðV IRs Þ 1 exp nkT kT
ð5Þ
where I0 is the saturation current and is equal to,
qUb I0 ¼ AA T 2 exp kT
Fig. 1. The structure diagram of the fabricated device.
ð6Þ
where Ub is barrier height at zero bias, Rs is the series resistance of the neutral region and IRs is the voltage drop across the series resistance, q is the electron charge, V is the applied voltage, k is the Boltzmann constant, T is the absolute temperature, A for the rectifier contact area, A⁄ for the effective Richardson constant (A⁄ = 112 A/ cm2 K2 for n-type Si) [17], n is the ideality factor. If ideality factor n is equal to one, pure thermionic emission is occurring. However, n usually has a value greater than unity and it is determined from
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Fig. 2. Experimental scheme for the deposition of ZnO thin films.
1500
Si (111)
Intensity (arb. units)
ZnO
1200
900
(002) 600
(100)
(101) (103)
(110)
300 20
30
40
50
60
70
2 θ (degrees) Fig. 3. The XRD pattern of ZnO thin film.
The saturation current I0, deduced from the I–V data by extrapolating the curves toward V = 0, is used to obtain the zero bias barrier height Ub0 ¼ ðkT=qÞ lnðAA T 2 =I0 Þ. Fig. 5 shows the semi-logarithmic forward bias I–V characteristics of the Zn/ZnO/n-Si/Au–Sb structure in the temperature range of 80–320 K by the steps of 20 K. The experimental values of the barrier height and the ideality factor for the device were determined from intercepts and slopes of the forward-bias ln I versus V plot at each temperature, respectively. The experimental values of barrier height, ideality factor and saturation current were calculated as 0.808 eV, 1.519 and 2.77 109 A at 320 K and 0.220 eV, 4.961 and 1.17 1011 A at 80 K, respectively. These values are given in Table 1. The high values of n can be attributed to effects of the bias voltage drop across the interfacial layer and series resistance, therefore, of the bias voltage dependence of the barrier height. On the other hand, the Schottky effect, leakage current, the presence of a thin interface layer, probably an native oxide layer at ZnO and n-type Si interface, inhomogeneous Schottky barrier heights [18,19] can be the most important cause of non-ideal behavior. Several methods to extract the series resistance Rs of a device have been suggested [20,21]. In our case, in order to calculate ser1.0E-3
Zn/ZnO/n-Si/Au-Sb T=20 K
1.0E-4
1.0E-5
1.0E-6
I (A)
320 K
1.0E-7
80 K
1.0E-8
1.0E-9
Fig. 4. SEM image of ZnO thin film.
the slope of the straight-line region of the semi-log forward bias I–V characteristics through the relation,
n¼
q dV kT dðln IÞ
ð7Þ
1.0E-10 -0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V (Volts) Fig. 5. The semi-log forward bias current–voltage characteristics of Zn/ZnO/n-Si/ Au–Sb sandwich structure at various temperature.
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Table 1 The experimentally obtained from different methods n, Ub, Rs values as a function of sample temperature for the Zn/ZnO/n-Si/Au–Sb sandwich structure. Zn/ZnO/n-Si/Au–Sb
I–V method
Chung method dV/d(In I)–I
H(I)–I
Temperature (K)
n
Ub (eV)
n
Rs (X)
Ub (eV)
Rs (X)
320 300 280 260 240 220 200 180 160 140 120 100 80
1.519 1.583 1.566 1.690 1.773 2.021 2.172 2.362 2.476 3.049 3.605 4.083 4.961
0.808 0.768 0.740 0.699 0.658 0.604 0.566 0.503 0.455 0.393 0.331 0.280 0.220
1.695 1.929 1.886 1.950 2.060 2.372 2.954 3.210 3.316 3.950 4.465 4.985 –
3238.1 2669.5 2849.1 2954.7 3084.9 3148.8 3112.3 3718.9 4551.7 5976.9 6365.1 7047.2 –
0.818 0.814 0.800 0.773 0.701 0.622 0.571 0.535 0.512 0.416 0.352 0.311 –
3382.4 3060.7 3207.5 3097.5 2924.4 3437.0 4075.8 4289.3 6170.6 8110.8 8454.1 9697.8 –
ies resistance in the device with high ideality factor and series resistance, we used Cheung method developed by Cheung [20] using Eq. (5). Cheung’s functions can be written as follow:
dV kT ¼ IRs þ n dðln IÞ q
ð8Þ
kT I HðIÞ ¼ V n ln q AA T 2
ð9Þ
HðIÞ ¼ IRs þ nUb
ð10Þ
Eq. (8) should give a straight line for the data of downward curvature region in the semi-log forward bias I–V characteristics. Thus, the slope of the linear plot of the dV/d(ln I) versus I will give Rs and its y-axis intercept will give nq/kT. Using the n value determined from Eq. (8) and the data of downward curvature region in the semi-log forward bias I–V characteristics in Eq. (9), a plot of H(I) versus I according to Eq. (10) will also give a straight line with y-axis intercept equal to nUb. The plots associated with these functions are given in Figs. 6 and 7 as a function of sample temperature. The three contact parameters (n, Ub and Rs) are given in Table 1. It is seen that there is a good agreement between the values of the series resistance obtained from two Cheung plots. However, it
Fig. 7. Experimental H(I)–I curves of Zn/ZnO/n-Si/Au–Sb sandwich structure as a function of sample temperature.
can clearly be seen that there is a relatively difference between the values of the ideality factor obtained from the downward curvature region of forward bias I–V plots and from the linear regions of the same characteristics. The reason for this difference can be attributed to the existence of effects such as the series resistance and the bias dependence of the Schottky barrier height, according to the voltage drop across the interfacial layer and charge of the interface states with bias in this concave region of the I–V plot. The series resistance is an important parameter on the electrical characteristics of the rectifying contacts or junctions. This parameter is influenced by the presence of the interface layer between the metal and the semiconductor and leads to non-ideal forward bias current–voltage. The increase of series resistance with decreasing temperature is believed to result due to factors responsible for increase of n and/or lack of free carrier concentration at low temperature. The values of n and Ub parameters versus temperature are shown in Figs. 8 and 9, respectively. Both parameters exhibit strong temperature dependence. While n decreases with an increase in tempera-
5.5
5.0
Zn/ZnO/n-Si/Au-Sb
4.5
I-V Method
Ideality factor , n
4.0
Cheung Method 3.5
3.0
2.5
2.0
1.5
50
100
150
200
250
300
350
T (K) Fig. 6. Experimental dV/d(ln I)–I curves of Zn/ZnO/n-Si/Au–Sb sandwich structure as a function of sample temperature.
Fig. 8. Temperature dependence of the ideality factor for Zn/ZnO/n-Si/Au–Sb sandwich structure.
M. Ali Yıldırım et al. / Microelectronic Engineering 88 (2011) 3075–3079
morphological and electrical properties of this structure with XRD, SEM and I–V measurements, respectively. I–V measurements were carried out in the temperature range of 80–320 K by the steps of 20 K. The XRD and SEM studies were showed that the ZnO film is covered well on n-type Si substrate and have polycrystalline structure. The parameters such as barrier height, ideality factor and series resistance of this structure were calculated from the forward bias I–V characteristics as a function of sample temperature. It was seen that the ideality factor and series resistance were decreased; the barrier height were increased with increasing sample temperature. In summary, it was shown that ZnO thin film interface layer grown by means of SILAR method can be confidently used in the Zn/n-Si metal–semiconductor contacts as alternatively other very expensive and difficult methods.
0.90
0.80
Barrier Height (eV)
0.70
0.60
0.50
Zn/ZnO/n-Si/Au-Sb
0.40
I-V Method 0.30
3079
Cheung Method
Acknowledgement 0.20
We would like to acknowledge the financial support given by _ the TUBITAK Foundation, Project Nos. 107T097 and 108T500.
0.10 50
100
150
200
250
300
350
400
T (K) Fig. 9. Temperature dependence of the barrier height for Zn/ZnO/n-Si/Au–Sb sandwich structure.
ture, Ub increases, as seen from Figs. 8 and 9. Since current transport across the M–S interface is a temperature activated process, electrons at low temperatures are able to surmount the lower barriers and therefore current transport will be dominated by current flowing through the patches of lower Schottky barrier height [22]. When the temperature increases, more and more electrons have sufficient energy to surmount the higher barrier. As a result, the dominant barrier height will increase with the temperature and bias voltage. Therefore, the current flow through the lower Schottky barrier height and a larger ideality factor will dominate current transport. In the other words, more electrons have sufficient energy to overcome the higher barrier when barrier height builds up with increasing temperature and bias voltage. An apparent increase in the ideality factor and a decrease in the barrier height at low temperatures result from possibly by other effects, such as inhomogeneities of thickness and non-uniformity of the interfacial charges [23]. 4. Conclusions In this study, we prepared Zn/ZnO/n-Si/Au–Sb sandwich structure by means of SILAR method and investigated the structural,
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