Test, diagnosis and fault simulation of embedded RAM modules in SRAM-based FPGAs

Microelectronic Engineering 84 (2007) 194–203 www.elsevier.com/locate/mee

Test, diagnosis and fault simulation of embedded RAM modules in SRAM-based FPGAs M.Y. Niamat a b

a,*

, D.M. Nemade b, M.M. Jamali

b

Program in Computer Science and Engineering Technology, The University of Toledo, Toledo, USA Department of Electrical Engineering and Computer Science, The University of Toledo, Toledo, USA Available online 29 March 2006

Abstract This paper presents a unique scheme for testing and locating multiple stuck at faults in the embedded RAM modules of SRAM-based FPGAs. The RAM modules are tested using the MATS++ algorithm. The interconnection scheme makes it possible to test all the cells within the RAM modules in the FPGA in just one test configuration. We also develop a diagnosis scheme capable of locating the faulty RAM cells and the CLB in which it is located. In this research, emphasis is also laid on reducing the testing time, which is achieved by partitioning the FPGA into two halves.  2006 Elsevier B.V. All rights reserved. Keywords: FPGA; Test; Structural testing; March test; MATS++; Stuck at fault; Fault diagnosis

1. Introduction A Field Programmable Gate Array (FPGA) is a generalpurpose multi-level programmable logic device [1,2]. Different types of FPGAs are available but a widely used one is the static-RAM (SRAM) based FPGA. The SRAM-based FPGA is a two dimensional array in which (m · m) Configurable Logic Blocks (CLBs) are configured to implement any user defined logic functions. These CLBs communicate by a configurable interconnection network surrounded by programmable input/output blocks. Each CLB is composed of LUT/RAM modules, which can either be configured in the LUT (Look up Table) mode or the RAM mode. Considerable research has been performed in the recent past in the area of testing FPGAs [3–14]. Some researchers have focused on testing the CLBs, while others have concentrated in testing interconnects. This paper presents an approach used to test and diagnose the embedded RAM *

Corresponding author. Tel.: +1 419 473 2663; fax: +1 419 530 3068. E-mail addresses: [email protected] (M.Y. Niamat), [email protected] (D.M. Nemade), [email protected] (M.M. Jamali). 0167-9317/$ - see front matter  2006 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2006.02.016

modules within the CLBs of SRAM based FPGAs for mainly stuck at faults. Address decoder, and transient faults are also covered. It should be noted that although testing embedded RAM modules is similar to testing classical RAM circuits using various memory testing algorithms [15–22], the complexity of the FPGA structure makes the task of testing the embedded RAM modules within it quite difficult. Earlier work in testing the LUT/ RAM modules (configured in RAM mode) for SRAM based FPGAs has been addressed in Refs. [6] and [12]. However, solution proposed in [6] is not an optimal solution as it requires N test configurations to test an N input RAM module. The solution proposed in [12] uses a pseudo shift register (PSR) interconnection scheme and the Shifted MATS++ algorithm. It is possible to test all RAM modules in an FPGA in one test configuration using this approach. Although this scheme can detect the cell faults in the RAM modules under test, it does not have the capability of locating the faulty CLB in which the RAM modules are located. In other words, the scheme assumes that the faulty CLB is known. This drawback is eliminated in the scheme presented in this paper. This paper uses a unique interconnection of CLBs in the form of a chain

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which is described later. In addition, the proposed interconnection scheme also reduces the testing time by approximately half the time taken by schemes presented in [6] and [12]. The XC4000 series FPGA [23] is used as a model for this research. The FPGA is modeled in VHDL at the equivalent gate level and the simulations results are generated using ModelSim. The rest of this paper is organized as follows: the LUT/ RAM modules are discussed in Section 2. Section 3 introduces the March algorithm used for testing the embedded RAM modules. Application of the MATS++ algorithm to test a single embedded RAM module is discussed in Section 4, while Section 5 gives the details of the interconnection scheme to test the embedded RAM modules in an FPGA. The diagnosis scheme is described in Section 6. Fault simulation results are presented in Section 7. The paper concludes with Section 8.

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process is known as configuring the FPGA and takes considerable amount of time because of its serial nature. The functional model of the LUT/RAM module is shown in Fig. 2. The model represents four different components: the control logic, the address decoder, the storage module, and the read/write logic. The address decoder is used to select the memory location for the read/write operation. The control logic issues the control signals such as WriteEnable, Enable, etc. The mode selector register bit defines the mode of operation: the LUT mode, or the RAM mode. In the LUT mode, the memory locations in the storage module store a predetermined data. This data implements some particular function of up to N variables. The write logic is disabled in this mode and hence the data can only be read out from the module. However, in the RAM mode, the write logic is enabled. 3. March tests

2. LUT/RAM modules The conceptual internal structure of a Xilinx XC4000 family CLB is shown in Fig. 1. As shown in the figure, the CLB comprises of LUT/RAM modules, the multiplexer network, the sequential output circuitry, and the configuration register [6]. Behavior of each module in the CLB is controlled by a configuration register. A configuration register is essentially a collection of programmable memory cells, which makes the FPGA reconfigurable. The black arrows (refer Fig. 1) show a serially entered bit stream, which is stored in the configuration register. This

Input

LUT/ RAM Inputs

Input

Input

G XQ

A large number of algorithms are available for testing RAM circuits [17], namely; the Zero–One [15], checkerboard [16], GALPAT [16], Walking 1/0 [16], Sliding Diagonal, and Butterfly tests. Some of these tests are based on functional fault model aimed at finding faults in the read–write logic, the memory cell array, and/or the address decoder. These test algorithms belong to a well-known family of March tests [18–20]. A March test consists of a finite sequence of March elements [20]. The March elements, in turn, can be described as a finite sequence of operations applied to every cell in memory, before proceeding to the next cell. The latter is applied in either of the two address orders: an increasing address order (from address 0 to address (n  1) indicated by an upward arrow ), or a decreasing address order (indicated by a downward arrow ). When the address order is irrelevant the double-sided arrow ( ) is used. An operation consists of writing a ‘0’ into a cell (w0), writing a ‘1’ into a cell (w1), reading a cell with expected value ‘0’ (r0), and reading a cell with expected value ‘1’ (r1) as explained in [17].

YQ Input Mux H

Mux Network

D Flip Flops and related

WriteEnable, Enable etc.

N

X

Config

Control Logic

Config

Storage Module 2N bits

Data Input

Address

Y

F

Config

Read/Write Logic Selector and other control signals

Address Decoder

Write Logic

Read Logic

Config

Configuration Register Data Output

X, Y: Combinational Outputs XQ, YQ: Sequential Outputs Config: Partial Configuration Register Fig. 1. CLB internal structure.

Mode Select Configuration Register Serial Configuration bits

Fig. 2. LUT/RAM functional model.

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Stuck at, coupling, transient, address decoder, and neighborhood pattern sensitive faults are the most common faults tested in semiconductor memories. There are many types of March tests and they target different types of faults [12]. For example, the Modified Algorithmic Test Sequence (MATS) algorithm [21] can test for all stuck at faults and some address decoder faults. MATS++ algorithm [17] is capable of detecting stuck at, address decoder, and transient faults. In this research, we use the MATS++ algorithm to detect stuck at faults (SAFs), address decoder faults, and transient faults in the embedded RAM modules. The MATS++ scheme is shown in Fig. 3. The pseudo-code for the MATS++ algorithm is shown in Fig. 4. As shown in Fig. 3, there are three March elements: M0, M1, and M2. March element M0 consists of writing a ‘0’ in each memory location in increasing address order. M1 consists of reading the memory location and writing a ‘1’ in that memory location in increasing address order. M2 consists of reading a memory location, writing a ‘0’ in that memory location, and reading the same memory location again; in decreasing address order. This test requires (6 · n) operations for an n-bit memory as there are three write operations and three read operations. One test configuration and 96 test vectors are thus required to test a 16-bit memory using the MATS++ algorithm. 4. Testing the RAM module(s) The RAM module is tested using the MATS++ algorithm as described in Section 3. Stuck at faults introduced in the memory array can be scanned and observed at the output pins of the FPGA. To test a single RAM module embedded in an FPGA, a single configuration is defined in which all the inputs and outputs are connected to the FPGA I/O pins. The inputs are controllable from the input pins and the outputs can be observed at the output pins. The F, G, and H RAM modules of each CLB are tested simultaneously in one test configuration. The WriteEnable signal, Enable signal, and Data In signal are common to all three RAM modules. In the next section, we investigate the testability of all the RAM modules in the FPGA. 5. Testing all embedded RAM modules in a FPGA One simple solution to test embedded RAM modules is to provide separate inputs and outputs to each of the RAM module. In this scheme, controllability and observability of each RAM module is ensured. However, there are not enough spare I/O pins available on the FPGA for this test scheme. Another solution to this problem is to use (m · m) test configurations, which will imply dedicated test config{

(w0); M0

(r0, w1); M1

(r1, w0, r0)} M2

Fig. 3. MATS++ scheme.

M0

M1

M2

Fig. 4. MATS++ algorithm.

urations for each CLB. This scheme also ensures controllability and observability. However, having (m · m) test configurations turns out to be too costly in terms of testing time. The aim here is to minimize the number of test configurations because re-programming the FPGA takes considerable time. Due to limited number of I/O pins, a practical solution consists in forming m one-dimensional arrays of m interconnected RAM modules. Fig. 5 shows such an interconnection with m = 4 (only one row is shown for simplicity). This solution does not require too many I/O pins. In Ref. [6], Huang et al. propose to use the output of the first module as an address input to the second module. In this proposition, full controllability and observability of every RAM module is achieved using N test configurations, i.e., one test configuration for each address bit. However, this test procedure takes considerable time. In Ref. [12], Renovell et al. propose a pseudo shift register (PSR) interconnection scheme that guarantees the full controllability and observability of all the RAM modules in the FPGA. In this scheme, the read operation works in conjunction with the write operation. To propagate the data stored at a certain memory location, it is read and then written to the same address location in the RAM of the next CLB. This process is repeated for the entire chain of CLBs. For example, consider any memory location in

Primary

Primary CLB#4

CLB#3

CLB#2

CLB#1 Output

Input

Fig. 5. One dimensional array (chain).

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the F RAM. The read ‘0’ and write ‘1’ operation (r0–w1) at this memory location is shown in Table 1. In the initial state, this memory location holds a ‘0’ in each of the four consecutive CLBs. In the final and fourth state, a 1 is written at the memory location of all the F modules. The arrows show how each CLB output is propagated after every read/write operation. After four read/write operations, all CLBs hold a ‘1’ at the memory location, successfully completing the r0–w1 operation. The read ‘1’ and write ‘0’ operation (r1–w0) is shown in Table 2. At the end of this operation, all the CLBs (F RAMs) are written with ‘0s’. It should be noted that although this scheme can test the RAM modules, it cannot locate the faulty CLB in which the RAM itself is embedded. This drawback Table 1 Read ‘0’ write ‘1’ operation

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is illustrated in Tables 3 and 4. For example, let us assume that a certain cell of the F RAM module of CLB#3 is stuck at ‘0’ (sa0). Table 3 shows the read ‘0’ and write ‘1’ operation (r0–w1) for this case. Because of this sa0 fault, all the CLBs to the right of CLB#3 will receive a ‘0’ at the corresponding memory locations. This leads to the failure of the next read ‘1’ operation as shown in Table 4. This leads to erroneous outputs (all 0s) in the read ‘1’ operation and hence it is impossible to determine which CLB is faulty. The above drawback is eliminated in the scheme presented in this work. In our scheme, the I/O pins at the top and the bottom rows of the FPGA are used as primary inputs. The I/O pins on the left and right sides of the FPGA are used as primary outputs. As there are primary outputs on both sides, the entire FPGA array is divided into two halves. Splitting the FPGA reduces the number of CLBs in a chain to half and hence the testing time is reduced. For a (m · m) FPGA, each chain has m/2 CLBs. One such chain having CLB#4, CLB#3, CLB#2, and CLB#1 is highlighted in Fig. 6. Table 4 r1–w0 operation with CLB#3 sa0

Table 2 Read ‘1’ write ‘0’ operation

PRIMARY INPUTS

4

Table 3 r0–w1 operation with CLB#3 sa0

3

2

1

P R I M A R Y

P R I M A R Y

O U T P U T S

O U T P U T S

PRIMARY INPUTS Fig. 6. FPGA partitioning.

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In the proposed scheme, the F and the G RAM modules are tested. The H module is configured in the LUT mode and implements an XOR gate. The H module is tested separately in a second test configuration. The details of the chain CLB#4–CLB#3–CLB#2–CLB#1 shown in Fig. 6 are shown in Fig. 7. In Fig. 7, each CLB receives the following primary inputs: the Clock input, 4 bit Address input, Control input WriteEnable (active low signal), Data input, Global Set Reset (GSR), etc. The GSR signal is used for setting or resetting the D flip flops in the FPGA. Each CLB has configuration inputs C1, C2, C3, and C4, which are available to the CLBs through four multiplexers (not shown in Fig. 7). Fig. 8 shows the interconnection details of four adjacent CLBs. Using the multiplexers in the CLB, input C1 is connected to the H1 input of the H LUT, Fig. 8. Input C1 of the first CLB is used as a primary input. Based on the value of G 0 (G module output), C1, and F 0 (F module output) a memory location is selected from the H LUT. The H output (H 0 ) passes through the multiplexer network (MUX N/W) and is routed appropriately to the D flip flop. The D flip flop output (YQ) is connected to the C1 input of the subsequent CLB, and so on. Tables 5 and 6 show all possible inputs to the H LUT and their corresponding outputs during a read ‘0’ and a read ‘1’ operation, respectively. To ensure proper inputs, each D flip flop is set and reset using GSR signal. Before

YQ4 CLB#3 C1

C1

1. If a fault is present in a CLB, the diagnosis algorithm tracks it down to a faulty RAM location; but not the actual RAM module (the fault is either in F or G RAM module, but cannot identify which one). This limitation is due to the fact that the H LUT is used as an interface to propagate the G and the F output. This imposes a restriction of only one output (H 0 ). Also, if both G 0 and F 0 give erroneous outputs, the fault goes undetected, which is the second limitation: 2. Faults located at the same address in F and G RAM module of the same CLB are not detected. If both G 0 and F 0 give erroneous outputs (for the same address location), the fault goes undetected. However, such an occurrence will be very rare as both are independent events. The probability of this occurring is extremely low.The H 0 signal is propagated to the next CLB as the C1 input of that CLB. Correct value of H 0 will

YQ3 CLB#2 C1

C1

CLB#4 4

C1

C1

CLB#3

YQ

YQ2 CLB#1 C1

CLB#2

YQ

4

CLB#1

YQ

4

YQ

4 Data

GSR

Write Enable

Address

Clock

GSR

Data

Write Enable

Address

Clock

Data

GSR

Write Enable

Address

Clock

Data

GSR

Write Enable

Address

Clock

YQ1_FPGA_O/P (Primary O/P)

CLB#4_C1 (Primary I/P)

a read ‘0’, all the flip flops are reset, while before a read ‘1’ operation, all the flip flops are set. Ideally, for a read ‘0’ operation, outputs G 0 and F 0 should be ‘0’. If the actual outputs are not ‘0’, it indicates the presence of a sa1 fault. Note that we cannot determine whether the F RAM module or the G RAM module is stuck at ‘1’ (sa1) by this arrangement. This gives way for the first limitation of the scheme:

Primary Inputs Fig. 7. Testing scheme.

C1 C2 C3 C4 GSR

YQ

YQ

MULTIPLEXERS

G1 G2 G3 G4

G L U T

F1 F2 F3 F4

F L U T

H L U T

CLB#4

M U X N / W

C1 C2 C3 C4 GSR

C1 C2 C3 C4 GSR

YQ MULTIPLEXERS

MULTIPLEXERS

D F F 1

G1 G2 G3 G4

G L U T

D F F 2

F1 F2 F3 F4

F L U T

H L U T

CLB#3

M U X N / W

C1 C2 C3 C4 GSR

D F F 1

G1 G2 G3 G4

G L U T

D F F 2

F1 F2 F3 F4

F L U T

H L U T

CLB#2

Fig. 8. Interconnection details.

M U X N / W

MULTIPLEXERS

D F F 1

G1 G2 G3 G4

D F F 2

F1 F2 F3 F4

G L U T

F L U T

H L U T

CLB#1

M U X N / W

D F F 1 D F F 2

YQ

M.Y. Niamat et al. / Microelectronic Engineering 84 (2007) 194–203 Table 5 Read ‘0’ operation

DataIn, WriteEnable, Enable

G0

C1

F0

H0

Fault diagnosis

0 0 1 1 0 1 0 1

0 0 0 0 1 1 1 1

0 1 0 1 0 0 1 1

0 1 1 0 1 0 0 1

No fault Fault detected (sa1) Fault detected (sa1) Fault not detected Fault detected (sa1) Fault not detected Fault not detected Fault detected (sa1)

Clock

F1 F2 F3 F4

199

PROM Address Generator

RAM Module(s ) Under Test

PROM SA1 SA0 Faulty

Table 6 Read ‘1’ Operation G0

C1

F0

H0

Fault diagnosis

1 1 0 0 1 1 0 0

1 1 1 1 0 0 0 0

1 0 1 0 1 0 1 0

1 0 0 1 0 1 1 0

No fault Fault detected (sa0) Fault detected (sa0) Fault not detected Fault detected (sa0) Fault not detected Fault not detected Fault detected (sa0)

F4

‘Z’ MUX

‘Z’ SA1 SA0

F3

‘Z’ F2

MUX

‘Z’ MUX

F1

‘Z’ Select

MUX

High Impedance. Stuck At 1. Stuck At 0

4 Faulty Address

Fig. 9. Fault diagnosis circuit.

propagate only in two cases, when there is no fault or if the fault is undetected, which is the case for the first four rows of Table 5. If there is a fault and it is detected, then it is propagated ahead as C1 as shown in the last four rows of Table 5. Now, the fault will only propagate ahead if G and F modules of this CLB are not faulty or if both of them are faulty. In all other cases it will not propagate ahead which is the final limitation: 3. Fault located at an address in a CLB is located only if there is no fault present at the same address in the next CLB in the chain. This also means that first fault in the chain that reaches the output is detected. During diagnosis, this fault can be located and marked as faulty. In subsequent testing (if needed), this location should not be considered, thus exposing inner masked faults. It is obvious that sa1 and sa0 faults at the same address location, but in different CLBs can be detected and located. The read ‘1’ operation is explained similarly. The outputs of the CLBs are scanned out in successive clock cycles. Any read operation for a four CLB chain takes 5 clock cycles (one clock cycle for application of GSR signal and four for scanning data out).

Address Generator at every clock tick. The clock is essentially the same for the PROM and the FPGA. Address (F1, F2, F3, and F4), DataIn, WriteEnable, and Enable are applied as inputs to the module under test. The RAM module(s) and the PROM outputs are compared using an XOR gate to get the Faulty signal. The Faulty signal indicates whether there is a fault in the memory location being tested. The Faulty signal is used as the select input for the four multiplexers. These multiplexers select the address (4 bit FaultyAddress) whenever the Faulty signal goes high. SA0 output indicates that a particular memory location is stuck at ‘0’ (sa0). SA1 output indicates that a particular memory location is stuck at ‘1’ (sa1). If there is any error in the output, then the error pattern enables us to locate the faulty CLB (explained in the next section). The following stuck-at faults are detected and located (with some exceptions as discussed in the limitations): • • • • •

Single fault in one LUT. Multiple faults in one LUT. Faults present in one or more LUTs of a single CLB. Faults present in one or more CLBs in a chain. Faults present in one or more chains in an FPGA.

6. Diagnosis of the output data

7. Simulation results

The data available on the primary outputs is used for diagnosis. We developed a fault diagnosis circuit which is shown in Fig. 9. The diagnosis circuit uses Programmable ROM (PROM) as the storage element. The PROM stores the expected responses in successive address locations. The consequent addresses are generated by the PROM

The functional model of the Xilinx XC 4000 series FPGA for an (8 · 8) array is implemented using VHDL at the equivalent gate level. The March test is applied on this model using MATS++ algorithm. The simulation results are presented in this section. For purpose of brevity, the simulation results for only one chain of CLBs are

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presented (refer Figs. 6 and 7). The remaining chains behave similar to the one under consideration. Signals shown in the simulation results are in accordance with Figs. 7 and 9. Initially, the simulations are done without introducing any faults. Following this, the simulations are done with stuck at faults introduced in the RAM modules. A sa0 fault is now introduced in the F module of CLB#3 at address 1000 (decimal 8) and at the same time a sa1 fault is introduced in the G module of CLB#3 at address 1011 (decimal 11). This is shown in Fig. 10 and the simulation results are shown in Fig. 11. The highlighted region (encircled by dashed lines) in Fig. 11, shows the outputs of each CLB after every clock cycle. The operation shown here is a read ‘0’ operation. All the CLBs are supposed to output a ‘0’ during the read cycle. It is seen that CLB#1 and CLB#2 are successful in outputting a ‘0’. However,

CLB#3 outputs a ‘1’ instead. This ‘1’ is propagated to CLB#1 and is observed after two clock cycles. This indicates that CLB#3 is faulty. Therefore, the Faulty signal goes high for address 1011. The signal FaultyAddress indicates the faulty location. SA1 signal indicates that the memory location is sa1. The simulation is further extended by introducing multiple faults in different CLBs under test. The faults introduced are as follows: CLB#4 Fsa0 at 0100 (decimal 4) in F module, CLB#3 Gsa0 at 0110 (decimal 6) in G module, CLB#3 Fsa1 at 1000 (decimal 8) in F module, CLB#3 Gsa1 at 1001 (decimal 9) in G module, CLB#2 Gsa1 at 1011 (decimal 11) in G module, and CLB#1 Fsa0 at 1101 (decimal 13) in F module. Fig. 12 shows the location of the inserted faults. Fig. 13(a) shows the detection and location of sa1 faults at memory address 1000, 1001, and 1011 (the FaultyAddress signal reads backwards).

Fig. 10. CLB#3 Fsa0 at 1000, Gsa1 at 1011.

Fig. 11. Fsa0 at 1000, Gsa1 at 1011.

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Fig. 12. Multiple stuck at faults in the chain.

Fig. 13(b) shows the detection and location of sa0 fault at memory address 1101 and sa1 fault at memory address 1011. Fig. 13(c) shows the detection and location of sa1

faults at memory address 1001 and 1000, while, Fig. 13(d) shows the detection and location of sa0 faults at memory address 0110 and 0100.

Fig. 13(a). Fsa1 at 1000, Gsa1 at 1001, 1011.

Fig. 13(b). Fsa0 at 1101, Gsa1 at 1011.

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Fig. 13(c). Gsa1 at 1001, Fsa1 at 1000.

Fig. 13(d). Gsa0 at 0110, Fsa0 at 0100.

8. Conclusion This paper deals with the detection and location of multiple faults in the embedded RAM modules in an FPGA. For this purpose, a unique interconnection scheme is proposed which is an enhancement over schemes discussed in [6] and [12]. This scheme also guarantees full controllability and observability of the (m · m) array of CLB modules. The MATS++ algorithm is applied to the embedded RAM modules and the simulation results are obtained. Unlike previous schemes, our diagnosis circuit is able to detect and locate the faulty CLB. It is also capable of locating the faulty memory location in the F or the G RAM module of the faulty CLB. In this scheme we also reduce the testing time by a factor of 2 by partitioning the FPGA into two halves. Detailed fault simulation using VHDL are also presented. References [1] S.D. Brown, R.J. Francis, S.G. Vranesic, Field Programmable Gate Arrays, Kluwer Academic Publishers, Dordrecht, 1992. [2] S.M. Trimberger (Ed.), Field Programmable Gate Array Technology, Kluwer Academic Publishers, Dordrecht, 1994.

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