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Testing logic arrays
182
World Abstracts on Microelectronics and Reliability
Standard cells hatch semicustom micros. RODERIC BERESFORD. Electronics, 93 (19 May 1983). Aiming single-chip systems at high-volume consumer markets, partisans of cell-based design rally at Custom 1C Conference.
Software--a critical dimension in testing LSI/VLSI chips. CHRIS CHRONES. Semiconductor Int., 72 (March 1983). The hardware features of LSI/VLSI testers are explicit, Software is still an obscure entity. Difficult to quantify, software enters into every facet of testing and impacts the tester's productivity.
Video designers move toward ICs. HOWARD BIERMAN and ERIK L. KELLER. Electronics, 112 (31 May 1983). The trend is emphasized as technical consumer-electronics conference also turns to digital TV, personal computers and batteries.
Testing logic arrays. R. WALKERand D. KING. Microelectron. J. 14 (3), 31 (1983). Designing for testability is the aim of every manufacturer of semi-custom devices. As these devices become more complex with unusually high pin counts, manufacturers must be able to test them whilst maintaining the level of quality and efficiency. This paper looks at Level Sensitive Scan Design, Scan testing and describes briefly the LDSI development system which has simplified the testing of semi-custom circuits developed by LS1.
ALU, multiplier chips zip through IEEE floating-point operations. BOB Woo, LYON LIN and ROBERT E. OWEN. Electronics, 121 (19 May 1983). Pipelined multiplier crunches 32-bit multil~lications at 5 megaflops; separate ALU chip handles addition, subtraction and normalization.
High-speed microelectronics for military applications. MARTIN C. PECKERARand ROBERT E. NEIDERT. Proc. IEEE 71 (5), 657 (1983). Future defence systems will require high-speed microcircuits for analog and digital applications. This includes digital devices which will operate with 25-MHz system clock, and contain in excess of 4 × l0 s gates/era 2. Analog devices operating as transmitters and receivers of signals up to 150 GHz will also be needed. A fundamental requirement for military systems is that they operate in hostile environments. In particular, they must survive after receiving large doses or dose transients of ionizing radiation. Micron and submicron engineering technology impacts each of these requirements. This paper describes the nature of this impact. Research and development in these technology areas at the Naval Research Laboratory is reviewed in this article.
VLSI test system grows in pin count and functionality. ALAN WHITESIDE. Electronics, 155 (31 May 1983). New pin card supports up to 256 pins and all common logic families; pattern processor mixes stored and algorithmic sources for functional checks. A practical approach to the testing of a high-volume custom linear IC. H. L. MASON. Electronics Power, 505 (June 1983). This article describes the design and construction of a small test system dedicated to the testing of a high-volume IC which was specially commissioned for use as a microphone amplifier in telephone receiver handsets. Enhanced testing of VLS1 devices. RICHARD MEREDITH. Electronics Power, 499 (June 1983). The in-circuit test technique, rather than functional testing, is in widespread use in the testing of printed-circuit-board components. This article highlights the facilities of today's in-circuit automatic test equipment with particular reference to one manufacturer's new product range.
Tomorrow's semiconductor memories. T. YAstTI. Electronics Power, 558 (July/August 1983). High speed, low power, convenient packaging and features custom tailored to engineering needs are characteristic of new electronic devices now coming onto the memory market. Charge loss in metal-nitride-oxide-semiconductor (MNOS) devices at high temperatures. C. S. DOBBS, W. D. BROWN and J. R. YEARGAN. Solid-St. Electron. 26 (5), 427 (1983). The charge loss from the nitride layer of MNOS transistors has been studied with emphasis on the temperature effects in the range of 25 to 175°C. The trend of major interest is the increase in the logarithmic decay rate of the dominant negative threshold voltage with increasing temperature. This result is believed due to a combination of three temperature related mechanisms: (1) thermal excitation (TE) discharge, (2) Poole-Frenkel emission-drift-capture events and (3) increasing nitride conductivity with increasing temperature.
A review of RAM testing methodologies. A. CORSI and C. MORANDI. Microelectron. J. 14 (2), 55 (1983). The foundations of RAM testing theory are reviewed and several test procedures designed to cover logical faults are examined in the light of experience of problems most frequently encountered. Widely used test patterns, derived on the basis of simple considerations, are analysed within the framework of the above theory. The results of this analysis, summarized in a table, provide a useful guide for the choice of the test patterns to be used for characterization or volume testing of RAM chips. 7. S E M I C O N D U C T O R
INTEGRATED
CIRCUITS,
Digital simulation of magnetic Czochralski flow under various laboratory conditions for silicon growth. WILLIAME. LANGLOIS and K~-JuN LEE. I B M J1 Res. Dev. 27 (3), 281 (1983). Previous digital simulations have suggested that an axial magnetic field in the 0.1-T (1000-Gs) range can effectively suppress convection in Czochralski growth of silicon. The present paper treats the matter more quantitatively by investigating the convection in a variety of flow conditions corresponding to typical Czochralski growth of silicon on a laboratory scale. Electrical characterization of AI-SiO2-Si (N-type) tunnel structures, influence of LPCVD and LPO2 oxide growth technologies on the properties of the Si-SiO 2 interface. G. PANANAKAKIS,G. KAMARINOSand M. EL-SAYED.Solid-St. Electron. 26 (5), 415 (1983). Metal-thin oxide-silicon tunnel diodes are studied. Two kinds of thin oxides (thickness 6 < 30,~) are examined. The first fabricated by oxidation under low oxygen pressure (LPO2) at T ~- 950°C. The second
DEVICES
AND
MATERIALS
fabricated by low pressure chemical vapour deposition (LPCVD) at T ~ 880°C. Besides, the influence of thermal annealing of these devices has been studied. (I, V), C(V,o~) and G(V,~o) experimental characteristics are analysed and compared with theoretical (I, V) curves issued from a detailed and original model. Interface states energy distribution Ns,(E), surface potential V~ vs applied voltage l,~, effective affinities Z, and Zp and oxide thickness homogeneity are deduced. The influence of pinholes is also discussed. It is worth noticing the complementarity of experimental results and the theoretical (1, V) simulation. LPCVD oxides after annealing are found to be more homogeneous and provide a lower density N~s(E) of interface states than LPO2 thin oxides.
Chemical impurities and structural imperfections in semiconductor silicon. Part II. HOWARD R. HUFF. Solid St. Teehnol., 211 (April 1983). The growth of macroscopic dislocation-free silicon crystals including the incorporation
World Abstracts on Microelectronics and Reliability
Standard cells hatch semicustom micros. RODERIC BERESFORD. Electronics, 93 (19 May 1983). Aiming single-chip systems at high-volume consumer markets, partisans of cell-based design rally at Custom 1C Conference.
Software--a critical dimension in testing LSI/VLSI chips. CHRIS CHRONES. Semiconductor Int., 72 (March 1983). The hardware features of LSI/VLSI testers are explicit, Software is still an obscure entity. Difficult to quantify, software enters into every facet of testing and impacts the tester's productivity.
Video designers move toward ICs. HOWARD BIERMAN and ERIK L. KELLER. Electronics, 112 (31 May 1983). The trend is emphasized as technical consumer-electronics conference also turns to digital TV, personal computers and batteries.
Testing logic arrays. R. WALKERand D. KING. Microelectron. J. 14 (3), 31 (1983). Designing for testability is the aim of every manufacturer of semi-custom devices. As these devices become more complex with unusually high pin counts, manufacturers must be able to test them whilst maintaining the level of quality and efficiency. This paper looks at Level Sensitive Scan Design, Scan testing and describes briefly the LDSI development system which has simplified the testing of semi-custom circuits developed by LS1.
ALU, multiplier chips zip through IEEE floating-point operations. BOB Woo, LYON LIN and ROBERT E. OWEN. Electronics, 121 (19 May 1983). Pipelined multiplier crunches 32-bit multil~lications at 5 megaflops; separate ALU chip handles addition, subtraction and normalization.
High-speed microelectronics for military applications. MARTIN C. PECKERARand ROBERT E. NEIDERT. Proc. IEEE 71 (5), 657 (1983). Future defence systems will require high-speed microcircuits for analog and digital applications. This includes digital devices which will operate with 25-MHz system clock, and contain in excess of 4 × l0 s gates/era 2. Analog devices operating as transmitters and receivers of signals up to 150 GHz will also be needed. A fundamental requirement for military systems is that they operate in hostile environments. In particular, they must survive after receiving large doses or dose transients of ionizing radiation. Micron and submicron engineering technology impacts each of these requirements. This paper describes the nature of this impact. Research and development in these technology areas at the Naval Research Laboratory is reviewed in this article.
VLSI test system grows in pin count and functionality. ALAN WHITESIDE. Electronics, 155 (31 May 1983). New pin card supports up to 256 pins and all common logic families; pattern processor mixes stored and algorithmic sources for functional checks. A practical approach to the testing of a high-volume custom linear IC. H. L. MASON. Electronics Power, 505 (June 1983). This article describes the design and construction of a small test system dedicated to the testing of a high-volume IC which was specially commissioned for use as a microphone amplifier in telephone receiver handsets. Enhanced testing of VLS1 devices. RICHARD MEREDITH. Electronics Power, 499 (June 1983). The in-circuit test technique, rather than functional testing, is in widespread use in the testing of printed-circuit-board components. This article highlights the facilities of today's in-circuit automatic test equipment with particular reference to one manufacturer's new product range.
Tomorrow's semiconductor memories. T. YAstTI. Electronics Power, 558 (July/August 1983). High speed, low power, convenient packaging and features custom tailored to engineering needs are characteristic of new electronic devices now coming onto the memory market. Charge loss in metal-nitride-oxide-semiconductor (MNOS) devices at high temperatures. C. S. DOBBS, W. D. BROWN and J. R. YEARGAN. Solid-St. Electron. 26 (5), 427 (1983). The charge loss from the nitride layer of MNOS transistors has been studied with emphasis on the temperature effects in the range of 25 to 175°C. The trend of major interest is the increase in the logarithmic decay rate of the dominant negative threshold voltage with increasing temperature. This result is believed due to a combination of three temperature related mechanisms: (1) thermal excitation (TE) discharge, (2) Poole-Frenkel emission-drift-capture events and (3) increasing nitride conductivity with increasing temperature.
A review of RAM testing methodologies. A. CORSI and C. MORANDI. Microelectron. J. 14 (2), 55 (1983). The foundations of RAM testing theory are reviewed and several test procedures designed to cover logical faults are examined in the light of experience of problems most frequently encountered. Widely used test patterns, derived on the basis of simple considerations, are analysed within the framework of the above theory. The results of this analysis, summarized in a table, provide a useful guide for the choice of the test patterns to be used for characterization or volume testing of RAM chips. 7. S E M I C O N D U C T O R
INTEGRATED
CIRCUITS,
Digital simulation of magnetic Czochralski flow under various laboratory conditions for silicon growth. WILLIAME. LANGLOIS and K~-JuN LEE. I B M J1 Res. Dev. 27 (3), 281 (1983). Previous digital simulations have suggested that an axial magnetic field in the 0.1-T (1000-Gs) range can effectively suppress convection in Czochralski growth of silicon. The present paper treats the matter more quantitatively by investigating the convection in a variety of flow conditions corresponding to typical Czochralski growth of silicon on a laboratory scale. Electrical characterization of AI-SiO2-Si (N-type) tunnel structures, influence of LPCVD and LPO2 oxide growth technologies on the properties of the Si-SiO 2 interface. G. PANANAKAKIS,G. KAMARINOSand M. EL-SAYED.Solid-St. Electron. 26 (5), 415 (1983). Metal-thin oxide-silicon tunnel diodes are studied. Two kinds of thin oxides (thickness 6 < 30,~) are examined. The first fabricated by oxidation under low oxygen pressure (LPO2) at T ~- 950°C. The second
DEVICES
AND
MATERIALS
fabricated by low pressure chemical vapour deposition (LPCVD) at T ~ 880°C. Besides, the influence of thermal annealing of these devices has been studied. (I, V), C(V,o~) and G(V,~o) experimental characteristics are analysed and compared with theoretical (I, V) curves issued from a detailed and original model. Interface states energy distribution Ns,(E), surface potential V~ vs applied voltage l,~, effective affinities Z, and Zp and oxide thickness homogeneity are deduced. The influence of pinholes is also discussed. It is worth noticing the complementarity of experimental results and the theoretical (1, V) simulation. LPCVD oxides after annealing are found to be more homogeneous and provide a lower density N~s(E) of interface states than LPO2 thin oxides.
Chemical impurities and structural imperfections in semiconductor silicon. Part II. HOWARD R. HUFF. Solid St. Teehnol., 211 (April 1983). The growth of macroscopic dislocation-free silicon crystals including the incorporation