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The 300 mm silicon wafer — a cost and technology challenge
Microelectronic Engineering 56 (2001) 3–13 www.elsevier.nl / locate / mee
The 300 mm silicon wafer — a cost and technology challenge Peter O. Hahn* Wacker Siltronic AG, P.O. Box 1140, 84479 Burghausen, Germany Abstract The conversion to 300 mm wafers is strictly cost driven. Cost, capability and timing are still the major challenges during this shaky transition phase. Looking back to 1995, industry consortia decided that the next wafer size would be 300 mm and all major Si manufacturers started to invest in costly 300 mm pilot lines. Even during the recent recession, they poured millions of dollars into the development of the first dummy, mechanical, and furnace wafers. Now 5 years later the first prime wafers with 0.18 mm design rule quality are available and the recession is over — one pilot line of a leading IC manufacturer is already running, proving the readiness of equipment and silicon — several other pilot lines and first fabs are planned in Asia, the USA and in Europe. The first silicon is scheduled for 2000 and 2001 anticipating the use of the 0.13 mm design rule at least. Besides this technological challenge, key-device manufacturers have posed a second challenge to the Si manufacturing community: price parity per square centimeter silicon at a much faster rate than in previous diameter conversions. Now that the 300 mm conversion is revitalized, the goal is to achieve the same area factor at a fraction of the historical number. To achieve these challenging cost and capability goals at the right time, Si manufacturers have to do things differently — they have to shift many paradigms, regarding cost reduction, communication and technology, which is the topic of this paper. 2001 Elsevier Science B.V. All rights reserved. Keywords: Silicon wafers
1. Introduction Similar to the laws of nature, Moore’s law — the complexity and structure density of silicon chips will double every 18 months — has an influence on everyday life. With ever decreasing costs per bit, microelectronics is steadily penetrating and revolutionizing our workplace, our homes, our cars, our leisure time, and our communications in particular. Microprocessors, memories, signal processors and the whole manifold of ICs are becoming more powerful and more versatile, smaller and cheaper, at a speed that the International Technology Roadmap for Semiconductors (Fig. 1) has a hard time to keep pace with. The road of this roadmap is paved with unspectacular black and shiny discs, called silicon wafers. Their crystalline perfection, purity and critical dimensions such as flatness are crucial enabling factors for chip making. Whenever design rules change, silicon has to be there already, providing the necessary improved properties over and above the existing leading edge wafers. Relentless and *Tel.: 1 49-8677-83-5436; fax: 1 49-8677-83-2808. E-mail address: [email protected] (P.O. Hahn). 0167-9317 / 01 / $ – see front matter PII: S0167-9317( 00 )00499-8
2001 Elsevier Science B.V. All rights reserved.
4
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
Fig. 1. ITRS roadmap / Semiconductor Industry Association (SIA) roadmap (1999).
successful efforts in technology and productivity avoid a ‘‘200 mm silicon wafer for the next design rule being twice as expensive as the current one’’.
2. Silicon diameter conversions are cost reduction driven only Despite the frequent design shrinks, new chip generations enlarge the size of a single chip. To stay in line with Moore’s law — which also means to reduce the cost per bit or logic function by 25–30% per year — the productivity engine of the semiconductor industry is fueled by four options [1]: (a) shrinking the design rule by lithography; (b) yield improvements; (c) increased equipment utilization; and (d) larger wafer diameter. Continuous cost reduction by design rule shrinking is anticipated at a rate of approximately 14%; yield improvements are expected to be rather small (about 1%) due to the already high yields in the 90% range and beyond. Equipment utilization and wafer sizes have to provide the residual substantial cost reduction needed. The increase of equipment efficiency — by optimizing the time the equipment is adding value to the wafer — is possible by enhancing the batch size of chips per wafer, or in other words to convert to the next diameter. This seems to occur about every 9 years. All the participants know the chances and the challenges [2] involved in such a diameter conversion, and the period of alpha-tools, of low yields, high depreciation and right timing becomes crucial. The total cost of the infrastructure conversion has been estimated at approximately $15B [3], which is beyond the resources of any individual organization. Therefore, two consortia (I300I, Selete) were installed to coordinate the industrial conversion to 300 mm wafers.
3. The price parity challenge Early dimensional dummy wafers came onto the market for around $1800. From there, the price decayed despite the lack of volume originally anticipated to accompany the decay. Today’s 300 mm
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
5
prime wafers are sold far below $900. Nevertheless, device manufacturers calculated that the cost of silicon would occupy an increasing percentage of the manufacturing process cost factor per square centimeter. Therefore, key IC companies posed a challenge to the silicon industry and to themselves to work together to achieve an unprecedented goal: price parity per square centimeter virgin silicon — for the same design rule generation — at a much faster rate than in previous diameter conversions in high volume production [4]. Let us look back into recent history. How did the square inch price factor for the 150 to 200 mm conversion develop with volume? The 200 / 150 mm price parity challenge is sketched generically in Fig. 2. Forty million 200 mm wafers have already been produced and so far no parity has been achieved. Volume production started in 1994. Now that the 300 mm conversion has been revitalized, it is the goal to achieve the same area factor of 1.4 at a fraction of the historical number. 1998 was the year when, for the first time, more 200 mm Si area was consumed than 150 mm. We expect an equivalence of Si area consumption between 200 and 300 mm not before 2010. Are there measures that can be taken to achieve the price parity target of 200 mm during this transition much earlier? This very challenging goal is not outrageously unrealistic. Nevertheless, a whole series of paradigm shifts and joint acceptance of higher risks are needed. It also requires a whole new degree of open cooperation between Si-wafer manufacturers, IC and equipment companies [4].
4. Cost reduction challenges
4.1. Paradigms shifted by Si manufacturers Of course, silicon manufacturers have to apply the usual productivity engine. They have to optimize yields, throughput, and cycle time. They have to reduce consumption of auxiliaries, of polysilicon and of consumables. They will increase overall equipment efficiency and capital utilization. Silicon manufacturers may enjoy the effects of economy of scale with ramping volumes. But all these efforts are not enough to reduce cost significantly faster than in previous conversions.
Fig. 2. Generic price parity challenge.
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P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
4.2. Overall cost reduction strategy The cost reduction program at some silicon suppliers was elevated to the same level in consciousness as the capability enhancement programs. It has been rigorously executed with formalized goal setting (target costing) and performance review processes (cost of ownership), making the task more efficient and effective. Open communication with customers and suppliers on the chances and limitations, the handles and their leverage, the probabilities of success and the shared actions required developed into a must. Every possibility to simplify the process flow (Fig. 3) was scrutinized. The development efforts focussed on high flexibility of the process sequence combined with the integration of innovative process steps, in particular to reduce silicon stock removal losses. Leading Si manufacturers actually defined a cost target for their wafers, anticipating a full load of their pilot line. The results of reviews of ‘performance against target (PAT)’, carried out quarterly, are shown in Fig. 4. Besides the overall target, subtargets of costs for all major steps are derived and agreed upon within the task owners. In order to exploit the maximum cost potential the following strategy is consequently pursued at some silicon manufacturers. Different technology approaches were evaluated for every process step. In slicing, for example, multi-wire slicing, ID slicing, band slicing, laser cutting, high-pressure water cutting, and pascal cutting were explored in terms of cost potential, capability and timing. At this point, breakthrough
Fig. 3. The 300 mm simplified process flow.
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
7
Fig. 4. Performance against target.
innovations were considered very carefully. Handling issues, clusterability, automation, potential for standardization, and in-line metrology capability were also under consideration. The decision was executed by a quality function deployment (QFD) procedure. It is worth mentioning that, in this way, the maximum cost reduction potential was considered and built in right from the very beginning. As a result, a flexible and innovative process flow, sketched schematically in Fig. 3, was realized. In going from 200 to 300 mm diameter manufacturing costs for the various process step groups scale differently. In some processes, time extends with the diameter, some processes have to account for the increased surface area, crystal growth with the effects of residual melt, seed and tail ends and the significantly more expensive quartz and graphite parts scale even higher than with the area factor. For a few other processes, time is independent of diameter, only the more expensive equipment matters. Also in terms of cost types percentages change characteristically. The influence of the cost of human resources decreases, depreciation and interest increase even higher. Fig. 5 lists some of the scaling elements. All these costs contribute with different weight to the total cost of manufacturing. Figs. 6 and 7 show the cost distribution for polished wafers both in terms of process steps as well as of cost types. Divisional and company overheads are not included. The effects of some of the cost reduction potentials are not included.
Fig. 5. Generic cost scaling (200 to 300 mm).
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
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Fig. 6. Cost distribution.
Fig. 7. Cost types 300 mm.
5. Communication challenges
5.1. Paradigms shifted by IC companies Shifting paradigms means an open communication on chances, opportunities, limitations and risks between customers and suppliers. Total cost minimization means an holistic approach involving all parties such as Si manufacturers, IC houses, suppliers, and consortia to drive standardization at a very early stage. Of course, the risks have to be shared between all parties. Device houses and silicon manufacturers have to sit together and tailor silicon specifications to the real needs of IC lines. Linear extrapolation from previous design rules maintains a nice safety margin, but results in overspecification and cost adders that most device houses are not even aware of. As a very cost efficient example, Dietrich [5] suggests — by widening the ITRS roadmap — using interstitial-rich wafers (slowly pulled) for monitor wafers and to work out an advanced metrology which is capable of differentiating between crystal originated defects (COPs) and particles.
6. Technological challenges Paradigm shifting means to design in cost reduction opportunities right from the beginning. Design rule wafer requirements beyond 0.1 mm are mandatory in the 300 mm era. Breakthrough innovations had to be built in right from the beginning, requiring a high degree of flexibility. The process sequence contains new or substantially modified processes such as crystal growth, multi-wire slicing, grinding and double-side polishing. Right from the beginning the capability required is comparable at least to 200 mm wafers.
6.1. Crystal pulling Economic 300 mm crystal pulling is a real challenge. The control of the melt, up to 300 kg, heat dissipation, convection, pulling speed as well as the influence of the magnetic field will be the key to a successful economic pulling process. The use of magnetic fields to control the convection and consequently steering the oxygen will be mandatory.
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
9
Fig. 8. Cost of ownership for different hot zone (HZ) puller technologies.
Auxiliaries from polysilicon to crucibles and graphite parts are very costly. Therefore, process simulations are mandatory for two reasons: cost reduction and time reduction to develop the material required — interstitial-rich (fast pull), vacancy-rich (slow pull), ring wafer (fast pull) or even perfect wafer. The yield has the overall highest impact on cost of ownership; high yields combined with large charges are the optimum. Fig. 8 depicts the influence of the theoretical yield and increasing charge sizes. Fig. 9 shows a 300 mm crystal grown with a 32 hot zone (250 kg polysilicon charge). Even the automation and handling of these crystals require new approaches.
6.2. Multi-wire slicing A brand new process, multi-wire slicing, has been developed for technical and economic reasons. This technology offers a minimum taper, bow and warpage while minimizing the kerf loss compared
Fig. 9. 300 mm crystal, 250 kg.
10
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
Fig. 10. Double-side polishing machine.
to ID slicing. Diamond-coated wire slicing, a possible breakthrough innovation, is under evaluation and offers a further cost reduction potential and can be integrated into the process flow at any time.
6.3. Grinding Grinding has replaced lapping for many reasons. The process is cleaner and fully automated, the wafers exhibit a higher flatness and less damage at comparable cost. Of course, challenges such as waviness resulting from slicing have to be solved.
6.4. Polishing New technologies, such as double-side polishing (Fig. 10), offer new opportunities for process integration. The DSP technology has already demonstrated its high flatness potential, as shown in Fig. 11, as well as high nanotopology capability. Intermediate cleaning steps can be eliminated. Double-side polishing offers the opportunity to eliminate wax mounting of wafers to a carrier. The resulting polished backside is of advantage in terms of minimized slip sensibility and particle transfer probability, but poses a series of new challenges with respect to automation, tracking and wafer handling. The smoother backsides make defects even more visible, increasing the attention of handling issues.
7. A 300 mm epi-wafer as an example of joint total cost minimization A 300 mm epitaxial wafer (0.18 mm) is already available due to a straightforward upgrade of equipment and the 200 mm process. Additional cost reductions can be achieved by a joint Si
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
11
Fig. 11. SFQR max distribution on a 300 mm wafer (site size 25 mm 3 25 mm).
manufacturer and IC house total cost minimizing product design. This will be demonstrated for the new generation of epitaxial wafers. Traditionally, epitaxial wafers are prime polished wafers, which are then topped with the epi-layer exhibiting the required properties. The substrate adds little value besides the single crystal structure information, resistivity, dimension and purity. The 300 mm epitaxial wafers can be designed more cost efficiently and achieve a cost factor over the prime polished wafer of 1.25 or even less if all opportunities are exploited (Fig. 12). The substrate has to be as inexpensive as possible. Low-cost crystal growth processes with cheaper equipment and auxiliaries can achieve this. Shifting paradigms even means considering the use of remelt. The specification of oxygen, radial oxygen variation, resistivity, and radial resistivity variation
Fig. 12. Prime wafer cost reduction potential.
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
12
has to be widened substantially. An epitaxial substrate may also be manufactured by not applying a prime polished wafer every step. Leading IC companies have demonstrated that 300 mm leading edge products can be produced without external gettering. Therefore, this step should be eliminated completely. Furthermore, the same holds for the oxide backcapping layer that prevents outdiffusion of boron in p / p 1 epitaxy. The choice of the correct resistivity window for substrate and layer eliminates this need completely. Therefore, polysilicon, backside damage and backside capping layers can be eliminated, reducing the cost of the epitaxial wafer substantially.
8. Standardization as a cost reduction driver Another important key word for accelerated cost reduction is standardization. Previous diameter conversions narrowed the variations in dimensions each time. A conscious effort is underway to emphasize this aspect even more in setting the early standards for 300 mm. This applies to silicon dimensions, to wafer identification by laser marks, to metrology and data generation, but also to aspects such as standardized wafer shippers and carriers. A world-wide consensus is needed in standardization to reduce non-value-adding costs. SEMI needs to be supported! • • • • • •
one one one one one one
standardized type and location for wafer ID laser marking; edge contour and shape; unified flatness metrology tool setup definition and site definition; flatness measurement methodology; unified LLS definition and setup for particle / etch pit discrimination; standardized backside.
9. Summary The 300 mm polished and epitaxial wafer is available in 0.18 mm quality; 0.13 mm quality is under development. With respect to technology, the challenges are manifold but no showstoppers are foreseen. The main challenge is cost reduction. Silicon is a highly engineered material in terms of dimension, purity and application-specific tailored properties. Performance is increasing, whereas costs have been decreasing continuously for years, supporting the validity of Moore’s law and enabling a revolution in communication technology. Yes, silicon can be cheaper, price parity can be reached even significantly faster than for the previous conversion! As a prerequisite we need a coherent approach from Si manufacturers, IC houses and equipment and auxiliary suppliers supported by a world-wide accepted standardization. However, the most important factor is the economy of scale! We have to overcome the chicken and the egg dilemma because a smooth and steady transition to volume production is needed first. The availability of the material and the equipment as well as the feasibility of the 300 mm processes has already been demonstrated by the readiness and shipment of the first 64 MDRAM devices.
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The analysts forecast an average growth of 15% per year. Silicon is the fuel for the communication age and will keep us in line with Moore’s law. Globalization has just started and is not imaginable without silicon, and the 300 mm generation will become the workhorse during the first century of the new millennium! References [1] H.R. Huff, R.K. Goodall, R.H. Nilson, K. Griffiths, in: Symposium Proceedings ULSI / 97, 191st Meeting ECS, May 4–9, 1997. [2] P.O. Hahn, H.G. Fußstetter, Productronica 95, Munich Proceedings in Semiconductor Equipment and Materials Beyond JESSI — 300 mm and Single Wafer Processing. [3] Dataquest, May 22, 1995, The move toward 300 mm wafers: the issues surrounding — when and how — money will talk. [4] P.O. Hahn, H.G. Fußstetter, Future Fab International, vol. 9, pp. 183–187. [5] H. Dietrich, F. Bialas, N. Caspary, in: SEMI 2000 European IEEE / SEMI Semiconductor Manufacturing Conference, Munich, 2000.
The 300 mm silicon wafer — a cost and technology challenge Peter O. Hahn* Wacker Siltronic AG, P.O. Box 1140, 84479 Burghausen, Germany Abstract The conversion to 300 mm wafers is strictly cost driven. Cost, capability and timing are still the major challenges during this shaky transition phase. Looking back to 1995, industry consortia decided that the next wafer size would be 300 mm and all major Si manufacturers started to invest in costly 300 mm pilot lines. Even during the recent recession, they poured millions of dollars into the development of the first dummy, mechanical, and furnace wafers. Now 5 years later the first prime wafers with 0.18 mm design rule quality are available and the recession is over — one pilot line of a leading IC manufacturer is already running, proving the readiness of equipment and silicon — several other pilot lines and first fabs are planned in Asia, the USA and in Europe. The first silicon is scheduled for 2000 and 2001 anticipating the use of the 0.13 mm design rule at least. Besides this technological challenge, key-device manufacturers have posed a second challenge to the Si manufacturing community: price parity per square centimeter silicon at a much faster rate than in previous diameter conversions. Now that the 300 mm conversion is revitalized, the goal is to achieve the same area factor at a fraction of the historical number. To achieve these challenging cost and capability goals at the right time, Si manufacturers have to do things differently — they have to shift many paradigms, regarding cost reduction, communication and technology, which is the topic of this paper. 2001 Elsevier Science B.V. All rights reserved. Keywords: Silicon wafers
1. Introduction Similar to the laws of nature, Moore’s law — the complexity and structure density of silicon chips will double every 18 months — has an influence on everyday life. With ever decreasing costs per bit, microelectronics is steadily penetrating and revolutionizing our workplace, our homes, our cars, our leisure time, and our communications in particular. Microprocessors, memories, signal processors and the whole manifold of ICs are becoming more powerful and more versatile, smaller and cheaper, at a speed that the International Technology Roadmap for Semiconductors (Fig. 1) has a hard time to keep pace with. The road of this roadmap is paved with unspectacular black and shiny discs, called silicon wafers. Their crystalline perfection, purity and critical dimensions such as flatness are crucial enabling factors for chip making. Whenever design rules change, silicon has to be there already, providing the necessary improved properties over and above the existing leading edge wafers. Relentless and *Tel.: 1 49-8677-83-5436; fax: 1 49-8677-83-2808. E-mail address: [email protected] (P.O. Hahn). 0167-9317 / 01 / $ – see front matter PII: S0167-9317( 00 )00499-8
2001 Elsevier Science B.V. All rights reserved.
4
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
Fig. 1. ITRS roadmap / Semiconductor Industry Association (SIA) roadmap (1999).
successful efforts in technology and productivity avoid a ‘‘200 mm silicon wafer for the next design rule being twice as expensive as the current one’’.
2. Silicon diameter conversions are cost reduction driven only Despite the frequent design shrinks, new chip generations enlarge the size of a single chip. To stay in line with Moore’s law — which also means to reduce the cost per bit or logic function by 25–30% per year — the productivity engine of the semiconductor industry is fueled by four options [1]: (a) shrinking the design rule by lithography; (b) yield improvements; (c) increased equipment utilization; and (d) larger wafer diameter. Continuous cost reduction by design rule shrinking is anticipated at a rate of approximately 14%; yield improvements are expected to be rather small (about 1%) due to the already high yields in the 90% range and beyond. Equipment utilization and wafer sizes have to provide the residual substantial cost reduction needed. The increase of equipment efficiency — by optimizing the time the equipment is adding value to the wafer — is possible by enhancing the batch size of chips per wafer, or in other words to convert to the next diameter. This seems to occur about every 9 years. All the participants know the chances and the challenges [2] involved in such a diameter conversion, and the period of alpha-tools, of low yields, high depreciation and right timing becomes crucial. The total cost of the infrastructure conversion has been estimated at approximately $15B [3], which is beyond the resources of any individual organization. Therefore, two consortia (I300I, Selete) were installed to coordinate the industrial conversion to 300 mm wafers.
3. The price parity challenge Early dimensional dummy wafers came onto the market for around $1800. From there, the price decayed despite the lack of volume originally anticipated to accompany the decay. Today’s 300 mm
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
5
prime wafers are sold far below $900. Nevertheless, device manufacturers calculated that the cost of silicon would occupy an increasing percentage of the manufacturing process cost factor per square centimeter. Therefore, key IC companies posed a challenge to the silicon industry and to themselves to work together to achieve an unprecedented goal: price parity per square centimeter virgin silicon — for the same design rule generation — at a much faster rate than in previous diameter conversions in high volume production [4]. Let us look back into recent history. How did the square inch price factor for the 150 to 200 mm conversion develop with volume? The 200 / 150 mm price parity challenge is sketched generically in Fig. 2. Forty million 200 mm wafers have already been produced and so far no parity has been achieved. Volume production started in 1994. Now that the 300 mm conversion has been revitalized, it is the goal to achieve the same area factor of 1.4 at a fraction of the historical number. 1998 was the year when, for the first time, more 200 mm Si area was consumed than 150 mm. We expect an equivalence of Si area consumption between 200 and 300 mm not before 2010. Are there measures that can be taken to achieve the price parity target of 200 mm during this transition much earlier? This very challenging goal is not outrageously unrealistic. Nevertheless, a whole series of paradigm shifts and joint acceptance of higher risks are needed. It also requires a whole new degree of open cooperation between Si-wafer manufacturers, IC and equipment companies [4].
4. Cost reduction challenges
4.1. Paradigms shifted by Si manufacturers Of course, silicon manufacturers have to apply the usual productivity engine. They have to optimize yields, throughput, and cycle time. They have to reduce consumption of auxiliaries, of polysilicon and of consumables. They will increase overall equipment efficiency and capital utilization. Silicon manufacturers may enjoy the effects of economy of scale with ramping volumes. But all these efforts are not enough to reduce cost significantly faster than in previous conversions.
Fig. 2. Generic price parity challenge.
6
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
4.2. Overall cost reduction strategy The cost reduction program at some silicon suppliers was elevated to the same level in consciousness as the capability enhancement programs. It has been rigorously executed with formalized goal setting (target costing) and performance review processes (cost of ownership), making the task more efficient and effective. Open communication with customers and suppliers on the chances and limitations, the handles and their leverage, the probabilities of success and the shared actions required developed into a must. Every possibility to simplify the process flow (Fig. 3) was scrutinized. The development efforts focussed on high flexibility of the process sequence combined with the integration of innovative process steps, in particular to reduce silicon stock removal losses. Leading Si manufacturers actually defined a cost target for their wafers, anticipating a full load of their pilot line. The results of reviews of ‘performance against target (PAT)’, carried out quarterly, are shown in Fig. 4. Besides the overall target, subtargets of costs for all major steps are derived and agreed upon within the task owners. In order to exploit the maximum cost potential the following strategy is consequently pursued at some silicon manufacturers. Different technology approaches were evaluated for every process step. In slicing, for example, multi-wire slicing, ID slicing, band slicing, laser cutting, high-pressure water cutting, and pascal cutting were explored in terms of cost potential, capability and timing. At this point, breakthrough
Fig. 3. The 300 mm simplified process flow.
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
7
Fig. 4. Performance against target.
innovations were considered very carefully. Handling issues, clusterability, automation, potential for standardization, and in-line metrology capability were also under consideration. The decision was executed by a quality function deployment (QFD) procedure. It is worth mentioning that, in this way, the maximum cost reduction potential was considered and built in right from the very beginning. As a result, a flexible and innovative process flow, sketched schematically in Fig. 3, was realized. In going from 200 to 300 mm diameter manufacturing costs for the various process step groups scale differently. In some processes, time extends with the diameter, some processes have to account for the increased surface area, crystal growth with the effects of residual melt, seed and tail ends and the significantly more expensive quartz and graphite parts scale even higher than with the area factor. For a few other processes, time is independent of diameter, only the more expensive equipment matters. Also in terms of cost types percentages change characteristically. The influence of the cost of human resources decreases, depreciation and interest increase even higher. Fig. 5 lists some of the scaling elements. All these costs contribute with different weight to the total cost of manufacturing. Figs. 6 and 7 show the cost distribution for polished wafers both in terms of process steps as well as of cost types. Divisional and company overheads are not included. The effects of some of the cost reduction potentials are not included.
Fig. 5. Generic cost scaling (200 to 300 mm).
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
8
Fig. 6. Cost distribution.
Fig. 7. Cost types 300 mm.
5. Communication challenges
5.1. Paradigms shifted by IC companies Shifting paradigms means an open communication on chances, opportunities, limitations and risks between customers and suppliers. Total cost minimization means an holistic approach involving all parties such as Si manufacturers, IC houses, suppliers, and consortia to drive standardization at a very early stage. Of course, the risks have to be shared between all parties. Device houses and silicon manufacturers have to sit together and tailor silicon specifications to the real needs of IC lines. Linear extrapolation from previous design rules maintains a nice safety margin, but results in overspecification and cost adders that most device houses are not even aware of. As a very cost efficient example, Dietrich [5] suggests — by widening the ITRS roadmap — using interstitial-rich wafers (slowly pulled) for monitor wafers and to work out an advanced metrology which is capable of differentiating between crystal originated defects (COPs) and particles.
6. Technological challenges Paradigm shifting means to design in cost reduction opportunities right from the beginning. Design rule wafer requirements beyond 0.1 mm are mandatory in the 300 mm era. Breakthrough innovations had to be built in right from the beginning, requiring a high degree of flexibility. The process sequence contains new or substantially modified processes such as crystal growth, multi-wire slicing, grinding and double-side polishing. Right from the beginning the capability required is comparable at least to 200 mm wafers.
6.1. Crystal pulling Economic 300 mm crystal pulling is a real challenge. The control of the melt, up to 300 kg, heat dissipation, convection, pulling speed as well as the influence of the magnetic field will be the key to a successful economic pulling process. The use of magnetic fields to control the convection and consequently steering the oxygen will be mandatory.
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
9
Fig. 8. Cost of ownership for different hot zone (HZ) puller technologies.
Auxiliaries from polysilicon to crucibles and graphite parts are very costly. Therefore, process simulations are mandatory for two reasons: cost reduction and time reduction to develop the material required — interstitial-rich (fast pull), vacancy-rich (slow pull), ring wafer (fast pull) or even perfect wafer. The yield has the overall highest impact on cost of ownership; high yields combined with large charges are the optimum. Fig. 8 depicts the influence of the theoretical yield and increasing charge sizes. Fig. 9 shows a 300 mm crystal grown with a 32 hot zone (250 kg polysilicon charge). Even the automation and handling of these crystals require new approaches.
6.2. Multi-wire slicing A brand new process, multi-wire slicing, has been developed for technical and economic reasons. This technology offers a minimum taper, bow and warpage while minimizing the kerf loss compared
Fig. 9. 300 mm crystal, 250 kg.
10
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
Fig. 10. Double-side polishing machine.
to ID slicing. Diamond-coated wire slicing, a possible breakthrough innovation, is under evaluation and offers a further cost reduction potential and can be integrated into the process flow at any time.
6.3. Grinding Grinding has replaced lapping for many reasons. The process is cleaner and fully automated, the wafers exhibit a higher flatness and less damage at comparable cost. Of course, challenges such as waviness resulting from slicing have to be solved.
6.4. Polishing New technologies, such as double-side polishing (Fig. 10), offer new opportunities for process integration. The DSP technology has already demonstrated its high flatness potential, as shown in Fig. 11, as well as high nanotopology capability. Intermediate cleaning steps can be eliminated. Double-side polishing offers the opportunity to eliminate wax mounting of wafers to a carrier. The resulting polished backside is of advantage in terms of minimized slip sensibility and particle transfer probability, but poses a series of new challenges with respect to automation, tracking and wafer handling. The smoother backsides make defects even more visible, increasing the attention of handling issues.
7. A 300 mm epi-wafer as an example of joint total cost minimization A 300 mm epitaxial wafer (0.18 mm) is already available due to a straightforward upgrade of equipment and the 200 mm process. Additional cost reductions can be achieved by a joint Si
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
11
Fig. 11. SFQR max distribution on a 300 mm wafer (site size 25 mm 3 25 mm).
manufacturer and IC house total cost minimizing product design. This will be demonstrated for the new generation of epitaxial wafers. Traditionally, epitaxial wafers are prime polished wafers, which are then topped with the epi-layer exhibiting the required properties. The substrate adds little value besides the single crystal structure information, resistivity, dimension and purity. The 300 mm epitaxial wafers can be designed more cost efficiently and achieve a cost factor over the prime polished wafer of 1.25 or even less if all opportunities are exploited (Fig. 12). The substrate has to be as inexpensive as possible. Low-cost crystal growth processes with cheaper equipment and auxiliaries can achieve this. Shifting paradigms even means considering the use of remelt. The specification of oxygen, radial oxygen variation, resistivity, and radial resistivity variation
Fig. 12. Prime wafer cost reduction potential.
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
12
has to be widened substantially. An epitaxial substrate may also be manufactured by not applying a prime polished wafer every step. Leading IC companies have demonstrated that 300 mm leading edge products can be produced without external gettering. Therefore, this step should be eliminated completely. Furthermore, the same holds for the oxide backcapping layer that prevents outdiffusion of boron in p / p 1 epitaxy. The choice of the correct resistivity window for substrate and layer eliminates this need completely. Therefore, polysilicon, backside damage and backside capping layers can be eliminated, reducing the cost of the epitaxial wafer substantially.
8. Standardization as a cost reduction driver Another important key word for accelerated cost reduction is standardization. Previous diameter conversions narrowed the variations in dimensions each time. A conscious effort is underway to emphasize this aspect even more in setting the early standards for 300 mm. This applies to silicon dimensions, to wafer identification by laser marks, to metrology and data generation, but also to aspects such as standardized wafer shippers and carriers. A world-wide consensus is needed in standardization to reduce non-value-adding costs. SEMI needs to be supported! • • • • • •
one one one one one one
standardized type and location for wafer ID laser marking; edge contour and shape; unified flatness metrology tool setup definition and site definition; flatness measurement methodology; unified LLS definition and setup for particle / etch pit discrimination; standardized backside.
9. Summary The 300 mm polished and epitaxial wafer is available in 0.18 mm quality; 0.13 mm quality is under development. With respect to technology, the challenges are manifold but no showstoppers are foreseen. The main challenge is cost reduction. Silicon is a highly engineered material in terms of dimension, purity and application-specific tailored properties. Performance is increasing, whereas costs have been decreasing continuously for years, supporting the validity of Moore’s law and enabling a revolution in communication technology. Yes, silicon can be cheaper, price parity can be reached even significantly faster than for the previous conversion! As a prerequisite we need a coherent approach from Si manufacturers, IC houses and equipment and auxiliary suppliers supported by a world-wide accepted standardization. However, the most important factor is the economy of scale! We have to overcome the chicken and the egg dilemma because a smooth and steady transition to volume production is needed first. The availability of the material and the equipment as well as the feasibility of the 300 mm processes has already been demonstrated by the readiness and shipment of the first 64 MDRAM devices.
P.O. Hahn / Microelectronic Engineering 56 (2001) 3 – 13
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The analysts forecast an average growth of 15% per year. Silicon is the fuel for the communication age and will keep us in line with Moore’s law. Globalization has just started and is not imaginable without silicon, and the 300 mm generation will become the workhorse during the first century of the new millennium! References [1] H.R. Huff, R.K. Goodall, R.H. Nilson, K. Griffiths, in: Symposium Proceedings ULSI / 97, 191st Meeting ECS, May 4–9, 1997. [2] P.O. Hahn, H.G. Fußstetter, Productronica 95, Munich Proceedings in Semiconductor Equipment and Materials Beyond JESSI — 300 mm and Single Wafer Processing. [3] Dataquest, May 22, 1995, The move toward 300 mm wafers: the issues surrounding — when and how — money will talk. [4] P.O. Hahn, H.G. Fußstetter, Future Fab International, vol. 9, pp. 183–187. [5] H. Dietrich, F. Bialas, N. Caspary, in: SEMI 2000 European IEEE / SEMI Semiconductor Manufacturing Conference, Munich, 2000.