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The analog pipeline system for the zeus calorimeter readout
Nuclear Physics B (Proc. Suppl.) 16 (1990) 511-512 North-Holland
THE ANALOG PIPELINE SYSTEM FOR THE ZEUS CALORIMETER READOUT Luis HERVAS (representing the Zeus Calorimeter Electronics Group) Universidad Autônoma de Madrid, Madrid,Spain The analog pipelining system for the Zeus calorimeter is presented. A 5 jcs delay line operating at 10 i-Iz and a one event Buffer-Multiplexer custom chips have been developed. A description of the chips as heart of the Front End electronics as well as test results are given. 1.
INTRODUCTION
ture of one channel is shown in figure 1.
ZEUS 1 is one of the two experiments for the new e-p storage ring HERA at DESY . In HERA 30 GeV elec-
trons will collide with 820 GeV protons. One of the main components is the high resolution calorimeter 2 consist-
ing of depleted uranium (DU) and scintillator layers,
with photomultiplier (PM) readout. The high crossing
rate of protons and electrons, 10.4 Mhz, and the large dynamic range requirements, from 10 MeV to 400 GeV,
have lead to the development of an analog pipeline sys-
tem since commercially available ADCs followed up by a digital pipeline do not provide such a performance at reasonable costs and power consumptions . The pipeline
has to store the analog data from the calorimeter for 5 its, the time the first level trigger needs to reach the decision whether a particular bunch crossing contains
an even% of interest . The wide energy range is covered
by a high and a low gain channels, each with a dynamic range of about 4000 :1 . In addition the pipeline
has to be linear and provide a timing accuracy in the 1 ns range. The pipeline system is constructed using two 2 .5 pm CMOS full custom integrated circuits . 2.
THE PIPELINE CHIP
The first stage of the system consists of the main pipeline chip, which stores the sampled data of the preceding 5 ps . For a sampling rate of 10.4 MHz a memory depth of 58 cells has been chosen .
The pipeline storage is based on an optimized ana-
log switched-capacitor (SC) architecture . The architec0920-5632/90/$3.50 © Elsevier Science Publishers B .V . North-Holland
FIGURk 1 Block diagramm of one pipeline châienel During the write time the switches named 'VVR' and the S; of the selected cell are closed and charge is stored at the selected capacitor C; . To read out the sampled data the switches labeled 'RD' must be closed and the charge
is transferred to capacitor Cf. The output voltage is
thus only proportional to the ratio of capacitances, a figure which is optimised in the manufacturing process. After reading out one cell the readout amplifier must be
cleared by the RESET switch . Four pipeline channels are placed together on one pipeline chip . All digital control inputs are TTL, ECL and CMOS compatible as they have differential input stages . 2 .1 .
Measurement Results
Extensive measurements on these devices have been performed 3,4,5 . The results are well within the specifi-
cations : DC linearity (0 .05% at inputs in -3V.. .+3V range), noise (< 0.3 mV r.m.s .
(baseband noise)),
cell to cell switching jitter (,:0 .1 ns), pedestal (typically ±20 mV), pedestal variation (few millivolts), input charging time constant (;~::5 ns), maximum writ-
L. Hervas, Zeus Calorimeter Electronics Group/Analog pipeline system
512
board calibration tools, e.g . charge injectors to simu-
ing speed (18 MHz), and settling time of the readout amplifier (==500 ns to 0.1%) . Only the change of the
late PM pulses, or a DC precision source to calibrate the pipelines.
pedestals at the physical ends of the pipeline (f10 mV) and the gain variation (0 .3% to 1%) from cell to cell
Each PM signal is resistively split into a trigger sum,
a high and a low gain shaper, the DU current measur-
are bigger than expected . 3.
ing circuit and the termination resistor. In the shapers, the signals are integrated and shaped into triangular
THE BUFFER/MULTIPLEXER CHIP
pulses with rise and fall times larger than the sampling
The second stage of the pipeline system consists of 12 buffered and 12 unbuffered inputs which are conected via an analog multiplexer to one output . For
time in order to insure samples on both edges. The
anolog pipelines sample and store the shaped signal for 12 PMs per analog card . On the reception of a trig-
writing, all twelve buffered channels are loaded in parallel with the proper cells of the pipeline . After switching
ger, the pipelines are stopped and up to eigth sam-
to the read state only the selected channel to be mul-
ples are transfered to the buffers. Then the pipelines
tiplexed receives the read shift clocks . The unbuffered inputs can be used for general purpose DC signals in the
are restarted and the samples are multiplexed from the buffers down to the ADC system . In this way the dead-
range of -3 ...+3 Volt . The results of the first measure-
time is drastically reduced.
ments have shown that the design criteria are satisfied
The unbuffered multiplexer inputs are used to send
in an even better way than the pipeline chips. 4.
the DU current measurements and other monitoring information to the same ADCs .
THE PIPELINE SYSTEM IN THE FRONT END
The pulse height which is proportional to the energy
Figure 2 shows a scheme of the Front-End card
deposited in the calorimeter is determined by the sum
which uses the 2 described application specific inte-
of the two samples around the peak weighted with the
grated circuits (ASICs).
slopes in order to remove time jitter influence. The time
is derived from one sample and the slope, by comparing
RM
it to the expected value of the sample for time zero.
The complete system consists of about 12000
PM INPUT 12
PMT's requiring 24000 pipeline channels, i.e .
some
6000 pipeline and some 2000 buffer/multiplexer chips. 1. The ZEUS Detector, Technical Proposal 1986 and Status Report 1987 DESY/Hamburg . 2. E. Hilger et .al., Nuclear Instruments and Methods, A257(1987), 488.
INPUT
CABLE DRIVER C IN
41844
FIGURE 2 Schematics of the Front-End "analog card" It is placed in the backbeam of the calorimeter mod-
ules as close as possible to the PMs and includes on-
3. W. Buttler et .al., Design and Performance of a 10 MHz CMOS Analog Pipeline, NIM, A227(1989) 217-221. 4. W. Sippach et . al ., Development of the Front End Electronic for the ZEUS High Resolution Calorimeter, Contribution to the IEEE Nuclear Science Symposium Orlando/Florida (1988) . 5. J. Möschen, Entwicklung eines schnellen Analogspeichers in integrierter CMOS-Technik, Studienarbeit, Universität-GH-Duisburg (1987) .
THE ANALOG PIPELINE SYSTEM FOR THE ZEUS CALORIMETER READOUT Luis HERVAS (representing the Zeus Calorimeter Electronics Group) Universidad Autônoma de Madrid, Madrid,Spain The analog pipelining system for the Zeus calorimeter is presented. A 5 jcs delay line operating at 10 i-Iz and a one event Buffer-Multiplexer custom chips have been developed. A description of the chips as heart of the Front End electronics as well as test results are given. 1.
INTRODUCTION
ture of one channel is shown in figure 1.
ZEUS 1 is one of the two experiments for the new e-p storage ring HERA at DESY . In HERA 30 GeV elec-
trons will collide with 820 GeV protons. One of the main components is the high resolution calorimeter 2 consist-
ing of depleted uranium (DU) and scintillator layers,
with photomultiplier (PM) readout. The high crossing
rate of protons and electrons, 10.4 Mhz, and the large dynamic range requirements, from 10 MeV to 400 GeV,
have lead to the development of an analog pipeline sys-
tem since commercially available ADCs followed up by a digital pipeline do not provide such a performance at reasonable costs and power consumptions . The pipeline
has to store the analog data from the calorimeter for 5 its, the time the first level trigger needs to reach the decision whether a particular bunch crossing contains
an even% of interest . The wide energy range is covered
by a high and a low gain channels, each with a dynamic range of about 4000 :1 . In addition the pipeline
has to be linear and provide a timing accuracy in the 1 ns range. The pipeline system is constructed using two 2 .5 pm CMOS full custom integrated circuits . 2.
THE PIPELINE CHIP
The first stage of the system consists of the main pipeline chip, which stores the sampled data of the preceding 5 ps . For a sampling rate of 10.4 MHz a memory depth of 58 cells has been chosen .
The pipeline storage is based on an optimized ana-
log switched-capacitor (SC) architecture . The architec0920-5632/90/$3.50 © Elsevier Science Publishers B .V . North-Holland
FIGURk 1 Block diagramm of one pipeline châienel During the write time the switches named 'VVR' and the S; of the selected cell are closed and charge is stored at the selected capacitor C; . To read out the sampled data the switches labeled 'RD' must be closed and the charge
is transferred to capacitor Cf. The output voltage is
thus only proportional to the ratio of capacitances, a figure which is optimised in the manufacturing process. After reading out one cell the readout amplifier must be
cleared by the RESET switch . Four pipeline channels are placed together on one pipeline chip . All digital control inputs are TTL, ECL and CMOS compatible as they have differential input stages . 2 .1 .
Measurement Results
Extensive measurements on these devices have been performed 3,4,5 . The results are well within the specifi-
cations : DC linearity (0 .05% at inputs in -3V.. .+3V range), noise (< 0.3 mV r.m.s .
(baseband noise)),
cell to cell switching jitter (,:0 .1 ns), pedestal (typically ±20 mV), pedestal variation (few millivolts), input charging time constant (;~::5 ns), maximum writ-
L. Hervas, Zeus Calorimeter Electronics Group/Analog pipeline system
512
board calibration tools, e.g . charge injectors to simu-
ing speed (18 MHz), and settling time of the readout amplifier (==500 ns to 0.1%) . Only the change of the
late PM pulses, or a DC precision source to calibrate the pipelines.
pedestals at the physical ends of the pipeline (f10 mV) and the gain variation (0 .3% to 1%) from cell to cell
Each PM signal is resistively split into a trigger sum,
a high and a low gain shaper, the DU current measur-
are bigger than expected . 3.
ing circuit and the termination resistor. In the shapers, the signals are integrated and shaped into triangular
THE BUFFER/MULTIPLEXER CHIP
pulses with rise and fall times larger than the sampling
The second stage of the pipeline system consists of 12 buffered and 12 unbuffered inputs which are conected via an analog multiplexer to one output . For
time in order to insure samples on both edges. The
anolog pipelines sample and store the shaped signal for 12 PMs per analog card . On the reception of a trig-
writing, all twelve buffered channels are loaded in parallel with the proper cells of the pipeline . After switching
ger, the pipelines are stopped and up to eigth sam-
to the read state only the selected channel to be mul-
ples are transfered to the buffers. Then the pipelines
tiplexed receives the read shift clocks . The unbuffered inputs can be used for general purpose DC signals in the
are restarted and the samples are multiplexed from the buffers down to the ADC system . In this way the dead-
range of -3 ...+3 Volt . The results of the first measure-
time is drastically reduced.
ments have shown that the design criteria are satisfied
The unbuffered multiplexer inputs are used to send
in an even better way than the pipeline chips. 4.
the DU current measurements and other monitoring information to the same ADCs .
THE PIPELINE SYSTEM IN THE FRONT END
The pulse height which is proportional to the energy
Figure 2 shows a scheme of the Front-End card
deposited in the calorimeter is determined by the sum
which uses the 2 described application specific inte-
of the two samples around the peak weighted with the
grated circuits (ASICs).
slopes in order to remove time jitter influence. The time
is derived from one sample and the slope, by comparing
RM
it to the expected value of the sample for time zero.
The complete system consists of about 12000
PM INPUT 12
PMT's requiring 24000 pipeline channels, i.e .
some
6000 pipeline and some 2000 buffer/multiplexer chips. 1. The ZEUS Detector, Technical Proposal 1986 and Status Report 1987 DESY/Hamburg . 2. E. Hilger et .al., Nuclear Instruments and Methods, A257(1987), 488.
INPUT
CABLE DRIVER C IN
41844
FIGURE 2 Schematics of the Front-End "analog card" It is placed in the backbeam of the calorimeter mod-
ules as close as possible to the PMs and includes on-
3. W. Buttler et .al., Design and Performance of a 10 MHz CMOS Analog Pipeline, NIM, A227(1989) 217-221. 4. W. Sippach et . al ., Development of the Front End Electronic for the ZEUS High Resolution Calorimeter, Contribution to the IEEE Nuclear Science Symposium Orlando/Florida (1988) . 5. J. Möschen, Entwicklung eines schnellen Analogspeichers in integrierter CMOS-Technik, Studienarbeit, Universität-GH-Duisburg (1987) .