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The application of high density electronic packaging for spacecraft cost and mass reduction
~
Acta Astronautica Vol. 35. Suppl., pp. 763-769. 1995 Elsev ier Science Ltd . Printed in Great Br itain
Pergamon
0094-5765(94)00248-7
The Application of High Density Electronic Packaging for Spacecraft Cost and Mass Reduction Lynn E. Lowry, Jon S. Prokop* .. Peter Sandborn* and Kristan Evans Jet
Propulsion
Laboratory
4800 Oak Grove Dr. m/s 158-224 Pasadena CA 91109 and
·Microelectronics
and
Computer
Technology
Corp .
12100 Technology Blvd . Austin TX 78727
ABSTRACT It has become clear over the past few years that packaging of spacecraft electronic systems must be improved. Not only have the weight and volume taken up by conventional packaging and interconnect systems become excessive, but active devices have advanced to the point where system performance is often limited by the packaging . Since electronic systems account for up to 30% of the size and weight budgets of a spacecraft, the utilization of high density electronic packaging will be a very important path to overall spacecraft miniaturization. In the late 1970's high density interconnection technologies were being introduced into mainframe computer applications. Subsequently, these technologies have been applied to avionics, telecommunication, biomedical and automotive systems. In each application the driving forces behind the adoption of these technologies were; improved electrical performance, miniaturization, reduced power consumption, increased reliability and reduced manufacturing costs. The application of these technologies to planetary missions could provide significant benefits by way of reduced cost and design time if commercial technology and best commercial manufacturing practices are accepted. A mixed signal telecommunication function has been used as an example to illustrate the potential mass, volume and power reduction achievable with the implementation of high density packaging technologies. The tradeoff analysis which was performed demonstrated that packaging technology selection is application specific, and system level impact must be considered early on in the design process. The results of this study which compare size, performance, cost, risk and system level impact are given. Finally, the technical and cultural obstacles which have inhibited the implementation of these technologies is discussed. Specifically, the issues of space qualified hardware and technology availability is addressed. Space qualification is perceived by industry as being the most significant obstacle to the insertion of innovative technologies and in many cases prohibited the use of best commercial manufacturing practices.
763
764
Low-cost planetary missions
INTRODUCTION System studies have shown that electronic packaging can account for up to 30% of the dry mass of the spacecraft (ref. 1). The implementation of mumchlp module(MCM) and other high density electronic packaging technologies, which have been heavily invested in by 000, ARPA and industry for the last ten years is central to achieving mass and volume reduction in future spacecraft. MCM's were developed in the early 1970's for high performance main frame computing applications. During the last decade various MCM technologies have found applications in systems requiring improved performance, miniaturization, reduced power consumption and assembly cost. The decrease in the interconnection length results in reduced power consumption and improved performance in terms of speed and minimized signal distortion. The reduction in system cost has been achieved through lowered assembly costs by the elimination of several levels of packaging and the overall reduction of the component count. Historically, interconnections at all levels have presented significant reliability concerns therefore, the elimination of one or more levels of interconnection should also improve the system reliability. However, the materials and processes used in these assemblies must be understood in terms of their reliability within the context of these applications.
HIGH DENSITY ELECTRONIC PACKAGING TECHNOLOGIES There are three primary multichip module technologies: MCM-L, MCM-C and MCM-D, the distinction is based on the substrate materials, the conductor materials and the deposition processes. A great deal of literature is available describing these technologies and the basic process flow,(ref. 2,3) a brief summary of each follows: MCM-L uses laminated organic substrate materials similar to printed circuit board. Typical materials are high temperature epoxies or polyimides. The substrate is rigid and multilayer however, it does not have particularly high mechanical strength. Bonding between layers is accomplished by a hot lamination process. Copper is the most widely used conductor, usually electrolytically plated. Via formation is accomplished by mechanical punching or laser drilling. This technology uses well known materials and processes which are relatively low cost. Considerations for its
application would include: low thermal dissipation, high dielectric constant (although new materials are being pursued), which along with the assembly processes limit circuit density, thermal expansion characteristics (typically 5X that of silicon) and the potential for moisture absorption and outgassing. MCM-C uses ceramic as the substrate material. This type of MCM can be categorized in two groups: those processed at high temperatures (up to 1500C) and those at low
temperatures. High temperature co-fired ceramics (HTCC) which use refractory metal conductors have been available for decades. Low temperature (LTCC) technologies use more conductive metals such as, silver, gold and copper. Ceramic based technologies are favored by the military for high reliability applications because ceramic is strong, inert to environmental exposure and can be hermetically sealed.
Low-cost planetary missions
765
Ceramic composites have been fabricated to achieve very high thermal conductivity(200W/mK) and controlled thermal expansion characteristics. MCM-D is an MCM substrate which uses deposited thin film on a silicon, ceramic, polymer or metal substrate. With the use of thin film technology excellent routing density s achievable. MCM·D technologies have been demonstrated for applications with operating frequencies in excess of 1 GHz. MCM-D has a relatively high cost due to its custom nature and lack of established manufacturing infrastructure.
HIGH DENSITY ELECTRONIC PACKAGING TECHNOLOGY SELECTION Multichip modules are complex assemblies and selecting the most appropriate technology and supplier(s) requires defining the trade-off space for the particular application. The technology solution trade-off space must take into account mass/volume, chip and component set, performance requirements, thermal management, manufacturability, testability, reliability, the impact of the packaging technology on the next level of the system packaging and cost. The goal is to find a design that balances performance with ease of manufacture and support while minimizing cost. Early in the design cycle, numerous tradeoff decisions have to be made intelligently and quickly before major investments are committed or detailed design work begins. These critical decisions, made within the first 20% of the total design cycle time, will ultimately commit 80% or more of the final product cost (Figure 1). Therefore, making the most appropriate choices early in the design cycle will have a significant impact throughout the design, production, and life cycle. 100 100 80
80% Percent of Product Cost Committed
80
U
60
40
40
20
20
0
U
:J "0
0
Ii: 0 0
i= c: 01
60
Cii 0
Ql
E
'iii
Ql
0 "0
Ql
a. IJ) ell
iIi 0 0
0
Verif ication Physical Logic Design De sign Start
Figure 1 • Costs incurred and committed as a function of packaging and interconnect system design and manufacturing steps.
Low-cost planetary missions
766
The tradeoff analyses performed for the JPL Telecommunication Command Detector Unit were performed using MCC's Multichip Systems Design Advisor (MSDA) tool (ref. 4). MSDA is a software tool (currently at the beta test stage of its existence) for enhancing the manufacturability and decreasing the design risk associated with the selection of packaging technologies. MSOA concurrently computes physical (size, weight, interconnect routing requirements, escape routing), electrical (delays, attenuation, dc drops, noise), thermal (internal and external thermal resistance), reliability (MTIF), and cost performance metrics for multichip systems. Figure 2 shows a block diagram of the MSOA tool. The MSOA tool concurrently performs the indicated analyses on candidate system packaging and interconnect technology/design rule selections for a given application. Reliability is assessed through the use of the Viable tool from Cadence. Viable serves as a reliability analysis manager through which MIL-HOBK-217 failure rate models and user definable failure rate models can be used.
I I
Ij I~
&
Ii
Viable (Cadence)
Ii ~
SPICE
I'
20 FEI4 (OEA International)
External Tools
rechnoloQy .l4ltllf1ll Oltabuee
J
_System Pwformlnce
OUtput Viewer
Packaging Specification
Figure 2 - Block diagram of the MSDA tradeoff analysis tool. The arrows drawn between advisor modules indicate the interdependencies managed by the MSDA tool. Links to external simulation tools can be automatically invoked from within the MSDA tool.
Low-cost planetary missions
767
DESIGN TRADE-OFF ANALYSIS A wiring diagram, information on piece parts and a candidate Surface Mount Technology (SMT) layout for the JPL Telecommunication Unit provided the input to the analyses performed. Seven different "what ifs" were performed. The parameters of interest were size, weight, thermal performance and cost. The MSDA tool's default case is a deposited thin film multichip module (MCM-D) with wire bonding used to connect its bare chips to the thin film substrate. That is shown in Table 1 as Case 1. Case 2 is a multichip module using a laminated substrate, fine-line printed wiring board and wire bonding for the chip connections. Two versions of case 2 are included (polyimide dielectric and FR-4).' Case 3. is a ceramic multichip module (MCM-C) using low temperature cofired ceramic (LTCC) for the substrate and wire bonding for chip connection. Case 4 is the same approach as Case 3 except that metallurgical flip chipping is used to connect the chips instead of wire bonding. Case 5 is MCM-D as Case 1, but uses metallurgical flip chipping. Case 6 is a SMT version, but the tool was allowed to calculate the minimum theoretical piece part spacing to arrive at the module size. Case 7 is the SMT version previously designed. Cas e
1 2a 2b
3 4 5 6 7
Description
Cost ($)
MCM-D, Wirebond MCM-L, Wirebond (Polyimide) MCM-L, Wirebond (FR-4) LTCC, Wirebond LTCC, C4 MCM-D, C4 SMT, (minimum size) SMT, (placed)
Weight (gms)
Size (in 2)
2866 1474
Internal Thermal R, without and with thermal vias for U11 (deg C/W) 33.0/11.0 276.4/6.5
10.2 8.2
5.69 5.69
1474
49.5/6.1
10.1
5.69
1747 938 2054 667
45.1/5.9 46.317.2 34.3/12.3 15.0/1.8
16.9 16.8 10.1 15.4
5.69 5.66 5.66 7.96
672
15.0/1.8
25.7
14.97
Table 1 - Summary of the results of MSDA analyses. MCM-D = thin/medium film, MCM-L = fine line printed circuit board, LTCC = low temperature cofired ceramic, C4 = metallurgical area array flip chip, SMT = surface mount (minimum size = minimum theoretical size, placed = placement which approximately matches JPL supplied layout), both SMT cases assume an FR-4 board. We assumed that the U3 package was ceramic (empty weight:: 0.8 g) and all the other SMT packages were plastic (total empty weight = 2.5 g).
768
Low-cost planetary missions
A comparison of the data in Table 1 shows that the SMT versions had the lowest costs and they were essentially the same in each case. It should be noted that the MSDA tool estimates costs based on internal sets of standard process flows which assume the existence of a capitalized and fully operational, seasoned factory with constant, near capacity production. The costs shown may not reflect what is being quoted for MCMs in small quantities today (since no fully operational, seasoned MCM factories exist), and should be used for comparison purposes only. The costs presented here assume a total of 10 modules constructed in two lots (5 each). The next highest cost case was Case 4, the MCM-C version using Low Temperature Cofired Ceramic and metallurgical flip chipping. Flip Chipping is not a standard process with all vendors as yet, so availability of both processes might be an issue and may well negate any cost advantage indicated by the data shown. Size turned out not to be an issue for Cases 1 through 5. In fact the similarity of the sizes in these cases indicates that further size optimization is possible for these cases. For Case 6, the MSDA tool was allowed to calculate the theoretical minimum placement area for all components. The size in Case 7 is the one given by the SMT version provided (approximates the same placement). One could interpret the case 6 and 7 areas to be the boundaries of the available design space for the SMT solution. Thus, an astute designer with good placement and layout tools would likely produce a smaller area unit lying somewhere between the two extremes. The case 7 SMT version had the highest weight due to the single chip packages and the large board area. The LTCC solutions may be as heavy as the SMT cases depending on how well the placement is optimized. The MCM-D cases are heavier than the MCM-L due to the presence of an Alumina substrate. This trade-off analysis has shown that one of the two MCM-C versions would be the appropriate choice for this unit. This approach offers a 3X reduction in size, reduced mass, and good thermal characteristics. The increase in cost compared with the SMT technology is negligible. Additionally, ceramic has good structural characteristics, doesn't outgas and has proven reliability. This conclusion was reached by investing less than a one day effort using the MSDA tool, and without investing in costly prototyping of various approaches. About half the time was used to put the component data into the MSDA library. The remainder of the time was used in iterating the design.
HIGH DENSITY ELECTRONIC PACKAGING TECHNOLOGY IMPLEMENTATION The implementation of these technologies in future spacecraft may be inhibited by the lack of established manufacturing infrastructure. This presents an availability concem for a potential user of MCM technologies and as has been mentioned previously, impacts cost.
Low-cost planetary missions
769
Additionally, the lack of relaibility data and qualification standards will inhibit the insertion of these technologies. Reliability testing guidelines are being developed by the RELTECH program(ref.5). RELTECH is a joint ARPA, 000, NASA. Industry working group which is performing product evaluations and identifying failure mechanisms for various MCM technologies. A goal of this group is to develop a database which will lead to the establishment of testing. qualification and screening procedures. Cost effective solutions for testing and qualifying any MCM technology must be sought. During an Advanced Electronic Packaging workshop hosted by JPL and MCC in June 1993 many industrial participants expressed the need to change space qualification practices. Many examples were given of unecessary requirements which drove up costs and inhibited technological innovations.
ACKNOWLEDGMENTS
The work described here was carried out at the Jet Propulsion Laboratory, California Institute of Technology under contract with the National Aeronautics and Space Administration, through sponsorship of NASA'S Office of Advanced Concepts and Technology and the Office of Science. We also appreciate the support John McNamee of the Mars Surface Exploration Pre-Project. REFERENCES 1. Personal Communication with Dr. R. Jones, JPL 2. G. Messner. I. Turlik, J. Balde, P. Garrou, Thin Film Multichip Modules, ISHM, 1990. 3. Proceedings of the 1993 International Conference on Multichip Modules, ISH/IEPS, Denver CO, April 1993. 4. Multichip Systems Design Advisor Users Handbook. MCC. 5. RELTECH Validation Plan Rev. 2.1, John Evans, NASA Code QE.
Acta Astronautica Vol. 35. Suppl., pp. 763-769. 1995 Elsev ier Science Ltd . Printed in Great Br itain
Pergamon
0094-5765(94)00248-7
The Application of High Density Electronic Packaging for Spacecraft Cost and Mass Reduction Lynn E. Lowry, Jon S. Prokop* .. Peter Sandborn* and Kristan Evans Jet
Propulsion
Laboratory
4800 Oak Grove Dr. m/s 158-224 Pasadena CA 91109 and
·Microelectronics
and
Computer
Technology
Corp .
12100 Technology Blvd . Austin TX 78727
ABSTRACT It has become clear over the past few years that packaging of spacecraft electronic systems must be improved. Not only have the weight and volume taken up by conventional packaging and interconnect systems become excessive, but active devices have advanced to the point where system performance is often limited by the packaging . Since electronic systems account for up to 30% of the size and weight budgets of a spacecraft, the utilization of high density electronic packaging will be a very important path to overall spacecraft miniaturization. In the late 1970's high density interconnection technologies were being introduced into mainframe computer applications. Subsequently, these technologies have been applied to avionics, telecommunication, biomedical and automotive systems. In each application the driving forces behind the adoption of these technologies were; improved electrical performance, miniaturization, reduced power consumption, increased reliability and reduced manufacturing costs. The application of these technologies to planetary missions could provide significant benefits by way of reduced cost and design time if commercial technology and best commercial manufacturing practices are accepted. A mixed signal telecommunication function has been used as an example to illustrate the potential mass, volume and power reduction achievable with the implementation of high density packaging technologies. The tradeoff analysis which was performed demonstrated that packaging technology selection is application specific, and system level impact must be considered early on in the design process. The results of this study which compare size, performance, cost, risk and system level impact are given. Finally, the technical and cultural obstacles which have inhibited the implementation of these technologies is discussed. Specifically, the issues of space qualified hardware and technology availability is addressed. Space qualification is perceived by industry as being the most significant obstacle to the insertion of innovative technologies and in many cases prohibited the use of best commercial manufacturing practices.
763
764
Low-cost planetary missions
INTRODUCTION System studies have shown that electronic packaging can account for up to 30% of the dry mass of the spacecraft (ref. 1). The implementation of mumchlp module(MCM) and other high density electronic packaging technologies, which have been heavily invested in by 000, ARPA and industry for the last ten years is central to achieving mass and volume reduction in future spacecraft. MCM's were developed in the early 1970's for high performance main frame computing applications. During the last decade various MCM technologies have found applications in systems requiring improved performance, miniaturization, reduced power consumption and assembly cost. The decrease in the interconnection length results in reduced power consumption and improved performance in terms of speed and minimized signal distortion. The reduction in system cost has been achieved through lowered assembly costs by the elimination of several levels of packaging and the overall reduction of the component count. Historically, interconnections at all levels have presented significant reliability concerns therefore, the elimination of one or more levels of interconnection should also improve the system reliability. However, the materials and processes used in these assemblies must be understood in terms of their reliability within the context of these applications.
HIGH DENSITY ELECTRONIC PACKAGING TECHNOLOGIES There are three primary multichip module technologies: MCM-L, MCM-C and MCM-D, the distinction is based on the substrate materials, the conductor materials and the deposition processes. A great deal of literature is available describing these technologies and the basic process flow,(ref. 2,3) a brief summary of each follows: MCM-L uses laminated organic substrate materials similar to printed circuit board. Typical materials are high temperature epoxies or polyimides. The substrate is rigid and multilayer however, it does not have particularly high mechanical strength. Bonding between layers is accomplished by a hot lamination process. Copper is the most widely used conductor, usually electrolytically plated. Via formation is accomplished by mechanical punching or laser drilling. This technology uses well known materials and processes which are relatively low cost. Considerations for its
application would include: low thermal dissipation, high dielectric constant (although new materials are being pursued), which along with the assembly processes limit circuit density, thermal expansion characteristics (typically 5X that of silicon) and the potential for moisture absorption and outgassing. MCM-C uses ceramic as the substrate material. This type of MCM can be categorized in two groups: those processed at high temperatures (up to 1500C) and those at low
temperatures. High temperature co-fired ceramics (HTCC) which use refractory metal conductors have been available for decades. Low temperature (LTCC) technologies use more conductive metals such as, silver, gold and copper. Ceramic based technologies are favored by the military for high reliability applications because ceramic is strong, inert to environmental exposure and can be hermetically sealed.
Low-cost planetary missions
765
Ceramic composites have been fabricated to achieve very high thermal conductivity(200W/mK) and controlled thermal expansion characteristics. MCM-D is an MCM substrate which uses deposited thin film on a silicon, ceramic, polymer or metal substrate. With the use of thin film technology excellent routing density s achievable. MCM·D technologies have been demonstrated for applications with operating frequencies in excess of 1 GHz. MCM-D has a relatively high cost due to its custom nature and lack of established manufacturing infrastructure.
HIGH DENSITY ELECTRONIC PACKAGING TECHNOLOGY SELECTION Multichip modules are complex assemblies and selecting the most appropriate technology and supplier(s) requires defining the trade-off space for the particular application. The technology solution trade-off space must take into account mass/volume, chip and component set, performance requirements, thermal management, manufacturability, testability, reliability, the impact of the packaging technology on the next level of the system packaging and cost. The goal is to find a design that balances performance with ease of manufacture and support while minimizing cost. Early in the design cycle, numerous tradeoff decisions have to be made intelligently and quickly before major investments are committed or detailed design work begins. These critical decisions, made within the first 20% of the total design cycle time, will ultimately commit 80% or more of the final product cost (Figure 1). Therefore, making the most appropriate choices early in the design cycle will have a significant impact throughout the design, production, and life cycle. 100 100 80
80% Percent of Product Cost Committed
80
U
60
40
40
20
20
0
U
:J "0
0
Ii: 0 0
i= c: 01
60
Cii 0
Ql
E
'iii
Ql
0 "0
Ql
a. IJ) ell
iIi 0 0
0
Verif ication Physical Logic Design De sign Start
Figure 1 • Costs incurred and committed as a function of packaging and interconnect system design and manufacturing steps.
Low-cost planetary missions
766
The tradeoff analyses performed for the JPL Telecommunication Command Detector Unit were performed using MCC's Multichip Systems Design Advisor (MSDA) tool (ref. 4). MSDA is a software tool (currently at the beta test stage of its existence) for enhancing the manufacturability and decreasing the design risk associated with the selection of packaging technologies. MSOA concurrently computes physical (size, weight, interconnect routing requirements, escape routing), electrical (delays, attenuation, dc drops, noise), thermal (internal and external thermal resistance), reliability (MTIF), and cost performance metrics for multichip systems. Figure 2 shows a block diagram of the MSOA tool. The MSOA tool concurrently performs the indicated analyses on candidate system packaging and interconnect technology/design rule selections for a given application. Reliability is assessed through the use of the Viable tool from Cadence. Viable serves as a reliability analysis manager through which MIL-HOBK-217 failure rate models and user definable failure rate models can be used.
I I
Ij I~
&
Ii
Viable (Cadence)
Ii ~
SPICE
I'
20 FEI4 (OEA International)
External Tools
rechnoloQy .l4ltllf1ll Oltabuee
J
_System Pwformlnce
OUtput Viewer
Packaging Specification
Figure 2 - Block diagram of the MSDA tradeoff analysis tool. The arrows drawn between advisor modules indicate the interdependencies managed by the MSDA tool. Links to external simulation tools can be automatically invoked from within the MSDA tool.
Low-cost planetary missions
767
DESIGN TRADE-OFF ANALYSIS A wiring diagram, information on piece parts and a candidate Surface Mount Technology (SMT) layout for the JPL Telecommunication Unit provided the input to the analyses performed. Seven different "what ifs" were performed. The parameters of interest were size, weight, thermal performance and cost. The MSDA tool's default case is a deposited thin film multichip module (MCM-D) with wire bonding used to connect its bare chips to the thin film substrate. That is shown in Table 1 as Case 1. Case 2 is a multichip module using a laminated substrate, fine-line printed wiring board and wire bonding for the chip connections. Two versions of case 2 are included (polyimide dielectric and FR-4).' Case 3. is a ceramic multichip module (MCM-C) using low temperature cofired ceramic (LTCC) for the substrate and wire bonding for chip connection. Case 4 is the same approach as Case 3 except that metallurgical flip chipping is used to connect the chips instead of wire bonding. Case 5 is MCM-D as Case 1, but uses metallurgical flip chipping. Case 6 is a SMT version, but the tool was allowed to calculate the minimum theoretical piece part spacing to arrive at the module size. Case 7 is the SMT version previously designed. Cas e
1 2a 2b
3 4 5 6 7
Description
Cost ($)
MCM-D, Wirebond MCM-L, Wirebond (Polyimide) MCM-L, Wirebond (FR-4) LTCC, Wirebond LTCC, C4 MCM-D, C4 SMT, (minimum size) SMT, (placed)
Weight (gms)
Size (in 2)
2866 1474
Internal Thermal R, without and with thermal vias for U11 (deg C/W) 33.0/11.0 276.4/6.5
10.2 8.2
5.69 5.69
1474
49.5/6.1
10.1
5.69
1747 938 2054 667
45.1/5.9 46.317.2 34.3/12.3 15.0/1.8
16.9 16.8 10.1 15.4
5.69 5.66 5.66 7.96
672
15.0/1.8
25.7
14.97
Table 1 - Summary of the results of MSDA analyses. MCM-D = thin/medium film, MCM-L = fine line printed circuit board, LTCC = low temperature cofired ceramic, C4 = metallurgical area array flip chip, SMT = surface mount (minimum size = minimum theoretical size, placed = placement which approximately matches JPL supplied layout), both SMT cases assume an FR-4 board. We assumed that the U3 package was ceramic (empty weight:: 0.8 g) and all the other SMT packages were plastic (total empty weight = 2.5 g).
768
Low-cost planetary missions
A comparison of the data in Table 1 shows that the SMT versions had the lowest costs and they were essentially the same in each case. It should be noted that the MSDA tool estimates costs based on internal sets of standard process flows which assume the existence of a capitalized and fully operational, seasoned factory with constant, near capacity production. The costs shown may not reflect what is being quoted for MCMs in small quantities today (since no fully operational, seasoned MCM factories exist), and should be used for comparison purposes only. The costs presented here assume a total of 10 modules constructed in two lots (5 each). The next highest cost case was Case 4, the MCM-C version using Low Temperature Cofired Ceramic and metallurgical flip chipping. Flip Chipping is not a standard process with all vendors as yet, so availability of both processes might be an issue and may well negate any cost advantage indicated by the data shown. Size turned out not to be an issue for Cases 1 through 5. In fact the similarity of the sizes in these cases indicates that further size optimization is possible for these cases. For Case 6, the MSDA tool was allowed to calculate the theoretical minimum placement area for all components. The size in Case 7 is the one given by the SMT version provided (approximates the same placement). One could interpret the case 6 and 7 areas to be the boundaries of the available design space for the SMT solution. Thus, an astute designer with good placement and layout tools would likely produce a smaller area unit lying somewhere between the two extremes. The case 7 SMT version had the highest weight due to the single chip packages and the large board area. The LTCC solutions may be as heavy as the SMT cases depending on how well the placement is optimized. The MCM-D cases are heavier than the MCM-L due to the presence of an Alumina substrate. This trade-off analysis has shown that one of the two MCM-C versions would be the appropriate choice for this unit. This approach offers a 3X reduction in size, reduced mass, and good thermal characteristics. The increase in cost compared with the SMT technology is negligible. Additionally, ceramic has good structural characteristics, doesn't outgas and has proven reliability. This conclusion was reached by investing less than a one day effort using the MSDA tool, and without investing in costly prototyping of various approaches. About half the time was used to put the component data into the MSDA library. The remainder of the time was used in iterating the design.
HIGH DENSITY ELECTRONIC PACKAGING TECHNOLOGY IMPLEMENTATION The implementation of these technologies in future spacecraft may be inhibited by the lack of established manufacturing infrastructure. This presents an availability concem for a potential user of MCM technologies and as has been mentioned previously, impacts cost.
Low-cost planetary missions
769
Additionally, the lack of relaibility data and qualification standards will inhibit the insertion of these technologies. Reliability testing guidelines are being developed by the RELTECH program(ref.5). RELTECH is a joint ARPA, 000, NASA. Industry working group which is performing product evaluations and identifying failure mechanisms for various MCM technologies. A goal of this group is to develop a database which will lead to the establishment of testing. qualification and screening procedures. Cost effective solutions for testing and qualifying any MCM technology must be sought. During an Advanced Electronic Packaging workshop hosted by JPL and MCC in June 1993 many industrial participants expressed the need to change space qualification practices. Many examples were given of unecessary requirements which drove up costs and inhibited technological innovations.
ACKNOWLEDGMENTS
The work described here was carried out at the Jet Propulsion Laboratory, California Institute of Technology under contract with the National Aeronautics and Space Administration, through sponsorship of NASA'S Office of Advanced Concepts and Technology and the Office of Science. We also appreciate the support John McNamee of the Mars Surface Exploration Pre-Project. REFERENCES 1. Personal Communication with Dr. R. Jones, JPL 2. G. Messner. I. Turlik, J. Balde, P. Garrou, Thin Film Multichip Modules, ISHM, 1990. 3. Proceedings of the 1993 International Conference on Multichip Modules, ISH/IEPS, Denver CO, April 1993. 4. Multichip Systems Design Advisor Users Handbook. MCC. 5. RELTECH Validation Plan Rev. 2.1, John Evans, NASA Code QE.