The capacitance of deep diffused planar junctions

381

NOTES

Buried

N+

P Substrate FIG. 3. Cross-section through typical SIC transistor.

processing time that would justify its incorporation into future production processes. are due to the Directors of The Plessey Company Ltd. for permission to publish this

Acknowledgment-Thanks note.

G. R. M. THOMAS Allen Clark Research Centre The PIessty Company Limited &swell, Towcester Northants, England REFERENCE 1. D. R. KERRet al., IBM Jl Res. Dev. 8, 376 (1964).

diffusant and it is shown that values computed from this agree reasonably well with experimental results. KENNEDY and O’BRIEN(~) have derived expressions for the sideways spreading of the diffusant in the planar diffusion technique. The diffusant does not penetrate as far sideways as it does into the bulk material but in order to simplify the calculations a junction shape as in Fig. 1 will be assumed.

Contact

Solid-State Electronics Pergamon Press 1968. Vol. 11,

pp. 381-382.

Printed in Great Britain

The capacitance of deep diffused planat junctions (Received 5 September 1967) AN IMPORTANT parameter in semiconductor device design is the junction capacitance. In deeply diffused planar devices the spreading of the diffusant under the protective oxide layer can increase the junction area considerably above that of the opening in the diffusion mask, and this can lead to unexpectedly large values of the junction capacitance. An approximate expression is obtained here for the capacitance due to this spreading of the

FIG. 1. Diode junction geometry. In addition the distance of the sides of the depletion layer from the junction will be considered to be identical for the plane and curved regions of the junction. The total junction capacitance, C,, then, is given by the capacitance of the plane part of the junction, C,, in parallel with the capacitance of the curved part of the junction under the oxide layer, Cc. c,

= c,+c,

(1)

382

NOTES

Circular junction

Experimental

Now C, is the capacitance of a circular parallel plate capacitor of radius, R. c,

plane

co K,=R2 = ~ w,

(2)

W, is the total depletion layer thickness is the dielectric constant of silicon. the capacitance of a ‘quarter toroid’ and by q,K,rr2R cc = ln 5-R/2 + (x, - Wd

Where and K, C, is is given

7rR/2+(xj+

W,)

Circular diodes with radii of 0.005 and 0.020 in. and junction depths of 50 TVwere made using the planar technique and their C-V characteristics were measured. The experimental characteristics were compared with values calculated from equation (4) using values obtained from LAWRENCE and WARNER(~) for the depletion layer widths. The results are shown in Fig. 2. It can be seen that IO’

1

where xj is the junction depth, Wl the width of the depletion layer on the highly doped side of the junction and W2 the width of the depletion layer on the lowly doped side of the junction. Hence C, = q,K,rR

Rectangular junction With a junction of sides a and b, C, is the capaciof a plane parallel plate capacitor of area ab.

tance

c,

c,K,ab = w,

(5)

c

= 2~K&a

+ b) +2~Kp(xj

b,as.

”

FIG. 2. The experimental and theoretical diode capacitance with reverse bias. 0

Circular diode of diameter 0.040 in.

variation

of

;

+ Circular diode of diameter 0.010 in.;

C, is the capacitance of a semicylindrical capacitor of radii (xj- W,) and (x,+ W,) and total length capacitor 2(a+b) in p ara 11e 1 with a hemispherical of radii (xi- WJ and (Xj+ W,). c

Reverse

+ Ws)(Xj - WI) w

-

Calculated from equation (4).

despite the assumptions made in theoretical capacitances very close obtained between the theoretical and capacitances. I’.

deriving the agreement is experimental R. WILSON

Semiconductor Engineering Dept. AEI-Thorn Semiconductors Ltd. Carholme Road Lincoln, U.K.

Hence C, = q,R, ab + 2rr(x, + Wg)(xj - WI) +

References

X w,

1. D. P.

KENNEDY and R. R. O’BRIEN,

IBM Jl Res. Dev. 9, 179 (1965). 2. H. LAWFSINCEand R. M. WARNER, Bell. Syst. tech. J. 39, 389 (1960).