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The conversion of BCD coded words into binary numbers
The conversion of BCD coded words into binary numbers by C. van Holten t
An example is given of a static BCD to binary code convertor with 4 decades input and 14 binary outputs. It is shown that the table look-up principle leads to a ROM with about 140 k bits, and that the use of smaller ROMS becomes complicated, leading to many circuits in cascade and a rather long delay. The cellular array of adders is described and some simplifications are discussed. By taking into account "don't happen" situations, using a tree structure a circuit as simple as possible (half adders and OR gates as a replacement for full adders) an economical and quick solution is found.
1. Introduction For small BCD coded words, e.g. with 3 decades, a read-only memory may be used in the well-known table look-up method. The BCD coded words are used as addresses for the locations in which the binary equivalent has been stored. For 3 decades, there are 12 input lines and 10 output lines, and since only 10~ input words are possible, the ROM consists of 10,000 bits. For 4 decades, however, there are 16 input lines, 104 input words and 14 output lines, which results in a ROM with 140,000 bits. This is at present not realisable. If the ROM is broken up into smaller parts, these may be cascaded. An example is the Texas Instruments 74185. For4 decades, however, 11 units are needed and the maximum delay time is 280 ns. On the other hand, a programmable logic array is too small to be used. In this paper, another method will be described, making use of full adders in a cellular array, and as will be shown, derivations from this, namely half adders and OR gates. The overall result is a delay time of about 100 ns and a small number of circuits. If the code convertor is integrated on a single chip, the advantages are considerable.
2.
Implementation
To begin with, it may be clear that the standard solutions for this type of problem, namely truth tables and Karnaugh maps are too cumbersome to be used. A table would consist of 10,000 lines and 14 outputs, not to speak of maps with 65,536 squares, of which 55,536 are "don't happen" conditions. In fact, the method used is to split up the BCD inputs into their binary equivalents as shown in Table I. It turns out that the 16 BCD inputs l through 8, l0 through 80, tTechnische Hogeschool, Delft, The Netherlands.
100 through 800 and 1000 through 8000 may be translated into 48 outputs, and if these outputs are connected to rows of full adders, the diagram of Fig. 1 has been derived. Each full adder has 3 inputs: A, B and at the top and at the right, respectively and 2 outputs: sum at the bottom and Co at the left. Some of these full adders are used as half adders by connecting any input to the 'O' level. Since the maximum value of the input word is 10,000, the last carry (16,384) may never occur. As will be shown later, the use of half adders and the deletion of carry outputs may be used to economise in the amount of circuitry. This straightforward method leads to 33 full adders and I0 half adders. The latter may be full adders with one input at the 'O' level, as described above. The circuit may be built from quad full ladders (e.g. type 7483) in which case 12 are needed. [If in a row less than nx4 adders are needed, all unused inputs have to be connected to the 'O' level]. Of course, this circuit may be improved in many ways.
3.
Development
At first, not all input signals can be '1' at the same time. As shown in Table II, the input values 20 and 80, 400 and 800, 2000 and 8000, 4000 and 8000 can never occur at the same time and may therefore be fed into 2-input OR gates. The values 2000, 4000, 8000 can be combined in 2 ways (not at the same time!). In this way, the number of inputs of the decoder is 41 instead of 48, requiring less adders. In Fig. 2 these combinations are shown, and in Fig. 3 the complete diagram has been sketched, consisting of 29 full adders, 6 half adders (or 35 full adders) and 2 2-input OR gates. Note that not all possibilities in Fig. 2 have been used, since the number of inputs available at the adders is more than is needed. If some full adders are replaced by half adders, a combination with OR gates would be possible; if quad
MICROELECTRONICS JOURNAL Vol. 11 No. 2 ,c~ 1980 Mackintosh Pt,blications Ltd., Luton.
29
T h e c o n v e r s i o n of BCD c o d e d w o r d s into b i n a r y n u m b e r s continued from page 29
BCD'n"III ~OU{ ary
2
2
4
8
16
32
64
128
256
512 1 0 2 4 2 0 4 8 4 0 9 (
4-
4
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3
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Inputs to 1 decoder
2
3
Table I
5
4
5
6
5
1 Total
~,8hputs
Comparison B C D inputs vs binary outputs
Fig. 1 Code convertor BCD to binary with serial configuration, 5 levels, 33 full adders, 10 half adders BCD
BIN
30
8000 ~00
2000
8192 /.096 20~.8 lO?t.
1000 800
/,00
200
512
256
12~
10080
~0
20
61.
32
16
10 8
8
&
2
4
2
Table II
1
BCD i n ' ~ 1
Comparison, if"dont' happen" combinations are taken into account
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BCD
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Fig. 3
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1
1 Total ~,I inputs
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8192 /~)6
20¢B
256
12B
6¢
3Z
16
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¢
2
Code convertor BCD to binary with serial configuration, 4 levels, 29 full adders, 6 half adders, 2 OR gates 31
The
c o n v e r s i o n of BCD
coded
i n t o b i n a r y n u m b e r s continued from page 31
words
100
1
2 4
61.
200
8
8
10
j
" 64 " 128 " 16
= 2. - 'G
20 ~
~0
4
16 800
" 3Z
IZB " 256 32 " 517_
80
1000
2000
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5
1000
32 6t~ lZ8
256 512
k__2 16
2000
12g 256 512 102t~
~000
8000 "
4000 256 512 lOZtt. = 20t~8 k096
8 32 6~ 128 256 512 16 128 256 512 102g 64 32 128 256 512 102~ Z0~8 4096
BOO0
Fig. 2 Splitting up of 16 BCD-inputs into41 binary inputs using "dont't happen" combinations
full adders are used, there is no advantage in this method. O f course, there are now less adders, and at the same time the n u m b e r of levels, e.g. the number of cascades, is 4 instead of 5, as was the case in Fig. 1 This leads to a second improvement. In Fig. 4 a comparison has been made of 2 modes of cascading. At the left each new input is fed into a new adder, so ( n - l ) adders are needed for n inputs. At the right a 'tree structure' has been used, in which the same number of adders is used, but the delay time is reduced. T h e principle is described by Kingsbury. It is amazing, however, to see how many times in the literature diagrams are shown with the structure as shown at the left. So-called cellular arrays are rather popular, e.g. in multipliers since the integration is easy, but the penalty is a longer delay time. In Fig. 5 the tree structure is shown. It uses as many circuits as in Fig. 1 ( " d o n ' t happens" are not taken into account). T h e r e are now only 3 levels, however. If Figs. 3 and 5 are combined, we combine the principles and find less levels as well as less circuits. This has been shown in Fig. 6. T h e use of quad full adders is not always possible, since neat rows do not always occur. If, however, this complete circuit is integrated on a chip with 32
1 6 + 1 4 + 2 = 3 2 pins, all the advantages are realisable. If this integration takes place, a lot of circuits may be simplified, namely half adders consisting of only one e x - O R gate and an A N D gate may replace full adders. If 2 inputs are present, and no carry can occur, (see Fig. 1 at the left for 16,384) a simple O R gate may be used. As a demonstration o f how these simplifications can lead to far better circuits, in Figs. 7 and 8 a 2-decade B C D to 7 bits binary convertor is shown. Instead of 2 quad full adders with the equivalent of 48 gates, now only 3 half adders and 2 O R gates are used, which is equivalent to 26 gates only. In integrated form, the circuit becomes simpler and cheaper. T h e a u t h o r has not yet tried to use carry look ahead generators for still better results. Their use would speed up the output, but more circuits would be needed. 4. A c k n o w l e d g m e n t I w o u l d like t o t h a n k D r J . O b d r z & l e k o f P r a g u e U n i v e r s i t y f o r m a n y h e l p f u l ideas in p r e p a r i n g t h i s paper. 5.
Reference
[1] Kingsbury, Electronics Letters,7, 10,277 (1971).
1input
I
2inputs
Oadder~ Olevels
- ~
ladder,
1 level
2 adders 2levels
2levels
4inputs
3adders 2 levels
3 levels
Fig. 4 4 adders 4 levels
5 inputs
8CD
BIN.
Eor~
~92
Fig. 5
4096
4000
20~8
4 adders 2 levels
.=• -2 ~
6 inputs
1024
5 adders 3 levels
5adders 5levels
2000 ~00 800
z,O0
512
Serial and parallel configurations
256
200
128
100 80
40
20
6~
32
16
10
B
4
2
1
8
~
2
1
Code convertor BCD to binary with parallel configuration, 3 levels, 33 full adders, 10 half adders 33
The conversion
of BCD coded w o r d s into
binary numbers continued from page 33
BCD
BIN8192
Fig. 6
4096
2048
1024
51Z
256
128
61,
32
16
8
4
2
I
Code convertor BCD to binary with a parallel configuration, 3 levels, 29 full adders, 6 half adders, 2 O R gates
BCD 80
40
20 10 8 ,
4
BCD80
2O
40
I
4- !1,18I,
8r
10 8
1
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64
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32
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BINARY Fig. 7
34
64
32
16
[ 8
I
4
2
Using 2 quad full adder 7483 for a 2-decade to 7 bit convertor (equivalent to 48 gates)
BIN 64 Fig. 8
32
16
8
4
2
Using 3 full adders, 3 half adders and 2 OR gates for the same convertor (equivalent to 26 gates)
An example is given of a static BCD to binary code convertor with 4 decades input and 14 binary outputs. It is shown that the table look-up principle leads to a ROM with about 140 k bits, and that the use of smaller ROMS becomes complicated, leading to many circuits in cascade and a rather long delay. The cellular array of adders is described and some simplifications are discussed. By taking into account "don't happen" situations, using a tree structure a circuit as simple as possible (half adders and OR gates as a replacement for full adders) an economical and quick solution is found.
1. Introduction For small BCD coded words, e.g. with 3 decades, a read-only memory may be used in the well-known table look-up method. The BCD coded words are used as addresses for the locations in which the binary equivalent has been stored. For 3 decades, there are 12 input lines and 10 output lines, and since only 10~ input words are possible, the ROM consists of 10,000 bits. For 4 decades, however, there are 16 input lines, 104 input words and 14 output lines, which results in a ROM with 140,000 bits. This is at present not realisable. If the ROM is broken up into smaller parts, these may be cascaded. An example is the Texas Instruments 74185. For4 decades, however, 11 units are needed and the maximum delay time is 280 ns. On the other hand, a programmable logic array is too small to be used. In this paper, another method will be described, making use of full adders in a cellular array, and as will be shown, derivations from this, namely half adders and OR gates. The overall result is a delay time of about 100 ns and a small number of circuits. If the code convertor is integrated on a single chip, the advantages are considerable.
2.
Implementation
To begin with, it may be clear that the standard solutions for this type of problem, namely truth tables and Karnaugh maps are too cumbersome to be used. A table would consist of 10,000 lines and 14 outputs, not to speak of maps with 65,536 squares, of which 55,536 are "don't happen" conditions. In fact, the method used is to split up the BCD inputs into their binary equivalents as shown in Table I. It turns out that the 16 BCD inputs l through 8, l0 through 80, tTechnische Hogeschool, Delft, The Netherlands.
100 through 800 and 1000 through 8000 may be translated into 48 outputs, and if these outputs are connected to rows of full adders, the diagram of Fig. 1 has been derived. Each full adder has 3 inputs: A, B and at the top and at the right, respectively and 2 outputs: sum at the bottom and Co at the left. Some of these full adders are used as half adders by connecting any input to the 'O' level. Since the maximum value of the input word is 10,000, the last carry (16,384) may never occur. As will be shown later, the use of half adders and the deletion of carry outputs may be used to economise in the amount of circuitry. This straightforward method leads to 33 full adders and I0 half adders. The latter may be full adders with one input at the 'O' level, as described above. The circuit may be built from quad full ladders (e.g. type 7483) in which case 12 are needed. [If in a row less than nx4 adders are needed, all unused inputs have to be connected to the 'O' level]. Of course, this circuit may be improved in many ways.
3.
Development
At first, not all input signals can be '1' at the same time. As shown in Table II, the input values 20 and 80, 400 and 800, 2000 and 8000, 4000 and 8000 can never occur at the same time and may therefore be fed into 2-input OR gates. The values 2000, 4000, 8000 can be combined in 2 ways (not at the same time!). In this way, the number of inputs of the decoder is 41 instead of 48, requiring less adders. In Fig. 2 these combinations are shown, and in Fig. 3 the complete diagram has been sketched, consisting of 29 full adders, 6 half adders (or 35 full adders) and 2 2-input OR gates. Note that not all possibilities in Fig. 2 have been used, since the number of inputs available at the adders is more than is needed. If some full adders are replaced by half adders, a combination with OR gates would be possible; if quad
MICROELECTRONICS JOURNAL Vol. 11 No. 2 ,c~ 1980 Mackintosh Pt,blications Ltd., Luton.
29
T h e c o n v e r s i o n of BCD c o d e d w o r d s into b i n a r y n u m b e r s continued from page 29
BCD'n"III ~OU{ ary
2
2
4
8
16
32
64
128
256
512 1 0 2 4 2 0 4 8 4 0 9 (
4-
4
+
8 10
•
*
20
-
40
*
•
80 .....
÷
-loo
.......
*
: ..........
200
:---:
*
+
+
400
÷
~
800 . . . . . . . . .
.............................
+
+ ~
+
*
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1000
.
.
.
.
. 4-
200O ÷
4000 8000
. +
÷
"f
+
+
4-
-t-
t
+
+
÷
÷
*
6
5
3
2
4-
Inputs to 1 decoder
2
3
Table I
5
4
5
6
5
1 Total
~,8hputs
Comparison B C D inputs vs binary outputs
Fig. 1 Code convertor BCD to binary with serial configuration, 5 levels, 33 full adders, 10 half adders BCD
BIN
30
8000 ~00
2000
8192 /.096 20~.8 lO?t.
1000 800
/,00
200
512
256
12~
10080
~0
20
61.
32
16
10 8
8
&
2
4
2
Table II
1
BCD i n ' ~ 1
Comparison, if"dont' happen" combinations are taken into account
Z
4
8
16 32
64 128 2 5 6 512 1024 2 0 4 8 4 0 9 6
+
2
+
4 8
f
10
*
+
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40 ZO
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8000 Inputs tc 1 decoder
BCD
BIN.
Fig. 3
Z
3
5
3
102/,
512
5
5
5
4
4
Z
1
1 Total ~,I inputs
I
8192 /~)6
20¢B
256
12B
6¢
3Z
16
B
¢
2
Code convertor BCD to binary with serial configuration, 4 levels, 29 full adders, 6 half adders, 2 OR gates 31
The
c o n v e r s i o n of BCD
coded
i n t o b i n a r y n u m b e r s continued from page 31
words
100
1
2 4
61.
200
8
8
10
j
" 64 " 128 " 16
= 2. - 'G
20 ~
~0
4
16 800
" 3Z
IZB " 256 32 " 517_
80
1000
2000
~
5
1000
32 6t~ lZ8
256 512
k__2 16
2000
12g 256 512 102t~
~000
8000 "
4000 256 512 lOZtt. = 20t~8 k096
8 32 6~ 128 256 512 16 128 256 512 102g 64 32 128 256 512 102~ Z0~8 4096
BOO0
Fig. 2 Splitting up of 16 BCD-inputs into41 binary inputs using "dont't happen" combinations
full adders are used, there is no advantage in this method. O f course, there are now less adders, and at the same time the n u m b e r of levels, e.g. the number of cascades, is 4 instead of 5, as was the case in Fig. 1 This leads to a second improvement. In Fig. 4 a comparison has been made of 2 modes of cascading. At the left each new input is fed into a new adder, so ( n - l ) adders are needed for n inputs. At the right a 'tree structure' has been used, in which the same number of adders is used, but the delay time is reduced. T h e principle is described by Kingsbury. It is amazing, however, to see how many times in the literature diagrams are shown with the structure as shown at the left. So-called cellular arrays are rather popular, e.g. in multipliers since the integration is easy, but the penalty is a longer delay time. In Fig. 5 the tree structure is shown. It uses as many circuits as in Fig. 1 ( " d o n ' t happens" are not taken into account). T h e r e are now only 3 levels, however. If Figs. 3 and 5 are combined, we combine the principles and find less levels as well as less circuits. This has been shown in Fig. 6. T h e use of quad full adders is not always possible, since neat rows do not always occur. If, however, this complete circuit is integrated on a chip with 32
1 6 + 1 4 + 2 = 3 2 pins, all the advantages are realisable. If this integration takes place, a lot of circuits may be simplified, namely half adders consisting of only one e x - O R gate and an A N D gate may replace full adders. If 2 inputs are present, and no carry can occur, (see Fig. 1 at the left for 16,384) a simple O R gate may be used. As a demonstration o f how these simplifications can lead to far better circuits, in Figs. 7 and 8 a 2-decade B C D to 7 bits binary convertor is shown. Instead of 2 quad full adders with the equivalent of 48 gates, now only 3 half adders and 2 O R gates are used, which is equivalent to 26 gates only. In integrated form, the circuit becomes simpler and cheaper. T h e a u t h o r has not yet tried to use carry look ahead generators for still better results. Their use would speed up the output, but more circuits would be needed. 4. A c k n o w l e d g m e n t I w o u l d like t o t h a n k D r J . O b d r z & l e k o f P r a g u e U n i v e r s i t y f o r m a n y h e l p f u l ideas in p r e p a r i n g t h i s paper. 5.
Reference
[1] Kingsbury, Electronics Letters,7, 10,277 (1971).
1input
I
2inputs
Oadder~ Olevels
- ~
ladder,
1 level
2 adders 2levels
2levels
4inputs
3adders 2 levels
3 levels
Fig. 4 4 adders 4 levels
5 inputs
8CD
BIN.
Eor~
~92
Fig. 5
4096
4000
20~8
4 adders 2 levels
.=• -2 ~
6 inputs
1024
5 adders 3 levels
5adders 5levels
2000 ~00 800
z,O0
512
Serial and parallel configurations
256
200
128
100 80
40
20
6~
32
16
10
B
4
2
1
8
~
2
1
Code convertor BCD to binary with parallel configuration, 3 levels, 33 full adders, 10 half adders 33
The conversion
of BCD coded w o r d s into
binary numbers continued from page 33
BCD
BIN8192
Fig. 6
4096
2048
1024
51Z
256
128
61,
32
16
8
4
2
I
Code convertor BCD to binary with a parallel configuration, 3 levels, 29 full adders, 6 half adders, 2 O R gates
BCD 80
40
20 10 8 ,
4
BCD80
2O
40
I
4- !1,18I,
8r
10 8
1
J'2
4.
-tl,
64
H
32
I
I
:t
l_.
2
J'4"
1__(
16
4
",,4
_; L-_.__
|
BINARY Fig. 7
34
64
32
16
[ 8
I
4
2
Using 2 quad full adder 7483 for a 2-decade to 7 bit convertor (equivalent to 48 gates)
BIN 64 Fig. 8
32
16
8
4
2
Using 3 full adders, 3 half adders and 2 OR gates for the same convertor (equivalent to 26 gates)