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The distribution of electromigration failures
World Abstracts on Microelectronics and Reliability
Modeling IC failure rates. JOHN HEALY. Proc. a. Reliab. Maintainab. Syrup., 307 (1986). Bell Communications Research (Bellcore) provides the Operating Telephone Companies (OTCs) with technical support to continue their leadership in the telecommunications field. In particular, Bellcore provides methods for reliability prediction, an important element in the process of selecting m a n y of the products in the multi-billion dollar electronic equipment purchases made by the O T C s each year. The most commonly used method of reliability prediction uses device failure rates as the foundation of the reliability prediction process for replaceable units, such as circuit packs. It is therefore important to have accurate device failure rates. The purpose of this paper is to describe an approach that Bellcore has developed to obtain failure rates for Integrated Circuits (ICs) of varying complexity (e.g. number of bits) based on data from several manufacturers of telecommunications equipment and from several companies which provide telecommunications service. This paper describes the newly proposed failure rates for ICs and the statistical models used to obtain them. A companion paper describes the data collected and the engineering considerations that were used in the analysis. The models allow prediction of the IC failure rates as functions of the complexity of the IC. The models can also be used to determine if the data support prior beliefs of the behaviour of IC failure rates. A practical VLSI characterization and failure analysis system for the IC user. RANDY KING and JOHN HlATT. 24 a. Proc. IEEE Reliab. Phys. Syrup., 87 (1986). Instrumentation for characterization and failure analysis of VLSI devices is described. The system combines functional and parametric test capability with voltage contrast imaging techniques. Digital signal processing allows comparison of good and bad devices to isolate faults. Reasonable cost and complexity makes the system appropriate for the IC user rather than limiting it to development applications. Specific application histories are presented. Comprehensive model for humidity testing correlation. D. STEWART PECK. 24 a. Proc. IEEE Reliab. Phys. Symp., 44 (1986). This paper reviews all published life in humidity conditions vs life at 85°C/85~oRH for epoxy packages; 61 data points are used. An acceleration formula is described which provides direct extrapolation from test results in autoclave tests at up to at least 140°C to low-humidity down to below 30~oRH. This formula compares favorably with previouslypublished formulae. The possible effect of the Tg of the epoxy is recognized, and other high-temperature and low-humidity effects are disclosed. Recommendations are made for future tests, replacing 1000 hours at 85°C/85~oRH with a 20 hour test at 140°C/100~RH, to reduce test time and increase test usefulness. The distribution of electromigration failures. DONALD J. LACOMBEand EARL L. PARKS. 24 a. Proc. 1EEE Reliab. Phys. Symp., 1 (1986). This paper presents the results of an evaluation of the statistical distribution of electromigration test failures. Large scale life tests were carried out and the nature of the failure distributions were determined for lines of varying length and width. In all cases, the distribution were found to be log-normal down to at least the 0.3% failure point. Possible reasons for these results and their implications with regard to the design of a cost effective electromigration testing program are discussed. Infrared microscopy as applied to failure analysis of P-DIP devices. STEPHEN H. LEWIS. 24 a. Proc. IEEE Reliab. Phys. Syrup., 99 (1986). Infrared microscopy is an important tool to the failure analyst, and its uses in failure mode identification are becoming more varied and numerous. Recent advances in equipment have enabled high magnification examination with very good resolution when analyzing plastic encapsu-
583
lated devices from the backside of the die. This paper will discuss various anomalies observable with this technique as well as sample preparation techniques and a description of the IR equipment used.
Power GaAs FET RF life test using temperaturecompensated electrical stressing. K. J. RUSSELL and J. K. DHIMAN. 24 a. Proc. IEEE Reliab. Phys. Syrup., 150 (1986). GaAs FETs were aged in RF operation, while keeping the electrical stress on the FETs like that in a typical application. Lifetimes measured were significantly lower than those predicted by life tests using dc bias only. Significant dependence of lifetimes upon the wafer process lot was found. Voltage screening did not provide more reliable devices. Field and temperature dependent life-time limiting effects of metaI-GaAs interfaces of device structures studied by XPS and electrical measurements. J. WURFL and H. L. HARTNAGEL. 24 a. Proc. IEEE Reliab. Phys. Symp., 138 (1986). Typical Schottky contacts for GaAs devices such as A1 and TiPtAu metallizations have been accelerated-stress tested under bias at room temperature and at temperatures up to 250°C. The influence of these stress tests on the interface properties were studied by XPS sputter profiling and correlated with electrical measurements. Concerning AI contacts it has been found that bias-stressing results in a structural change of the AI layer and that the oxygen concentration at the A I - G a A s transition depends both on the polarity of bias stressing and on the GaAs surface treatment before A1 metallization. These effects are quite pronounced even at room temperature. TiPtAu contacts are stable at room temperature over the period of investigation (200h), but at elevated temperatures (200°C) a GaAs diffusion into Ti and a subsequent Ti diffusion into Ga vacancies could be observed. This results in a catastrophic bias dependent degradation of the I/V characteristics. Impact of ceramic packaging anneal on the reliability of AI interconnects. M. R. LIN and J. T. YUE. 24 a. Proc. IEEE Reliab. Phys. Syrup., 164 (1986). Experimental results show conclusive evidence that stress induced metal voids and Si nodules (both of which originate during wafer processing) grow significantly after Ceramic Packaging (CDIP) glass sealing anneal. Furthermore, the growth of a metal void is almost always accompanied by Si precipitation in its immediate neighborhood. The combination of a metal void and an adjacent silicon nodule was observed to significantly reduce the net metal line cross-sectional area and is highly undesirable for interconnect reliability. In this paper the above phenomenon is fully explained and the effects of C D I P anneal temperature profiles are examined. Reliability characterization of a 3pm CMOS/SOS process. M. PATRICK DUGAN. R C A Rev. 47, 138 (June 1986). A continuing study of advanced short-channel CMOS/SOS arrays has been carried out at the RCA Microelectronics Center (MEC) and at RCA Laboratories, Princeton, N J, since 1981. A technique to assess the reliability of a new process relatively quickly consists of high-temperature accelerated stress testing of ICs by maintaining the temperature at 200°C, while biasing half the inputs at the positive supply voltage and half at ground. The results of these accelerated stress tests, together with device analysis, were used to calculate a failure rate and to determine that time-dependent dielectric breakdown (TDDB) is the principal failure mechanism. No mechanism unique to the C M O S / S O S technology has been observed. Moisture determination in IC packages by conductance technique. N. K. ANNAMALAI.24 a. Proc. IEEE Reliab. Phys. Syrup., 61 (1986). An a.c. conductance technique using a lockin-amplifier (LIA) is described. The conductance technique is a non-destructive technique and uses the die as a sensor. O u r
Modeling IC failure rates. JOHN HEALY. Proc. a. Reliab. Maintainab. Syrup., 307 (1986). Bell Communications Research (Bellcore) provides the Operating Telephone Companies (OTCs) with technical support to continue their leadership in the telecommunications field. In particular, Bellcore provides methods for reliability prediction, an important element in the process of selecting m a n y of the products in the multi-billion dollar electronic equipment purchases made by the O T C s each year. The most commonly used method of reliability prediction uses device failure rates as the foundation of the reliability prediction process for replaceable units, such as circuit packs. It is therefore important to have accurate device failure rates. The purpose of this paper is to describe an approach that Bellcore has developed to obtain failure rates for Integrated Circuits (ICs) of varying complexity (e.g. number of bits) based on data from several manufacturers of telecommunications equipment and from several companies which provide telecommunications service. This paper describes the newly proposed failure rates for ICs and the statistical models used to obtain them. A companion paper describes the data collected and the engineering considerations that were used in the analysis. The models allow prediction of the IC failure rates as functions of the complexity of the IC. The models can also be used to determine if the data support prior beliefs of the behaviour of IC failure rates. A practical VLSI characterization and failure analysis system for the IC user. RANDY KING and JOHN HlATT. 24 a. Proc. IEEE Reliab. Phys. Syrup., 87 (1986). Instrumentation for characterization and failure analysis of VLSI devices is described. The system combines functional and parametric test capability with voltage contrast imaging techniques. Digital signal processing allows comparison of good and bad devices to isolate faults. Reasonable cost and complexity makes the system appropriate for the IC user rather than limiting it to development applications. Specific application histories are presented. Comprehensive model for humidity testing correlation. D. STEWART PECK. 24 a. Proc. IEEE Reliab. Phys. Symp., 44 (1986). This paper reviews all published life in humidity conditions vs life at 85°C/85~oRH for epoxy packages; 61 data points are used. An acceleration formula is described which provides direct extrapolation from test results in autoclave tests at up to at least 140°C to low-humidity down to below 30~oRH. This formula compares favorably with previouslypublished formulae. The possible effect of the Tg of the epoxy is recognized, and other high-temperature and low-humidity effects are disclosed. Recommendations are made for future tests, replacing 1000 hours at 85°C/85~oRH with a 20 hour test at 140°C/100~RH, to reduce test time and increase test usefulness. The distribution of electromigration failures. DONALD J. LACOMBEand EARL L. PARKS. 24 a. Proc. 1EEE Reliab. Phys. Symp., 1 (1986). This paper presents the results of an evaluation of the statistical distribution of electromigration test failures. Large scale life tests were carried out and the nature of the failure distributions were determined for lines of varying length and width. In all cases, the distribution were found to be log-normal down to at least the 0.3% failure point. Possible reasons for these results and their implications with regard to the design of a cost effective electromigration testing program are discussed. Infrared microscopy as applied to failure analysis of P-DIP devices. STEPHEN H. LEWIS. 24 a. Proc. IEEE Reliab. Phys. Syrup., 99 (1986). Infrared microscopy is an important tool to the failure analyst, and its uses in failure mode identification are becoming more varied and numerous. Recent advances in equipment have enabled high magnification examination with very good resolution when analyzing plastic encapsu-
583
lated devices from the backside of the die. This paper will discuss various anomalies observable with this technique as well as sample preparation techniques and a description of the IR equipment used.
Power GaAs FET RF life test using temperaturecompensated electrical stressing. K. J. RUSSELL and J. K. DHIMAN. 24 a. Proc. IEEE Reliab. Phys. Syrup., 150 (1986). GaAs FETs were aged in RF operation, while keeping the electrical stress on the FETs like that in a typical application. Lifetimes measured were significantly lower than those predicted by life tests using dc bias only. Significant dependence of lifetimes upon the wafer process lot was found. Voltage screening did not provide more reliable devices. Field and temperature dependent life-time limiting effects of metaI-GaAs interfaces of device structures studied by XPS and electrical measurements. J. WURFL and H. L. HARTNAGEL. 24 a. Proc. IEEE Reliab. Phys. Symp., 138 (1986). Typical Schottky contacts for GaAs devices such as A1 and TiPtAu metallizations have been accelerated-stress tested under bias at room temperature and at temperatures up to 250°C. The influence of these stress tests on the interface properties were studied by XPS sputter profiling and correlated with electrical measurements. Concerning AI contacts it has been found that bias-stressing results in a structural change of the AI layer and that the oxygen concentration at the A I - G a A s transition depends both on the polarity of bias stressing and on the GaAs surface treatment before A1 metallization. These effects are quite pronounced even at room temperature. TiPtAu contacts are stable at room temperature over the period of investigation (200h), but at elevated temperatures (200°C) a GaAs diffusion into Ti and a subsequent Ti diffusion into Ga vacancies could be observed. This results in a catastrophic bias dependent degradation of the I/V characteristics. Impact of ceramic packaging anneal on the reliability of AI interconnects. M. R. LIN and J. T. YUE. 24 a. Proc. IEEE Reliab. Phys. Syrup., 164 (1986). Experimental results show conclusive evidence that stress induced metal voids and Si nodules (both of which originate during wafer processing) grow significantly after Ceramic Packaging (CDIP) glass sealing anneal. Furthermore, the growth of a metal void is almost always accompanied by Si precipitation in its immediate neighborhood. The combination of a metal void and an adjacent silicon nodule was observed to significantly reduce the net metal line cross-sectional area and is highly undesirable for interconnect reliability. In this paper the above phenomenon is fully explained and the effects of C D I P anneal temperature profiles are examined. Reliability characterization of a 3pm CMOS/SOS process. M. PATRICK DUGAN. R C A Rev. 47, 138 (June 1986). A continuing study of advanced short-channel CMOS/SOS arrays has been carried out at the RCA Microelectronics Center (MEC) and at RCA Laboratories, Princeton, N J, since 1981. A technique to assess the reliability of a new process relatively quickly consists of high-temperature accelerated stress testing of ICs by maintaining the temperature at 200°C, while biasing half the inputs at the positive supply voltage and half at ground. The results of these accelerated stress tests, together with device analysis, were used to calculate a failure rate and to determine that time-dependent dielectric breakdown (TDDB) is the principal failure mechanism. No mechanism unique to the C M O S / S O S technology has been observed. Moisture determination in IC packages by conductance technique. N. K. ANNAMALAI.24 a. Proc. IEEE Reliab. Phys. Syrup., 61 (1986). An a.c. conductance technique using a lockin-amplifier (LIA) is described. The conductance technique is a non-destructive technique and uses the die as a sensor. O u r