- Email: [email protected]
The DRS chip: cheap waveform digitizing in the GHz range
ARTICLE IN PRESS
Nuclear Instruments and Methods in Physics Research A 518 (2004) 470–471
The DRS chip: cheap waveform digitizing in the GHz range Stefan Ritt* Paul Schrerrer Institute (PSI), OLGA/021, CH-5232 Villigen, Switzerland
Abstract An analog sampling chip is currently under development for fast waveform digitizing of PMT and drift chamber signals for the MEG Experiment at PSI. This experiment searches for the lepton-flavour violating decay m+-e+g with a sensitivity down to 10 13. The first prototype of the chip contains 768 capacitive sampling cells fabricated in a 0.25 mm CMOS process. Sampling takes place with an on-chip generated frequency ranging up to 2.5 GHz. The cells are read out at 40 MHz with an external 12 bit flash ADC. The design of the chip is described and test results from the first prototype are reported. r 2003 Elsevier B.V. All rights reserved. PACS: 07.05.Hd; 07.50.Ek; 85.40. e Keywords: Fast waveform sampling; Signal digitizing; MEG experiment
1. Introduction The MEG experiment [1] utilizes a high-resolution liquid xenon calorimeter and a drift chamber system to detect the decay positron and gamma from a potential m+-e+g decay, respectively. A muon beam with B108 m/s is stopped in a thin target. Since the calorimeter is unsegmented, a high pile-up rate is expected, making waveform digitizing on all PMT channels mandatory. Instead of using commercial flash analog-to-digital converters (FADC), an analog waveform digitizer in the GHz range will be used, which follows an earlier development at PSI [2]. This solution is not only cheaper and requires less power than an FADC, it also delivers high-timing resolution,
*Tel.: +41-56-310-3728; fax: +41-56-310-2199. E-mail address: [email protected] (S. Ritt).
which makes the usage of discriminators and TDCs unnecessary.
2. Principle of operation Since it is very hard to generate and distribute clock signals in the GHz range, the sampling frequency is generated with a series of inverters. A sampling signal propagates through these inverters freely (domino principle). Transmission gates between the inverters make the frequency controllable in a wide range. A special ‘‘tail-biting’’ circuitry ensures that the width of the sampling signal is always four cells wide. Additional ANDgates allow to stop the domino wave in any cell by an external trigger signal. The domino wave runs continuously in a circular fashion, hence the name Domino Ring Sampling chip. Since the storage depth is larger than a typical PMT signal width,
0168-9002/$ - see front matter r 2003 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2003.11.059
ARTICLE IN PRESS S. Ritt / Nuclear Instruments and Methods in Physics Research A 518 (2004) 470–471
0.5-2 ns
Inverter “Domino” chain
Rotating singal
471
Table 1 Basic chip parameters
Input
Current prototype
Final chip
1 768 2.5
9 1024 2.5
0.7
0.2
20 40 — 80
40 26 11 80
Output Shift Register
40 MHz
Fig. 1. Simplified schematic of the DRS chip.
the storage chain acts like an analog pipeline and makes delay cables unnecessary for first-level trigger latencies up to several hundred nanoseconds. Fig. 1 shows the simplified schematic of the chip. Once a signal is stored, it is read out by a shift register at a clock speed of 40 MHz and digitized externally by a flash ADC. Several DRS channels can be multiplexed into a single ADC channel to reduce costs, but with the drawback of an increased readout dead time. The final chip will contain nine channels all driven by the same domino wave, which makes it possible to use the ninth channel for timing calibration. Several chips will be housed on a VME board at a cost of about 30$ (chip) and 30$ (board) per channel for 10,000 channels. Table 1 summarizes the basic chip parameters. It is considered to use two chips in parallel for each set of eight channels. While one chip is read out, the other one is digitizing the input signal, allowing for dead time free operation. The VME board will host in addition to the DRS chip FPGAs and static RAM, making it possible to run the boards in a mode similar to a digital oscilloscope.
3. Test results A first prototype chip was produced and tested recently. The domino wave runs stably between 700 MHz and 2.5 GHz. A timing jitter of 80 ps has been measured. The sampling speed has a tem-
Number of channels/chip Number of cells/channel Maximum sampling speed (GHz) Minimum sampling speed (GHz) Readout speed (MHz) Readout dead time (ms) Signal-to-noise ratio (bit) Timing accuracy at 2.5 GHz (ps)
perature dependence of 0.2%/ C which makes it necessary to regulate it using an external clock and a digital-locked-loop (DLL). A commercial DLL circuit is used to lock all domino waves to an external quartz signal, thus removing any speed variation. While the digital part is working perfectly, the analog readout of the small (200 fF) capacitors is problematic due to large parasitic on-chip capacitances. A revised design will use a modified readout scheme which avoids this problem. The next version is planned for fall 2003 and the final production for 2004. The DAQ system of the MEG experiment will use the DRS chip on all PMT channels running at 2.5 GHz and on all drift chamber channels (cathodes and anodes) at a speed of 500 MHz, delivering an excellent pile-up rejection.
References [1] T. Mori, et al., PSI R-99-05 Experiment Proposal, Paul Scherrer Institute, Villigen, 1999. . [2] C. Bronnimann, et al., Nucl. Instr. and Meth. A 420 (1999) 264.
Nuclear Instruments and Methods in Physics Research A 518 (2004) 470–471
The DRS chip: cheap waveform digitizing in the GHz range Stefan Ritt* Paul Schrerrer Institute (PSI), OLGA/021, CH-5232 Villigen, Switzerland
Abstract An analog sampling chip is currently under development for fast waveform digitizing of PMT and drift chamber signals for the MEG Experiment at PSI. This experiment searches for the lepton-flavour violating decay m+-e+g with a sensitivity down to 10 13. The first prototype of the chip contains 768 capacitive sampling cells fabricated in a 0.25 mm CMOS process. Sampling takes place with an on-chip generated frequency ranging up to 2.5 GHz. The cells are read out at 40 MHz with an external 12 bit flash ADC. The design of the chip is described and test results from the first prototype are reported. r 2003 Elsevier B.V. All rights reserved. PACS: 07.05.Hd; 07.50.Ek; 85.40. e Keywords: Fast waveform sampling; Signal digitizing; MEG experiment
1. Introduction The MEG experiment [1] utilizes a high-resolution liquid xenon calorimeter and a drift chamber system to detect the decay positron and gamma from a potential m+-e+g decay, respectively. A muon beam with B108 m/s is stopped in a thin target. Since the calorimeter is unsegmented, a high pile-up rate is expected, making waveform digitizing on all PMT channels mandatory. Instead of using commercial flash analog-to-digital converters (FADC), an analog waveform digitizer in the GHz range will be used, which follows an earlier development at PSI [2]. This solution is not only cheaper and requires less power than an FADC, it also delivers high-timing resolution,
*Tel.: +41-56-310-3728; fax: +41-56-310-2199. E-mail address: [email protected] (S. Ritt).
which makes the usage of discriminators and TDCs unnecessary.
2. Principle of operation Since it is very hard to generate and distribute clock signals in the GHz range, the sampling frequency is generated with a series of inverters. A sampling signal propagates through these inverters freely (domino principle). Transmission gates between the inverters make the frequency controllable in a wide range. A special ‘‘tail-biting’’ circuitry ensures that the width of the sampling signal is always four cells wide. Additional ANDgates allow to stop the domino wave in any cell by an external trigger signal. The domino wave runs continuously in a circular fashion, hence the name Domino Ring Sampling chip. Since the storage depth is larger than a typical PMT signal width,
0168-9002/$ - see front matter r 2003 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2003.11.059
ARTICLE IN PRESS S. Ritt / Nuclear Instruments and Methods in Physics Research A 518 (2004) 470–471
0.5-2 ns
Inverter “Domino” chain
Rotating singal
471
Table 1 Basic chip parameters
Input
Current prototype
Final chip
1 768 2.5
9 1024 2.5
0.7
0.2
20 40 — 80
40 26 11 80
Output Shift Register
40 MHz
Fig. 1. Simplified schematic of the DRS chip.
the storage chain acts like an analog pipeline and makes delay cables unnecessary for first-level trigger latencies up to several hundred nanoseconds. Fig. 1 shows the simplified schematic of the chip. Once a signal is stored, it is read out by a shift register at a clock speed of 40 MHz and digitized externally by a flash ADC. Several DRS channels can be multiplexed into a single ADC channel to reduce costs, but with the drawback of an increased readout dead time. The final chip will contain nine channels all driven by the same domino wave, which makes it possible to use the ninth channel for timing calibration. Several chips will be housed on a VME board at a cost of about 30$ (chip) and 30$ (board) per channel for 10,000 channels. Table 1 summarizes the basic chip parameters. It is considered to use two chips in parallel for each set of eight channels. While one chip is read out, the other one is digitizing the input signal, allowing for dead time free operation. The VME board will host in addition to the DRS chip FPGAs and static RAM, making it possible to run the boards in a mode similar to a digital oscilloscope.
3. Test results A first prototype chip was produced and tested recently. The domino wave runs stably between 700 MHz and 2.5 GHz. A timing jitter of 80 ps has been measured. The sampling speed has a tem-
Number of channels/chip Number of cells/channel Maximum sampling speed (GHz) Minimum sampling speed (GHz) Readout speed (MHz) Readout dead time (ms) Signal-to-noise ratio (bit) Timing accuracy at 2.5 GHz (ps)
perature dependence of 0.2%/ C which makes it necessary to regulate it using an external clock and a digital-locked-loop (DLL). A commercial DLL circuit is used to lock all domino waves to an external quartz signal, thus removing any speed variation. While the digital part is working perfectly, the analog readout of the small (200 fF) capacitors is problematic due to large parasitic on-chip capacitances. A revised design will use a modified readout scheme which avoids this problem. The next version is planned for fall 2003 and the final production for 2004. The DAQ system of the MEG experiment will use the DRS chip on all PMT channels running at 2.5 GHz and on all drift chamber channels (cathodes and anodes) at a speed of 500 MHz, delivering an excellent pile-up rejection.
References [1] T. Mori, et al., PSI R-99-05 Experiment Proposal, Paul Scherrer Institute, Villigen, 1999. . [2] C. Bronnimann, et al., Nucl. Instr. and Meth. A 420 (1999) 264.