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The Effect of Pad Wear on the Chemical Mechanical Polishing of Silicon Wafers
The Effect of Pad Wear on the Chemical Mechanical Polishing of Silicon Wafers G. Byrne’ (1). B. Mullany’, P.Young2 Dept. of Mechanical Engineering, University College Dublin, Dublin, Ireland Dept. of Mechanical Engineering, Dublin City University, Glasnevin, Dublin, Ireland Received on January 7,1999 1
2
Abstract The Chemical Mechanical Polishing process planarises wafers with a high degree of success, however wear on the polishing pad causes the planarisation rate and the post-process planarity to deteriorate. To date, there has been no method of predicting the effect of this wear on the wafer planarity. Using finite element models of the process for new and worn pads the wafer stress distribution on the wafer surface can be predicted. Equating high stresses to high material removal rates these models predict that the process should become ‘centre slow’ as the pad wears. This correlates well with experimental data. Keywords: Chemical Mechanical Polishing, FEM, Wear
1 INTRODUCTION The fabrication of the latest integrated circuits (IC’s) requires careful construction of multi-layer interconnections between devices on the surface of the silicon wafer. With increasing complexity and speed requirements, the density and number of layers is increasing. Between layers an Inter Layer Dielectric (ILD) is deposited as a conformal layer which must then be planarised to provide a foundation for the next layer of connections and to expose the connections (vias) to lower levels. The fabrication costs of complex IC’s mean that the success of the process is measured by the number of fully functional devices which can be obtained from a single 200 mm or 300 mm diameter silicon wafer.
To date the most successful industrial method of planarising the ILD is that of Chemical Mechanical Polishing (CMP). As the name suggests CMP is a process in which both chemical and mechanical mechanisms interact to planarise the ILD at a satisfactory rate. It is a complex process as the relationship between the chemical and mechanical aspects has been difficult to define and quantify. Due to the lack of basic understanding of the CMP removal mechanisms, the success of the process in industry is dependent on the manufacturer’s ability to consistently operate the process within specific tolerances. In most cases the optimum values chosen for influential process parameters such as process pressure, slurry temperature and pH, and relative velocity are by determined by a trial and error approach in the process development stage. However not all parameters influencing the process planarity capabilities can receive the same meticulous attention. One such factor, which has hitherto received little attention, is that of polishing pad wear. Pad wear is a serious concern as it varies in an uncontrolled manner over time, inducing nonuniform effects on the polishing pad. These effects have an impact on the process itself, inducing undesirable instabilities which affect the ILD removal rates from the wafer surface. In order to improve the
Annals of the ClRP Vol. 48/7/1999
process work must be undertaken to understand the mechanisms and effects of such wear so that the consequences on the process stability may be minimised. PLANARITY OF SILICON WAFERS Good wafer planarity, both local and global, is essential for the dimensional accuracy required at subsequent lithography stages in wafer manufacture. On a global scale, within wafer uniformity of 0.2 pm across a 200 mm wafer is required, and as the wafer size increases even tighter tolerances are necessary. There are two main concerns when considering global planarity of wafers: 1. The edge-ring effect, whereby sharp variations in the ILD removal rate around the edge of the wafer result in a profile as shown in figure 1. 2. The less severe variation in ILD removal rates from the centre to the circumference of the wafer. With respect to the latter, several factors such as downward pressure on the wafer [2,3], inherent polishing pad properties [3], pad wear [4], relative velocities [5,6] and wafer temperature variations [7,8]are all known to affect wafer planarity. Over time the planarity of the processed wafers becomes inadequate and the ILD removal rates too slow as the pad becomes worn. The polishing action causes the soft pad to become smooth 2
30 20 10 0 Distance in from Wafer Edge (mm) Figure 1: Edge ring effect.
143
and ineffective almost immediately. In order to re-dress the surface of the pad, a conditioning arm tracks back and forth over the area where the pad is in contact with the wafer. This tears the surface, restoring the roughness, and also removes some material from the pad. Material removal is proportional to the conditioning density at each point on the pad radius. The deterioration in the quality of the product is a direct result of this pad wear as it alters both the physical properties and geometry of the pad.The majority of the work investigating the relationship between the process parameters and wafer planarity has been of an empirical nature with little mathematical modelling done to compliment the experimental work. For example, experimental work by Curry [9] highlighted the effect of different geometric pad profiles induced by differing pad conditioning density patterns on the global planarity of the polished wafers and the increasing deviations in planarity as the pad aged. It was also found that particular conditioning densities allowed good global planarity to be achieved consistently over the pad life while other conditioning densities induced a deterioration in the capability of the processes to achieve the required planarity. More recently, finite element models by Srinivasa-Murthy et al. [lo] and Wang et al. [ll] have been developed. A typical CMP system was modelled as a static 3-D model and loaded with the process pressure. The von Mises stress distributions along the wafer surface in contact with the pad showed a marked increase near the edge of the wafer, an area where a phenomenon known as the edge ring effect occurs. Here wafer planarity is often poor as a sharp dip in the surface results from higher material removal rates. The models showed that the applied down force causes some radial deformation of the pad during polishing and that it is most noticeable at the edge of the wafer. Although the radial deformation at the wafer edge is only in the order of 0.03 mm. it can induce stresses up to 3 times greater than the average in the region of the wafer edge resulting in significant variations in the von Mises stresses. More interestingly, the calculated von Mises stresses correlated well with observed removal rates, with higher von Mises stresses corresponding to higher removal rates, thus allowing an explanation for the edge ring effect. These models both assumed that the pad geometry was flat and it’s properties consistent across the area of contact between the pad and the wafer. Here, the same approach is used to determine the effects of changes in pad geometry on the material removal rates. POLISHING PAD WEAR Several different polishing pad materials are available to the industry, the pad which is modelled in this work is an ICI 000 porous polyurethane pad. Pad life, determined by the process output, is in the region of 800 wafers after which the ILD removal rates are inadequate and wafer planarity is unacceptable. 3
3.1 Geometric alterations due to pad wear The most noticeable effect of wear is that the geometry of the pad alters with time. It experiences nonuniform thinning across its radius resulting in a concave or ‘dished thickness profile. Figure 2 shows the reduction in pad thickness with wear. A worn pad, at its thinnest, will be approximately 10% thinner than a new pad, however this thinning can be as little as 2% at the outer edge and centre of the polishing pad.
144
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,
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,,
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. 0.3
m
a
Polishing Pad Radius (m) Figure 2: Pad thinning due to wear.
h
Crn
.-
z
4c /
n
--I”
0
U
0.3
0.15 Polishing Pad Radius(rn)
rn
a
Figure 3: Modelled profile of worn pad. From the nature of the geometries it is clear that the distribution of the reaction force from the pad will be considerably different for new and worn pads. As the removal rate of the ILD is dependent on the contact pressure acting on the wafer, a correlation between pad protile and deteriorating planarity is expected.
3.2 Intrinsic pad property alterations due to wear Polishing pad wear also affects both the surface and bulk properties of the polishing pad. Both pad compliance and hardness vary as the pad wears [4]. The compliance values for worn and new lCl000 pads differ by about 13% with worn pads being more compliant, while the shore D hardness values differ by approx. 3% with the worn pad been harder. Both of these properties also vary with pad thickness, thus as a direct result of pad dishing there will be varying compliance and hardness values from the edge of the pad to its centre leading to anisotropic material properties.
4 FINITE ELEMENT MODEL For this investigation, a 2-D finite element model of the system was developed. The model includes the carrier head, wafer and polishing pad as per Figure 4. Two simulation scenarios were modelled, in the first simulation the pad was modelled with a nominally flat surface representing a new pad, while in the second simulation the pad has a dished profile shown in Figure 3. The mechanical properties for the wafer and the polishing pad are listed in Table 1. The values of Young’s Modulus for the both new and worn polishing pads were determined experimentally based on the average of several points measured across the pad radius. In the case of new polishing pads there was no noticeable variation in Young’s Modulus across the pad diameter but there are noticeable variations in the case of a worn pad. Later work will incorporate these radial variations into the finite element model. All other values used are typical values for the material in question. Carrier Head L W a f e r
YI
x
’
I
Figure 4: Schematic of the 2-0finite element model.
Density, p,(Kg/m3)
Polishing pad
Young’s Modulus, E, (Nlm2) 1.16 x 106
800
0.1
Wafer
2.00
7,000
0.3
x
1011
Poisson’s Ratio, y
E -0.02
-0.02
N^
V
a”
i ??
;a v)
-0.1
-0.1
a
z
?,
3 -0.14
-0.14 “, 3
Fi Z
g 3
-0.18
Wafer Radius (mm)
100
0
-0.18
Y
Figure 6: Comparison of wafer normal stress, oy and pad compression, 6p, for new and worn pads. Figure 6 compares the normal stresses, cY, for new and worn pads together with the compression of the pad. It can be seen that the magnitude of the stress normal to the wafers surface is strongly dependent on the deformation of the underlying pad.
5 RESULTS AND DISCUSSION CPU time for a worn pad is considerably longer than that for the new pad. The extra computational time is required to solve the more complex wafer-pad contact, particularly in the initial stage. New pad model Figure 5 shows the variations in the von Mises stress distribution across the wafer radius. As can be clearly seen there are large variations in the stresses towards the edge of wafer which correlates well with previous findings [lo] and [ll]. This edge ring effect extends approximately 5 mm in from the wafer edge, in agreement with measurements from polished wafers. 5.1
5.2 Worn pad model The von Mises stress distribution across the surface of the wafer for contact with a worn pad is distinctly different, figure 5. Variations in the von Mises stress are not just confined to the wafer edges, they exist across the entire wafer surface. The stress isup to 30% higher in the outer 40% of the wafer than at the centre. This suggests that the removal rates at the centre of the wafer are lower, resulting in a convex surface after planarisation. On investigation, the component of the von Mises stress which contributed most to this distribution is the normal stress on the wafer surface, oy.
5.3 Comparison to measured ILD removal rates To validate these results several unpatterned wafers were selected for polishing at various stages during the life of the pad. The thickness of the ILD layer is measured at selected locations on the wafer before and after polishing to determine both the ILD removal rate and post-process planarity. Each wafer tested is polished for 2 minutes. Since all wafers have individual surface profiles as a result of variations within the fabrication process wafers with very similar pre polishing ILD thickness were paired together. The wafer surface profile was established by measuring the ILD layer thickness at 49 locations distributed in concentric rings and at the centre. To show the similarity of a pair of wafers figure 7 shows the measured ILD thickness of wafers 23 and 144. In order to see the differences, the vertical axis has been greatly increased, and as viewing the resulting profile from the side results in several distinct locations appearing to be co-incident, the data is shown in a 3-D view. The wafers are inclined 15 degrees anti-clockwise about the x axis and then rotated 5 degrees around the z-axis.
The first wafer of the pair, wafer 23, was polished early in the pad life, .while the second wafer, wafer 144 was polishe’d at a later stage. The ILD removed from the wafer surface by polishing follows the trend highlighted in the finite element model. Figure 8 shows the average amount
7
ILD Depth Wafer 23
*
$ ,
ILD DeDth Wafer 144
0.15 rn
rn
a, .g
0.1
m E % E
5 50.05 c
P
0 100
Wafer Radius (mm)
0
Figure 5: Comparison of von Mises stress distributions for New and Worn pads.
Figure 7: Measured ILD thicknesses for wafer numbers 23 and 144 (x, y axes not to scale).
145
0%
50%
100%
Radius (%)
Figure 8: Amount of ILD removed from wafer numbers 23 and 144. of ILD removed from the centre and each of the 3 rings on the wafer surface. The wafers have a convex profile on entry, so material removal rates for a new pad are higher in the centre. On examining the ILD removed from wafer 144, which was polished with a pad at about one quarter of its useful life, a distinct reduction in the removal rate at the centre of the wafer was found. This reduction was predicted by the model. The edge ring effect is not visible in these measured results as no readings are available from the 10 mm annulus at the wafer's edge. CONCLUSIONS The finite element models developed show clearly that, with pad wear, the von Mises stresses on the surface of the wafer increase at the outer 40% of the wafer radius. This is accompanied by a reduction of the stresses at the centre of the wafer. As a result it is expected that the process will be 'centre slow' towards the end of pad life. This correlates well with measurements of the average profile along the radius of polished wafers. although the low density of the measurements does not allow for direct confirmation of the edge ring. The models, while being both static and two dimensional provide reasonable results, especially in comparison the the three dimensional models of other researchers. As a result, computation times are reduced and the models are a valuable tool for process developers. 6
7 ACKNOWLEDGEMENTS The authors wish to thank the Centre for High Performance Computing Applications, University College Dublin for the use of their computing resources. They would also like to thank Enterprise Ireland and Intel Ireland for their support under the Applied Research Grants Scheme for Universities (Project Number HEB61125IA).
8 1.
2.
3.
146
REFERENCES Komanduri, R., Lucca, D.A.. Tani, Y., 1997, Technological Advances in Fine Abrasive Processes, Annals of the CIRP, Vol. 4612, pp 545596. Sun, S. C., Yeh, F. L., Tien, H. Z.. 1994. Characterisation of Chemical-Mechanical Polishing Dielectrics for Multilevel Metalization, Mat. Res. Symp. Proc. Vol. 337, pp. 389381. Li, W.; Shin, D.W.. Tomozawa, M., Murarka, S.. 1995, The Effect of the Polishing Pad Treatments on
the Chemical-Mechanical Polishing of Si02 Films., Thin Solid Films, 270, pp 601-606. 4. Mullany, 6..1997. Global Planarity of Silicon Wafers Resulting from Chemical Mechanical Polishing, Sir Bernard Crossland Symposium, Oct. pp. 35-49. (ISBN 1898012377). 5. Patrick, W., Guthrie. W., Standley, C.. Schiable, P., 1991, Application of Chemical Mechanical Polishing to the Fabrication of VLSl Circuit Interconnections., J. Electrochem. SOC., June, Vol. 138. No. 6, pp. 1778-1784. Stell. M., Jairath. R.. Desai. M., Tooles, R., 1994, 6. Planarization Ability of Chemical Mechanical Planarization (CMP) Processes., Mat. Res. SOC. Symp. Proc., Materials Research Society, Vol. 337, pp 151-156. 7. Nakamura, T., Akamatsu, K., Masuda, M., 1993, Mirror Polishing of Silicon Wafers (2nd Report)., Int. J. Japan SOC.Prec. Eng., Dec., Vol. 27, No. 4, pp. 345-350. Sugimoto, F., Arimoto ,Y., Ito, T., 1995, 8. Simultaneous Temperature Measurement of Wafers in Chemical Mechanical Polishing of Silicon Dioxide Layer., Jap. J. Appl. Phys.. Vol. 34,pp. 6314-6320. 9. Curry, J.. 1998, Integrating Solutions for the Challenges of CMP, Semiconductor Fabtech, 7th edition, pp. 223-233 (ISSN 1358-1759). 10. Srinivasa-Murthy, C.. Wang. D., Beaudoin, S.P., Bibby, T., Holland, K., Cale, T.S., 1997, Stress Distribution in Chemical Mechanical Polishing, Thin Solid Films, 308-309, pp. 533-537. 11. Wang, D., Lee, J., Holland, K., Biddy, T., Beaudoin, S., Cale, T., 1997, Von Mises Stress in Chemical Mechanical Polishing Process, Journal of Electrochem. SOC.,Vol. 144, No. 3, pp 1121-1127.
2
Abstract The Chemical Mechanical Polishing process planarises wafers with a high degree of success, however wear on the polishing pad causes the planarisation rate and the post-process planarity to deteriorate. To date, there has been no method of predicting the effect of this wear on the wafer planarity. Using finite element models of the process for new and worn pads the wafer stress distribution on the wafer surface can be predicted. Equating high stresses to high material removal rates these models predict that the process should become ‘centre slow’ as the pad wears. This correlates well with experimental data. Keywords: Chemical Mechanical Polishing, FEM, Wear
1 INTRODUCTION The fabrication of the latest integrated circuits (IC’s) requires careful construction of multi-layer interconnections between devices on the surface of the silicon wafer. With increasing complexity and speed requirements, the density and number of layers is increasing. Between layers an Inter Layer Dielectric (ILD) is deposited as a conformal layer which must then be planarised to provide a foundation for the next layer of connections and to expose the connections (vias) to lower levels. The fabrication costs of complex IC’s mean that the success of the process is measured by the number of fully functional devices which can be obtained from a single 200 mm or 300 mm diameter silicon wafer.
To date the most successful industrial method of planarising the ILD is that of Chemical Mechanical Polishing (CMP). As the name suggests CMP is a process in which both chemical and mechanical mechanisms interact to planarise the ILD at a satisfactory rate. It is a complex process as the relationship between the chemical and mechanical aspects has been difficult to define and quantify. Due to the lack of basic understanding of the CMP removal mechanisms, the success of the process in industry is dependent on the manufacturer’s ability to consistently operate the process within specific tolerances. In most cases the optimum values chosen for influential process parameters such as process pressure, slurry temperature and pH, and relative velocity are by determined by a trial and error approach in the process development stage. However not all parameters influencing the process planarity capabilities can receive the same meticulous attention. One such factor, which has hitherto received little attention, is that of polishing pad wear. Pad wear is a serious concern as it varies in an uncontrolled manner over time, inducing nonuniform effects on the polishing pad. These effects have an impact on the process itself, inducing undesirable instabilities which affect the ILD removal rates from the wafer surface. In order to improve the
Annals of the ClRP Vol. 48/7/1999
process work must be undertaken to understand the mechanisms and effects of such wear so that the consequences on the process stability may be minimised. PLANARITY OF SILICON WAFERS Good wafer planarity, both local and global, is essential for the dimensional accuracy required at subsequent lithography stages in wafer manufacture. On a global scale, within wafer uniformity of 0.2 pm across a 200 mm wafer is required, and as the wafer size increases even tighter tolerances are necessary. There are two main concerns when considering global planarity of wafers: 1. The edge-ring effect, whereby sharp variations in the ILD removal rate around the edge of the wafer result in a profile as shown in figure 1. 2. The less severe variation in ILD removal rates from the centre to the circumference of the wafer. With respect to the latter, several factors such as downward pressure on the wafer [2,3], inherent polishing pad properties [3], pad wear [4], relative velocities [5,6] and wafer temperature variations [7,8]are all known to affect wafer planarity. Over time the planarity of the processed wafers becomes inadequate and the ILD removal rates too slow as the pad becomes worn. The polishing action causes the soft pad to become smooth 2
30 20 10 0 Distance in from Wafer Edge (mm) Figure 1: Edge ring effect.
143
and ineffective almost immediately. In order to re-dress the surface of the pad, a conditioning arm tracks back and forth over the area where the pad is in contact with the wafer. This tears the surface, restoring the roughness, and also removes some material from the pad. Material removal is proportional to the conditioning density at each point on the pad radius. The deterioration in the quality of the product is a direct result of this pad wear as it alters both the physical properties and geometry of the pad.The majority of the work investigating the relationship between the process parameters and wafer planarity has been of an empirical nature with little mathematical modelling done to compliment the experimental work. For example, experimental work by Curry [9] highlighted the effect of different geometric pad profiles induced by differing pad conditioning density patterns on the global planarity of the polished wafers and the increasing deviations in planarity as the pad aged. It was also found that particular conditioning densities allowed good global planarity to be achieved consistently over the pad life while other conditioning densities induced a deterioration in the capability of the processes to achieve the required planarity. More recently, finite element models by Srinivasa-Murthy et al. [lo] and Wang et al. [ll] have been developed. A typical CMP system was modelled as a static 3-D model and loaded with the process pressure. The von Mises stress distributions along the wafer surface in contact with the pad showed a marked increase near the edge of the wafer, an area where a phenomenon known as the edge ring effect occurs. Here wafer planarity is often poor as a sharp dip in the surface results from higher material removal rates. The models showed that the applied down force causes some radial deformation of the pad during polishing and that it is most noticeable at the edge of the wafer. Although the radial deformation at the wafer edge is only in the order of 0.03 mm. it can induce stresses up to 3 times greater than the average in the region of the wafer edge resulting in significant variations in the von Mises stresses. More interestingly, the calculated von Mises stresses correlated well with observed removal rates, with higher von Mises stresses corresponding to higher removal rates, thus allowing an explanation for the edge ring effect. These models both assumed that the pad geometry was flat and it’s properties consistent across the area of contact between the pad and the wafer. Here, the same approach is used to determine the effects of changes in pad geometry on the material removal rates. POLISHING PAD WEAR Several different polishing pad materials are available to the industry, the pad which is modelled in this work is an ICI 000 porous polyurethane pad. Pad life, determined by the process output, is in the region of 800 wafers after which the ILD removal rates are inadequate and wafer planarity is unacceptable. 3
3.1 Geometric alterations due to pad wear The most noticeable effect of wear is that the geometry of the pad alters with time. It experiences nonuniform thinning across its radius resulting in a concave or ‘dished thickness profile. Figure 2 shows the reduction in pad thickness with wear. A worn pad, at its thinnest, will be approximately 10% thinner than a new pad, however this thinning can be as little as 2% at the outer edge and centre of the polishing pad.
144
h
-
.--*.tL..,*.
,
,..,
,,
.dC__
~~. -,
h..
*. ’ *-
0.15
. 0.3
m
a
Polishing Pad Radius (m) Figure 2: Pad thinning due to wear.
h
Crn
.-
z
4c /
n
--I”
0
U
0.3
0.15 Polishing Pad Radius(rn)
rn
a
Figure 3: Modelled profile of worn pad. From the nature of the geometries it is clear that the distribution of the reaction force from the pad will be considerably different for new and worn pads. As the removal rate of the ILD is dependent on the contact pressure acting on the wafer, a correlation between pad protile and deteriorating planarity is expected.
3.2 Intrinsic pad property alterations due to wear Polishing pad wear also affects both the surface and bulk properties of the polishing pad. Both pad compliance and hardness vary as the pad wears [4]. The compliance values for worn and new lCl000 pads differ by about 13% with worn pads being more compliant, while the shore D hardness values differ by approx. 3% with the worn pad been harder. Both of these properties also vary with pad thickness, thus as a direct result of pad dishing there will be varying compliance and hardness values from the edge of the pad to its centre leading to anisotropic material properties.
4 FINITE ELEMENT MODEL For this investigation, a 2-D finite element model of the system was developed. The model includes the carrier head, wafer and polishing pad as per Figure 4. Two simulation scenarios were modelled, in the first simulation the pad was modelled with a nominally flat surface representing a new pad, while in the second simulation the pad has a dished profile shown in Figure 3. The mechanical properties for the wafer and the polishing pad are listed in Table 1. The values of Young’s Modulus for the both new and worn polishing pads were determined experimentally based on the average of several points measured across the pad radius. In the case of new polishing pads there was no noticeable variation in Young’s Modulus across the pad diameter but there are noticeable variations in the case of a worn pad. Later work will incorporate these radial variations into the finite element model. All other values used are typical values for the material in question. Carrier Head L W a f e r
YI
x
’
I
Figure 4: Schematic of the 2-0finite element model.
Density, p,(Kg/m3)
Polishing pad
Young’s Modulus, E, (Nlm2) 1.16 x 106
800
0.1
Wafer
2.00
7,000
0.3
x
1011
Poisson’s Ratio, y
E -0.02
-0.02
N^
V
a”
i ??
;a v)
-0.1
-0.1
a
z
?,
3 -0.14
-0.14 “, 3
Fi Z
g 3
-0.18
Wafer Radius (mm)
100
0
-0.18
Y
Figure 6: Comparison of wafer normal stress, oy and pad compression, 6p, for new and worn pads. Figure 6 compares the normal stresses, cY, for new and worn pads together with the compression of the pad. It can be seen that the magnitude of the stress normal to the wafers surface is strongly dependent on the deformation of the underlying pad.
5 RESULTS AND DISCUSSION CPU time for a worn pad is considerably longer than that for the new pad. The extra computational time is required to solve the more complex wafer-pad contact, particularly in the initial stage. New pad model Figure 5 shows the variations in the von Mises stress distribution across the wafer radius. As can be clearly seen there are large variations in the stresses towards the edge of wafer which correlates well with previous findings [lo] and [ll]. This edge ring effect extends approximately 5 mm in from the wafer edge, in agreement with measurements from polished wafers. 5.1
5.2 Worn pad model The von Mises stress distribution across the surface of the wafer for contact with a worn pad is distinctly different, figure 5. Variations in the von Mises stress are not just confined to the wafer edges, they exist across the entire wafer surface. The stress isup to 30% higher in the outer 40% of the wafer than at the centre. This suggests that the removal rates at the centre of the wafer are lower, resulting in a convex surface after planarisation. On investigation, the component of the von Mises stress which contributed most to this distribution is the normal stress on the wafer surface, oy.
5.3 Comparison to measured ILD removal rates To validate these results several unpatterned wafers were selected for polishing at various stages during the life of the pad. The thickness of the ILD layer is measured at selected locations on the wafer before and after polishing to determine both the ILD removal rate and post-process planarity. Each wafer tested is polished for 2 minutes. Since all wafers have individual surface profiles as a result of variations within the fabrication process wafers with very similar pre polishing ILD thickness were paired together. The wafer surface profile was established by measuring the ILD layer thickness at 49 locations distributed in concentric rings and at the centre. To show the similarity of a pair of wafers figure 7 shows the measured ILD thickness of wafers 23 and 144. In order to see the differences, the vertical axis has been greatly increased, and as viewing the resulting profile from the side results in several distinct locations appearing to be co-incident, the data is shown in a 3-D view. The wafers are inclined 15 degrees anti-clockwise about the x axis and then rotated 5 degrees around the z-axis.
The first wafer of the pair, wafer 23, was polished early in the pad life, .while the second wafer, wafer 144 was polishe’d at a later stage. The ILD removed from the wafer surface by polishing follows the trend highlighted in the finite element model. Figure 8 shows the average amount
7
ILD Depth Wafer 23
*
$ ,
ILD DeDth Wafer 144
0.15 rn
rn
a, .g
0.1
m E % E
5 50.05 c
P
0 100
Wafer Radius (mm)
0
Figure 5: Comparison of von Mises stress distributions for New and Worn pads.
Figure 7: Measured ILD thicknesses for wafer numbers 23 and 144 (x, y axes not to scale).
145
0%
50%
100%
Radius (%)
Figure 8: Amount of ILD removed from wafer numbers 23 and 144. of ILD removed from the centre and each of the 3 rings on the wafer surface. The wafers have a convex profile on entry, so material removal rates for a new pad are higher in the centre. On examining the ILD removed from wafer 144, which was polished with a pad at about one quarter of its useful life, a distinct reduction in the removal rate at the centre of the wafer was found. This reduction was predicted by the model. The edge ring effect is not visible in these measured results as no readings are available from the 10 mm annulus at the wafer's edge. CONCLUSIONS The finite element models developed show clearly that, with pad wear, the von Mises stresses on the surface of the wafer increase at the outer 40% of the wafer radius. This is accompanied by a reduction of the stresses at the centre of the wafer. As a result it is expected that the process will be 'centre slow' towards the end of pad life. This correlates well with measurements of the average profile along the radius of polished wafers. although the low density of the measurements does not allow for direct confirmation of the edge ring. The models, while being both static and two dimensional provide reasonable results, especially in comparison the the three dimensional models of other researchers. As a result, computation times are reduced and the models are a valuable tool for process developers. 6
7 ACKNOWLEDGEMENTS The authors wish to thank the Centre for High Performance Computing Applications, University College Dublin for the use of their computing resources. They would also like to thank Enterprise Ireland and Intel Ireland for their support under the Applied Research Grants Scheme for Universities (Project Number HEB61125IA).
8 1.
2.
3.
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REFERENCES Komanduri, R., Lucca, D.A.. Tani, Y., 1997, Technological Advances in Fine Abrasive Processes, Annals of the CIRP, Vol. 4612, pp 545596. Sun, S. C., Yeh, F. L., Tien, H. Z.. 1994. Characterisation of Chemical-Mechanical Polishing Dielectrics for Multilevel Metalization, Mat. Res. Symp. Proc. Vol. 337, pp. 389381. Li, W.; Shin, D.W.. Tomozawa, M., Murarka, S.. 1995, The Effect of the Polishing Pad Treatments on
the Chemical-Mechanical Polishing of Si02 Films., Thin Solid Films, 270, pp 601-606. 4. Mullany, 6..1997. Global Planarity of Silicon Wafers Resulting from Chemical Mechanical Polishing, Sir Bernard Crossland Symposium, Oct. pp. 35-49. (ISBN 1898012377). 5. Patrick, W., Guthrie. W., Standley, C.. Schiable, P., 1991, Application of Chemical Mechanical Polishing to the Fabrication of VLSl Circuit Interconnections., J. Electrochem. SOC., June, Vol. 138. No. 6, pp. 1778-1784. Stell. M., Jairath. R.. Desai. M., Tooles, R., 1994, 6. Planarization Ability of Chemical Mechanical Planarization (CMP) Processes., Mat. Res. SOC. Symp. Proc., Materials Research Society, Vol. 337, pp 151-156. 7. Nakamura, T., Akamatsu, K., Masuda, M., 1993, Mirror Polishing of Silicon Wafers (2nd Report)., Int. J. Japan SOC.Prec. Eng., Dec., Vol. 27, No. 4, pp. 345-350. Sugimoto, F., Arimoto ,Y., Ito, T., 1995, 8. Simultaneous Temperature Measurement of Wafers in Chemical Mechanical Polishing of Silicon Dioxide Layer., Jap. J. Appl. Phys.. Vol. 34,pp. 6314-6320. 9. Curry, J.. 1998, Integrating Solutions for the Challenges of CMP, Semiconductor Fabtech, 7th edition, pp. 223-233 (ISSN 1358-1759). 10. Srinivasa-Murthy, C.. Wang. D., Beaudoin, S.P., Bibby, T., Holland, K., Cale, T.S., 1997, Stress Distribution in Chemical Mechanical Polishing, Thin Solid Films, 308-309, pp. 533-537. 11. Wang, D., Lee, J., Holland, K., Biddy, T., Beaudoin, S., Cale, T., 1997, Von Mises Stress in Chemical Mechanical Polishing Process, Journal of Electrochem. SOC.,Vol. 144, No. 3, pp 1121-1127.