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The effects of impurity bands on the electrical characteristics of metal-semiconductor ohmic contacts
452
World abstracts on microelectronics and reliability
dependence of the Y parameters on the gate bias voltage, drain bias voltage, channel doping, and gate position along the channal is discussed. In addition, the MC simulation and a two-dimensional driftdiffusion (DD) model were compared. This was accomplished by comparing the current gain and Y parameters of the transistor over a wide range of frequency predicted by the two approaches. The MC approach led to a 40% higher unity current gain frequency over the DD model.
Lead inductance of tape carrier package for high-speed LSI's. MITSUYUKI TAKADA et al., IEEE Transactions on Components, Packayiny, and Manufacturing Technoloyy--Part B, 17, 4, 584 (November 1994). Lead inductances of a 432-lead TCP (Tape Carrier Package) with a metal cap are evaluated by treating the leads as multiconductor-coupled lines. A useful inductanace evaluating method is obtained by using a quasi-TEM electromagnetic field analysis and matrix operations. This method is demonstrated for the TCP. By a proximity effect of grounded conductors, the effective self inductance of the longest lead can be reduced to 7.3 nil. This result indicates that TCP's can be applied to high-speed LSI's of clock rates up to 100 MHz. Reliability modelling and performance evaluation of variable link-capacity networks. PRAMOD K, VARSHNEY, ABHAY R. JOSHI and PEI-LIANG CHANG. IEEE Transactions on Reliability, 43, 3, 378 (September 1994). This paper presents a composite performance index for communication networks with variable link-capacities. This index is based on link reliabilities and multiple-capacity link-states. Source-to-terminal success is the ability to provide connectivity with a certain traffic-carrying capacity. This index is useful for determining the performance of networks with links operating with residual traffic-carrying capacity and gives a good idea of the available resources for a particular s-t connection. An algorithm evaluates the composite performance index. Examples illustrate the method.
7. SEMICONDUCTOR INTEGRATED CIRCUITS, DEVICES AND MATERIALS
A new contactless S-polarized reflectance technique for determining the Si film and buried oxide thickness in silicon-on-insulator materials. YUN-SHAN CaANG and SHENG S. LL Solid-State Electronics, 38, 2, 297 (1995). A new contactless dual-beam S-polarized reflectance (DBSPR) technique has been developed for measuring the top Si film and buried oxide thickness in a SIMOX (Separation by IMplantation of OXygen) wafer. Top Si slim and buried oxide thicknesses of the SIMOX wafers ranging from 0.2 to 1.6 gm and 0.36 to 0.44 gin, respectively, were determined using this new technique. The DBSPR method is based on the S-polarized reflectances measured at oblique angle incidence using laser beam of different wavelengths (2 = 442 and
632.8 nm). A theoretical model for the DBSPR technique has been derived for determining the top Si film and buried oxide thicknesses in the SO1 wafers. A three-dimensional (3D) mapping of the top Si film and buried oxide thicknesses for several SIMOX wafers has been carried out, and the results were found in excellent agreement agreement with values determined by the conventional reflection interference spectroscopy and ellipsometry methods.
Investigation of multilayered Ge/Si structures with varying thicknesses. N. A. KISELEV, O. I. LEBEDEV, A. L, VASILIEV,M. V. ANTIPOV, A. A, ORLIKOVSKY, K. A. VALIEVand A. G. VASlLIEV. Vacuum, 46, 3, 269 (1995). The aim of this paper is the investigation of a GeSi/Si heterostructure formation obtained by deposition of Ge and Si layers of different thickness. GexSil_x/Si films obtained by MBE in high vacuum were multilayered systems with alternate Si and Ge layers. The layer thickness was 10-150 A. The samples were obtained at substrate temperatures from RT to 700°C. The transmission electron microscopy (TEM) and Rutherford backscattering spectroscopy (RBS) investigation allowed one to propose a model for the GeSi/Si heterostructure formation process during MBE. The data on mutual Ge and Si diffusion at different substrate temperatures were obtained and the temperature range of layer interface mixing was defined. HREM investigation of the film and interface structure at different TS allows one to define the conditions of 2-D and 3-D film growth. Active doping instability in n+-p silicon surface avalanche diodes. S. MANZ1NI. Solid-State Electronics, 38, 2, 331 (1995). A failure mode of n +- p silicon surface avalanche diodes subject to reverse current stress is characterized. The observed instability of the breakdown voltage is associated with a large increase of the dynamic resistance of the diode, likely due to boron neutralization of the p-type silicon region by hydrogen atoms released by hot-carriers from the avalanche condition. The initial phase of degradation is described by an empirical equation with appropriate parameters valid for a wide range of temperature and reverse current. Both static and dynamic degradation is investigated. Some issues relevant to accelerated life-tests are also addressed. The effects of impurity bands on the electrical characteristics of metal-semiconductor ohmic contacts. YUNG-SONG LOU and CHING-YUAN WU. Solid-State Electronics, 38, 1, 163 (1995). The effects of semiconductor heavy doping on the I V characteristics and the specific contact resistivity Pc of semiconductor-metal ohmic contacts have been theoretically studied by incorporating the band-edgetailing and impurity band effects. The Fermi level and the effective conduction band edge have been recalculated to determine the electron population and the bandgap narrowing. When the available electrons
World abstracts on microelectronics and reliability with higher transmission probability, which dominate the tunneling process, have been reduced by the presence of an impurity band, the tunneling current density becomes lower and hence the specific contact resistivity becomes higher for the case with the impurity band than that without the impurity band. Considering the physical properties inherent in a heavily-doped semiconductor, it is possible to explain the deviations of the experimental data from the theoretical results obtained from the conventionally used tunnneling theory for the ohmic contacts. Furthermore, by comparing the simulated results and the measured Pc data deduced from the AI and Ti contacts on both doping types of the Si-substrate, satisfactory agreements have been obtained. Resistivity curves for subsurface diffused layers in silicon. CONSTANTINBULUCEA.Solid-State Electronics, 38, 2, 367 (1995). Average resistivity curves are calculated for subsurface diffused layers in silicon using the updated resistivity-concentration data available for boron- and phosphorus-doped bulk silicon. This complements a recent paper of the author on full-depth diffused profiles, making up a complete equivalent of Irvin's original set. An improved representation format is used, which decompresses the resistivity scale and also reduces to half the total number of graphs involved in average resistivity calculations. Plasma-grown oxides on silicon with extremely low interface state densities. G. P. KENNEDY, S. TAYLOR, W. ECCLESTON and M. J. UREN. Microelectronics Journal, 25, 485 (1994). Plasma-grown oxides on silicon with midgap interface state densities less than 101 o cm 2 eV i have been obtained using low process temperatures ( < 120°C). Slow and fast interface state densities were measured over a wide frequency range by two different techniques: the quasistatic (CV) and the conductance (Gp/w)methods. Careful attention to system apparatus design, cleanliness and operation are thought to be the main factors responsible for the low interface trap densities. MOSFET degradation during substrate hot electron stress. S. P. ZHAO, S. TAYLOR and A. McPHIv. Microelectronics Journal, 25, 515 (1994). The reliability of n-channel MOSFETs during hot electron injection is studied using the SHE technique on CMOS samples. Results show the degradation dependence of the oxide bulk and interface over the field range from 0.5 to 6 MV cm t for different injection fluence levels, which has been conveniently monitored using subthreshold current measurements. A novel hot carrier reliability monitor for LDD p-MOSFETs. Y. PAN, K. K. NG and W. KWONG. Solid-State Electronics, 37, 12, 1961 (1994). The gate-edge shape of an LDD p-MOSFET exhibits large influences upon the hot carrier induced degradation and its performances. It is observed that the gate-to-drain tunneling current is strongly correlated
453
to the reentrant gate oxide thickness and to the device degradation. A simple model is then constructed to provide an explanation for the observation. Under the tunneling current measurement conditions, a thicker oxide at the gate-edge leads to a weaker peak electric field in the p-LDD and to a lower gate-to-drain current. On the other hand, under the hot carrier stressing conditions, the thicker oxide decreases the oxide electric field and thus suppresses the hot electron injection. The observed correlation can be employed to monitor the process induced gate-edge (overlap) variation. 8. THICK- AND THIN-FILM COMPONENTS, HYBRID CIRCUITS AND MATERIALS Application of lead-free eutectic Sn-Ag solder in no-clean thick film electronic modules. DONGKAI SHANGGUAN, ACHYUTA ACHARI and WELLS GREEN.
IEEE Transactions on Components, Packaging, and Manufacturin 9 Technology--Part B, 17, 4, 603 (November 1994). As part of the lead-free solder development process currently underway, this paper presents the evaluation of the lead-free Sn-Ag solder for use in no-clean thick film electronics packages. The Sn-Ag (96.5/3.5 wt%) eutectic solder alloy, with a no-clean flux system, is the focus of this study. Based on studies of metallurgical interactions, the conductor/substrate adhesion, and electromigration/ dendritic growth, it is concluded that this solder has superior overall properties and is suitable for solder interconnects in thick film automotive electronics packages when used with a mined bonded Ag conductor. Fracture mechanics for thin-film adhesion. M. D. THOULESS. IBM Journal of Research and Development, 38, 4, 367 (July 1994). The essential elements of the mechanics of delamination are reviewed and their implications for design are discussed. Two important concepts for the prediction of the reliability of thin-film systems are emphasized: (1) limiting solutions for the crack-driving force that are independent of flaw size, and (2) 'mixed-mode fracture'. Consideration of the first concept highlights the possibility of flaw-tolerant design in which the statistical effects associated with flaw distributions can be eliminated. The significance of mode-mixedness includes its effect on crack trajectories and on the interface toughness, two key variables in determining failure mechanisms. Theoretical predictions are given for some cases of delamination of thin films under compressive stresses, and the results are compared with experimental observations to illustrate appropriate design criteria for the model systems studied. A vertical suhmicron SiC thin film transistor. J. D. HWANG, Y. K. FANG and T. Y. TSAI. Solid-State Electronics, 38, 2, 275 (1995). Two vertical type submicron p-channel depletion mode SiC MOSFETs have been studied. To produce the first M O S F E T a
World abstracts on microelectronics and reliability
dependence of the Y parameters on the gate bias voltage, drain bias voltage, channel doping, and gate position along the channal is discussed. In addition, the MC simulation and a two-dimensional driftdiffusion (DD) model were compared. This was accomplished by comparing the current gain and Y parameters of the transistor over a wide range of frequency predicted by the two approaches. The MC approach led to a 40% higher unity current gain frequency over the DD model.
Lead inductance of tape carrier package for high-speed LSI's. MITSUYUKI TAKADA et al., IEEE Transactions on Components, Packayiny, and Manufacturing Technoloyy--Part B, 17, 4, 584 (November 1994). Lead inductances of a 432-lead TCP (Tape Carrier Package) with a metal cap are evaluated by treating the leads as multiconductor-coupled lines. A useful inductanace evaluating method is obtained by using a quasi-TEM electromagnetic field analysis and matrix operations. This method is demonstrated for the TCP. By a proximity effect of grounded conductors, the effective self inductance of the longest lead can be reduced to 7.3 nil. This result indicates that TCP's can be applied to high-speed LSI's of clock rates up to 100 MHz. Reliability modelling and performance evaluation of variable link-capacity networks. PRAMOD K, VARSHNEY, ABHAY R. JOSHI and PEI-LIANG CHANG. IEEE Transactions on Reliability, 43, 3, 378 (September 1994). This paper presents a composite performance index for communication networks with variable link-capacities. This index is based on link reliabilities and multiple-capacity link-states. Source-to-terminal success is the ability to provide connectivity with a certain traffic-carrying capacity. This index is useful for determining the performance of networks with links operating with residual traffic-carrying capacity and gives a good idea of the available resources for a particular s-t connection. An algorithm evaluates the composite performance index. Examples illustrate the method.
7. SEMICONDUCTOR INTEGRATED CIRCUITS, DEVICES AND MATERIALS
A new contactless S-polarized reflectance technique for determining the Si film and buried oxide thickness in silicon-on-insulator materials. YUN-SHAN CaANG and SHENG S. LL Solid-State Electronics, 38, 2, 297 (1995). A new contactless dual-beam S-polarized reflectance (DBSPR) technique has been developed for measuring the top Si film and buried oxide thickness in a SIMOX (Separation by IMplantation of OXygen) wafer. Top Si slim and buried oxide thicknesses of the SIMOX wafers ranging from 0.2 to 1.6 gm and 0.36 to 0.44 gin, respectively, were determined using this new technique. The DBSPR method is based on the S-polarized reflectances measured at oblique angle incidence using laser beam of different wavelengths (2 = 442 and
632.8 nm). A theoretical model for the DBSPR technique has been derived for determining the top Si film and buried oxide thicknesses in the SO1 wafers. A three-dimensional (3D) mapping of the top Si film and buried oxide thicknesses for several SIMOX wafers has been carried out, and the results were found in excellent agreement agreement with values determined by the conventional reflection interference spectroscopy and ellipsometry methods.
Investigation of multilayered Ge/Si structures with varying thicknesses. N. A. KISELEV, O. I. LEBEDEV, A. L, VASILIEV,M. V. ANTIPOV, A. A, ORLIKOVSKY, K. A. VALIEVand A. G. VASlLIEV. Vacuum, 46, 3, 269 (1995). The aim of this paper is the investigation of a GeSi/Si heterostructure formation obtained by deposition of Ge and Si layers of different thickness. GexSil_x/Si films obtained by MBE in high vacuum were multilayered systems with alternate Si and Ge layers. The layer thickness was 10-150 A. The samples were obtained at substrate temperatures from RT to 700°C. The transmission electron microscopy (TEM) and Rutherford backscattering spectroscopy (RBS) investigation allowed one to propose a model for the GeSi/Si heterostructure formation process during MBE. The data on mutual Ge and Si diffusion at different substrate temperatures were obtained and the temperature range of layer interface mixing was defined. HREM investigation of the film and interface structure at different TS allows one to define the conditions of 2-D and 3-D film growth. Active doping instability in n+-p silicon surface avalanche diodes. S. MANZ1NI. Solid-State Electronics, 38, 2, 331 (1995). A failure mode of n +- p silicon surface avalanche diodes subject to reverse current stress is characterized. The observed instability of the breakdown voltage is associated with a large increase of the dynamic resistance of the diode, likely due to boron neutralization of the p-type silicon region by hydrogen atoms released by hot-carriers from the avalanche condition. The initial phase of degradation is described by an empirical equation with appropriate parameters valid for a wide range of temperature and reverse current. Both static and dynamic degradation is investigated. Some issues relevant to accelerated life-tests are also addressed. The effects of impurity bands on the electrical characteristics of metal-semiconductor ohmic contacts. YUNG-SONG LOU and CHING-YUAN WU. Solid-State Electronics, 38, 1, 163 (1995). The effects of semiconductor heavy doping on the I V characteristics and the specific contact resistivity Pc of semiconductor-metal ohmic contacts have been theoretically studied by incorporating the band-edgetailing and impurity band effects. The Fermi level and the effective conduction band edge have been recalculated to determine the electron population and the bandgap narrowing. When the available electrons
World abstracts on microelectronics and reliability with higher transmission probability, which dominate the tunneling process, have been reduced by the presence of an impurity band, the tunneling current density becomes lower and hence the specific contact resistivity becomes higher for the case with the impurity band than that without the impurity band. Considering the physical properties inherent in a heavily-doped semiconductor, it is possible to explain the deviations of the experimental data from the theoretical results obtained from the conventionally used tunnneling theory for the ohmic contacts. Furthermore, by comparing the simulated results and the measured Pc data deduced from the AI and Ti contacts on both doping types of the Si-substrate, satisfactory agreements have been obtained. Resistivity curves for subsurface diffused layers in silicon. CONSTANTINBULUCEA.Solid-State Electronics, 38, 2, 367 (1995). Average resistivity curves are calculated for subsurface diffused layers in silicon using the updated resistivity-concentration data available for boron- and phosphorus-doped bulk silicon. This complements a recent paper of the author on full-depth diffused profiles, making up a complete equivalent of Irvin's original set. An improved representation format is used, which decompresses the resistivity scale and also reduces to half the total number of graphs involved in average resistivity calculations. Plasma-grown oxides on silicon with extremely low interface state densities. G. P. KENNEDY, S. TAYLOR, W. ECCLESTON and M. J. UREN. Microelectronics Journal, 25, 485 (1994). Plasma-grown oxides on silicon with midgap interface state densities less than 101 o cm 2 eV i have been obtained using low process temperatures ( < 120°C). Slow and fast interface state densities were measured over a wide frequency range by two different techniques: the quasistatic (CV) and the conductance (Gp/w)methods. Careful attention to system apparatus design, cleanliness and operation are thought to be the main factors responsible for the low interface trap densities. MOSFET degradation during substrate hot electron stress. S. P. ZHAO, S. TAYLOR and A. McPHIv. Microelectronics Journal, 25, 515 (1994). The reliability of n-channel MOSFETs during hot electron injection is studied using the SHE technique on CMOS samples. Results show the degradation dependence of the oxide bulk and interface over the field range from 0.5 to 6 MV cm t for different injection fluence levels, which has been conveniently monitored using subthreshold current measurements. A novel hot carrier reliability monitor for LDD p-MOSFETs. Y. PAN, K. K. NG and W. KWONG. Solid-State Electronics, 37, 12, 1961 (1994). The gate-edge shape of an LDD p-MOSFET exhibits large influences upon the hot carrier induced degradation and its performances. It is observed that the gate-to-drain tunneling current is strongly correlated
453
to the reentrant gate oxide thickness and to the device degradation. A simple model is then constructed to provide an explanation for the observation. Under the tunneling current measurement conditions, a thicker oxide at the gate-edge leads to a weaker peak electric field in the p-LDD and to a lower gate-to-drain current. On the other hand, under the hot carrier stressing conditions, the thicker oxide decreases the oxide electric field and thus suppresses the hot electron injection. The observed correlation can be employed to monitor the process induced gate-edge (overlap) variation. 8. THICK- AND THIN-FILM COMPONENTS, HYBRID CIRCUITS AND MATERIALS Application of lead-free eutectic Sn-Ag solder in no-clean thick film electronic modules. DONGKAI SHANGGUAN, ACHYUTA ACHARI and WELLS GREEN.
IEEE Transactions on Components, Packaging, and Manufacturin 9 Technology--Part B, 17, 4, 603 (November 1994). As part of the lead-free solder development process currently underway, this paper presents the evaluation of the lead-free Sn-Ag solder for use in no-clean thick film electronics packages. The Sn-Ag (96.5/3.5 wt%) eutectic solder alloy, with a no-clean flux system, is the focus of this study. Based on studies of metallurgical interactions, the conductor/substrate adhesion, and electromigration/ dendritic growth, it is concluded that this solder has superior overall properties and is suitable for solder interconnects in thick film automotive electronics packages when used with a mined bonded Ag conductor. Fracture mechanics for thin-film adhesion. M. D. THOULESS. IBM Journal of Research and Development, 38, 4, 367 (July 1994). The essential elements of the mechanics of delamination are reviewed and their implications for design are discussed. Two important concepts for the prediction of the reliability of thin-film systems are emphasized: (1) limiting solutions for the crack-driving force that are independent of flaw size, and (2) 'mixed-mode fracture'. Consideration of the first concept highlights the possibility of flaw-tolerant design in which the statistical effects associated with flaw distributions can be eliminated. The significance of mode-mixedness includes its effect on crack trajectories and on the interface toughness, two key variables in determining failure mechanisms. Theoretical predictions are given for some cases of delamination of thin films under compressive stresses, and the results are compared with experimental observations to illustrate appropriate design criteria for the model systems studied. A vertical suhmicron SiC thin film transistor. J. D. HWANG, Y. K. FANG and T. Y. TSAI. Solid-State Electronics, 38, 2, 275 (1995). Two vertical type submicron p-channel depletion mode SiC MOSFETs have been studied. To produce the first M O S F E T a