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The effects of test and rework operations on the flow of materials in circuit card assembly
Journal of Manufacturing Systems Volume l 1/No. 3
The Effects of Test and Rework Operations on the Flow of Materials in Circuit Card Assembly W.E. Wilhelm, Texas A&M University, College Station, TX
Abstract
The incidence of test and rework cycles is determined by the system-wide quality control plan that integrates the quality of vendor-supplied components, the capabilities of assembly processes, the strategy of testing, and the workmanship at rework stations to achieve corporate objectives for product quality. Models used to analyze material flow often take a pragmatic view of this complex phenomenon, assuming an equal probability of rejection on each test cycle as well as independent and identically distributed operation times at each cycle. 14A5'17'18 Models that invoke these assumptions typically do not predict the bottlenecks that frequently occur at test and rework operations. The objective of this paper is to apply the fundamental axioms of the probability theory to better understand the phenomena that might lead to flow bottlenecks at test and rework operations in circuit card assembly systems. Since each assembly system may be unique (for example, due to product design or the assembly processes employed), a systematic approach is required so that a model may be easily derived for each specific case of interest. To achieve this objective, the fundamental axioms of the probability theory are utilized to suggest such a systematic approach. Circuit cards are used as a focus because they are crucial to numerous modern products and present certain worst case challenges to analysis. Results are thus applicable to circuit card assembly, but it is expected that the method of analysis may find general application in industry. Models that describe quality capabilities have been based on the binomial distribution, 4 Markov chains, 3 thruput rates,13 and fundamental probability axioms. In related models, a rejected product may be scrapped, 10'12 replaced by a good one, 21 repaired instantaneously, 22 reworked, 4's'15 or cycled through test and rework until accepted. 17-18
This paper presents a structured approach for analyzing the effects of test and rework operations on material flow in systems that assemble circuit cards. Stages that affect quality (e.g., vendor preparation of components, pooling, assembly processes, and test and rework) are identified and representative models of each are presented. Each product is treated as a composite of multiple components, each of which is vulnerable to a variety of defects. Test is treated as fallible and rework as imperfect. Several procedures that accomplish rework are considered. Examples demonstrate some fundamental effects of test and rework operations on material flow. Management implications for improving material flow are discussed.
Keywords: Material Flow Management, Effects of Quality on Material Flow, Test and Rework Operations, Probability Model of Quality, Circuit Card Assembly
Introduction Material flow may interact with quality control in a number of ways. For example, the length of a queue may influence the production rate of an operator and affect the quality of his work. Tests may identify defective workpieces that must be scrapped, reducing flow rates. Other types of defects can be repaired so that materials are cycled between test and rework stations until deemed acceptable. Test and rework operations are particularly important in systems that assemble circuit cards, since they are typically lengthy, require highly variable times, and often lead to flow bottlenecks. As systems automate, understanding the nature of test and rework operations becomes even more important since rejects may require specialcase routing and handling.
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Tablel Notation
P r o d u c t s are t y p i c a l l y a s s u m e d to e x h i b i t a single t y p e o f d e f e c t , a l t h o u g h m u l t i p l e d e f e c t s h a v e also b e e n m o d e l e d . 4'7 I n s p e c t i o n s are m o s t o f t e n a s s u m e d to b e p e r f e c t , b u t fallible i n s p e c t i o n ( g o o d p r o d u c t s m a y be r e j e c t e d a n d d e f e c t i v e o n e s accepted),2'4'7 repeated inspection,l~ and sampling 6 h a v e b e e n treated. A n u m b e r o f studies deal w i t h q u a l i t y c o n t r o l o f e l e c t r o n i c s in g e n e r a l 8'ls a n d circuit c a r d a s s e m b l y in particular. ~'~9 C i r c u i t c a r d test p r o c e d u r e s h a v e been studied using simulation, 4 and rules for sequencing r e w o r k h a v e b e e n e v a l u a t e d , s'15 D o o l e y 7 d e v e l o p e d a m o d e l o f circuit c a r d q u a l i t y . His m o d e l is l i m i t e d , h o w e v e r , s i n c e it c o n s i d e r s the f l o w o f d e f e c t s r a t h e r than circuit c a r d s . F u et al. 9 a n a l y z e the relative c o s t s o f w o r k in-process (WIP), materials, equipment, labor, maintenance, and overhead using a macroscopic m o d e l that relates these c o s t s to the p r o b a b i l i t y that a circuit c a r d is a c c e p t e d at test. T h e i r m o d e l d o e s not, h o w e v e r , d e v e l o p the p r o b a b i l i t y o f a c c e p t a n c e as a f u n c t i o n o f the s y s t e m - w i d e q u a l i t y c o n t r o l p l a n as d o e s this p a p e r . Suri, S a n d e r s , a n d M o d y 2° d e s c r i b e an e m p i r i c a l s t u d y that c o m p a r e s the c o s t s o f a s s e m b l i n g circuit c a r d s in d e v e l o p e d c o u n t r i e s , n e w l y i n d u s t r i a l i z e d c o u n t r i e s , a n d less d e v e l o p e d c o u n t r i e s . T h e y e m p h a s i z e that n e w l y i n d u s t r i a l i z e d countries gain a competitive advantage through h i g h e r q u a l i t y , w h i c h entails less s c r a p a n d l o w e r W I P costs.
Indices c = 1..... Ct i -- 1..... I' j = 1..... J' k = 1..... K' l = 1..... L' m = 1..... M' n = 1..... N'~ t = 1..... T' v = 1, .... V' Sets Dt Mk N~, O,. Ti Tj
U~, U'i Vl W~ Zl 5v
numberof times test t is performed products(i.e., circuit cards) componenttypes defecttypes tests at the component level processes
individual components on card i tests at the circuit card level vendors
= = = = = = = = = =
{k I defect type k is detectable at test t} {m I process m can introduce defect type k} {n [ component n is vulnerable to defect type k} [k [ defect type k may be introduced at process m} {t [ test t is performed on card i after assembly} {l I test I is conducted on component type j } {k [ defect type k affects component type j on card i} {k [ defect type k affects circuit card i} {v I vendor v supplies component type j} {j I component type j is assembled on card i} {m I process m is required to assemble card type i} = {k [ defect type k introduced by vendor v}
Parameters
oi, J,.
= portion of type j components supplied by vendor v = type of (specific) component n on card i
Probabilities Associated with Process Capabilities e~t, = Pr[test calls component good ] component is good] f ~ = Pr[test calls component good [ component is bad] r~ = Pr[defect type k is NOT introduced at process m] uk~ = Pr[rework yields good component I defect k existed] wm = Pr[defect type k is introduced by c~ rework cycle] Xkffi = Pr[rework yields good component I defect did not exist] Probabilities for Component Quality .a~,, = Pr[accept component on cth test/rework cycle] dj~ = Pr[accept component at test/] g~,, = Pr[component is good coming into cth test cycle] ~a = Pr[type j component is good relative to defect type k at test/] Y'iu = Pr[type j component is good I accepted by test/] rl"~, = Pr[replacement component of type j is good w/r defect type k]
Fundamental Concepts T h e m o d e l i n g a p p r o a c h classifies e a c h step in the a s s e m b l y p r o c e s s l o g i c a l l y as a stage s u c h as p r o c e s s , test, o r r e w o r k ; e a c h is d e s c r i b e d in this s e c t i o n . N o t a t i o n is d e f i n e d as it is i n t r o d u c e d in this p a p e r , b u t it is also s u m m a r i z e d in T a b l e 1 f o r r e a d e r c o n v e n i e n c e . T h e n o t a t i o n that d e f i n e s the p r o b a b i l i t y that a c o m p o n e n t is g o o d as it enters o r l e a v e s e a c h stage is s u m m a r i z e d in T a b l e 2. T h e s y m b o l that d e n o t e s the q u a l i t y input to a stage is a s s i g n e d the suffix " to i n d i c a t e q u a l i t y o u t p u t f r o m that stage. T h e o u t p u t o f o n e s t a g e is the input to the n e x t so that stages m a y b e l i n k e d in series to m o d e l the ( p o s s i b l y u n i q u e ) r o u t i n g o f e a c h p r o d u c t . By appropriate subscripting, a probability notation is m a d e s p e c i f i c to a p a r t i c u l a r c o m b i n a t i o n o f indices; f o r e x a m p l e ,
Probabilities for Circuit Card Quality AL,~ = Pr[accept card on c'~ test cycle [ c cycles] Bi,~ = Pr[accepted card on cth test cycle] I%, = Pr[card is good relative to defect type k] Q~.= = Pr[card is rejected due to components other than n] Sit = Pr[card type i is treated as an exception at test t]
gikntc = P r [ c o m p o n e n t n o n c a r d i is g o o d relative to d e f e c t t y p e k as it enters the c th c y c l e at test t]. T h u s , s u b s c r i p t s r e f l e c t the f u n d a m e n t a l r e l a t i o n s h i p s that d e t e r m i n e q u a l i t y , the l i k e l i h o o d that a c i r c u i t c a r d will be r e j e c t e d at test, a n d the potential o u t c o m e s o f r e w o r k o p e r a t i o n s . T h e s e
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Table 2 Notation Defining Pr [GOOD] for Input to and Output From Each Stage
relationships must be made explicit to understand the effects of test and rework operations on material flow. To apply the models discussed in this paper, a number of parameters must be estimated. An extensive set of data must be collected and statistical issues related to sample size must be addressed (i.e., parameters representing rare events would have to be estimated). Such an activity is beyond the scope of this paper. Nevertheless, this paper does suggest a meaningful approach that could be adopted in practice to analyze operations. Other standard notation is the overbar, which indicates the complement of a probability, for example, gikntc :
QUALITY MEASURES FOR
INPUT
OUTPUT
STAGE CAPABILITy
Vendor
--
~"~
pooling
Pjk,
P"j,
"rest
vj.
?',~
Replacement
__
~"~
Process
p~
p"~
r~
Test
g~
__
ea,~
f~
Rework
__
g"~
u~ x~
w~
Process
H~
H"ik
Test
G.~
__
Rework
__
G"a.
COMPONENTS
Component Level
e,,,,
f~,
Product Level
CIRCUIT CARDS
1--gikntc,
and the symbol ', which is used to indicate a conditional probability, for example, given that a component has been accepted by a test. An assembly system typically produces a variety of products (i.e., circuit cards) indexed by i {i I i = 1 . . . . . I'}. A set of component types ( W i) comprises card i; each is identified individually by the indexn {n I n = l . . . . . N'i}, and the type of each (e.g., a transistor) is denoted Jin.
* Suffix " indicates an output from a stage
requires definition of an additional defect type, k', and, therefore, another set Nit,'. The number of components in each Na, set may thus be small to correctly account for all possible variations. Some types of defects may affect a number of components due to inter-dependencies induced by the circuitry; for example, the failure of an overload protecting device may lead to the failure of several components. Each component may be included in a number of sets, Uu,, because it may be vulnerable to a number of defect types. The quality of a circuit card is evaluated by modeling its quality relative to the set of defects, U' i, to which it is vulnerable. The in-service reliability of a circuit card depends upon the manner in which components are interrelated by circuitry. For example, serial and parallel structures yield different reliability structures. Redundant components may be included in the circuit to extend product lifetime. Nevertheless, the objective of manufacturing is to produce a defectfree product, so that a defective redundant component is just as serious as a defective component connected in series (i.e., one that is not redundant). Circuitry may induce inter-dependencies among components so that a defect type may relate such a set of components in set Nik. Models presented in this paper allow for such possibilities, although a detailed circuit analysis is beyond the scope of this work.
Approach To model test and rework operations, product quality is defined by describing the quality of each component (i.e., the probability that it is good relative to a defect) as it progresses through the system. Each stage has a different impact on quality and is modeled as a logical device that transforms input quality to an output value. For most stages, output quality is determined by a compound event and is modeled by the product of event probabilities; exceptions are discussed in detail. Defects A structured treatment of defects is employed. First, a list of mutually exclusive and collectively exhaustive types of defects {k I k = 1 . . . . . K'} must be prepared. 7 Next, each product must be analyzed to identify the set of components, Nik, that are vulnerable to defect type k. Membership in set Ng k is restricted to ensure homogeneity of constituents; any variation in process, test, rework, or defect
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Processes Each process {m I m -- 1 . . . . . M'} (e.g., component preparation, pre-assembly, assembly, and post-assembly operations) may introduce a set of defect types, 0 m, but it cannot detect or repair defects. It is assumed that each defect is introduced independently of others. The capability of a process is defined by r,m, the probability that process m does not introduce a defect of type k.
component; in fact, it may introduce additional defects through handling and workmanship. The process capabilities of rework operations are described by probabilities u,t c, the P r [rework yields good component I defect k existed]; wt, tc, the P r [defect type k is introduced by c th rework cycle]; and x , t ~, the P r [rework yields good component I defect did not exist]. Should the data be available, these measures could be made more specific by adding a subscript i to indicate characteristics that relate to a particular product. After rework, a circuit card is retested, and may undergo a number of test and rework cycles c {c I c : 1 . . . . , Ct} until it is accepted. However, if it is rejected on cycle Ct at test t, the circuit card is typically treated as an exception, since further attempts using routine procedures would be futile. Exceptions are usually reworked by a skilled specialist to avoid the cost of scrapping. After in-circuit and functional tests, circuit cards progress through additional processes (e.g., storage, handling, system assembly, and burn-in), then system-level test stages, which usually return rejected cards to functional test for diagnosis and fault isolation. In addition, in-service conditions may be modeled as processes that introduce defects, followed by tests that return rejected cards, creating additional test and rework cycles.
Tests A test stage may entail either visual inspection or electronic test, but it cannot introduce or rework defects. Tests may be performed at the component or card (in-process, in-circuit, function, system, and in-warrantee) levels. To distinguish these levels, tests at the component level (e.g., test Tj for component j {j I j = 1 . . . . . J'}) are indexed by 1 {l I 1 = 1 . . . . . L'}; and those at the card level (e.g., test Ti) are indexed by t {t I t = 1 . . . . . T'}. Each test is capable of detecting a certain set of defects, Dt or Dt, including those that are of primary focus as well as others that might be identified incidentally (i.e., as by-products), but cannot introduce or repair defects. Tests are fallible and may identify a defect that does not exist or fail to identify one that does exist. The probabilities of these errors, -eikntc and fi*ntc, respectively, specify test effectiveness. The models described in this paper are based upon the assumption that 100% testing is accomplished at each test. This assumption appears to be realistic in an automated environment in which components are routinely inspected individually, every insertion is checked by assembly equipment, and each circuit card is subjected to a final test. Models could be adapted to reflect sampling plans, should they be of interest in a particular application. Again, this paper discusses a systematic approach for analysis and demonstrates it in deriving models for one scenario of operation; the specific models themselves may not represent all systems.
Sets Relationships among various sets may be clarified by noting that each test may detect a certain set of defects, D t, each process may introduce a set of defects, 0 m, and each type of defect may be introduced by a set of processes, M k. A circuit card is vulnerable to a set of defects, U'i, the union of all sets of defects, Uin, to which its N ' i constituent components are vulnerable.
Modeling Approach Representative models of stages are described in this section. The motivation for modeling all types of stages is to provide a unified description of product quality and test and rework operations.
Rework If a component is rejected by a component-level test, it is eliminated (e.g., by scrapping it). However, defects identified by tests at the card level may be corrected by a rework stage that repairs or replaces rejected components. Rework is an imperfect procedure that may or may not yield a good
Pooling The quality history of a type j component starts with the set of vendors, Vj, that supply it. Each
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vendor, v {v I v = 1 . . . . . V'}, is a process that supplies a portion, O/v, of the requirements for part type j. A component delivered by vendor v has the probability 13"jkv of being good relative to defect k~8~. The term pooling describes a situation in which all components of type j are intermingled so that the probability that a randomly selected component was supplied by vendor v is o/,. If components from the set of vendors are pooled upon delivery Pr [component good on input to pooling[ = P/k~ = Pr [component good as output from vendor] = [3"jk" for all j,k and v. The probability that a randomly selected, pooled component of type j is good relative to defect k is
[type j component is good relative to defect type k at test 1]), or (2) the component is bad relative to defect type k but is incorrectly identified as good (with probability Yjt,l fit,l):
djl = "Yjkl ejkl -]- Vjkl fjkl"
Subscript i is not used, since the components have not yet been assigned to a circuit card. "Yjkl must be set equal to the output probability of the preceding stage, for example, P"jk if pooling precedes this test, or [3"jkv if components are not pooled. Figure 1 depicts the two acceptance conditions for test l I (only subscript k = 1 is shown for clarity). A component accepted by test l = 1 is good with probability gl and defective with probability b 1. A second test l = 2, which checks for defect type k = 2, may be modeled again using Equation (3). Four acceptance conditions result (g~ g2, gl b2, bl g2, and b I b2) a s indicated by Figure 1. A set of L* tests is represented by a series of L* stages, each modeled by Equation (3) and each providing the input quality to the subsequent stage. 2L* states of quality result upon completion of the L* tests. Component quality may thus be defined by a vector in which element k gives the probability that the component is good relative to defect type k. The probability that a component of typej is good relative to defect k given that it is accepted at test l, Y'jkt, may be determined by dividing the probability that a good component is accepted (Yjkl ejkl) by the probability of acceptance
P'~ik ---- ~v, Vj Pjkv O/v ---- ~'v~Vj ~"jkv Ojv; for each ke8 v-
(1)
P"jk is, thus, a weighted average of all vendorsupplied qualities. The quality of a pooled component of type j is defined by the vector with elements {P"jk I k~8,} that relate to the set of defects 8~ that may be introduced by vendor v. The probability that a component of type j is good with respect to all defects introduced by vendors is:
Pr [pooled component is good relative to all keSv] = IIk,~v i f ) k ,
(3)
(2)
and the number of good components in a pool of size P has the binomial distribution with mean E [number of good components] = P Ilk~v p"jt,.
Y'jkt = Y/k, e/k,/ d/,.
If components are not pooled, the subscript v must be retained so that the quality of a component is given by 13"jkv. The capability of tracking vendor-supplied materials may be important, for example, in systems that produce military hardware, since they are usually required to record the source of all materials assembled into a product.
(4)
Similarly, the conditional probability that an accepted component is not good is: ~ )kl = ~ / k l & l / djl"
(5)
The number of components of type j that will be accepted from a lot of size P has the binomial distribution, so
Component-Level Tests
E [number components accepted by test l] = P d/1.
Component-level tests, I~Tj, screen defectives. It is assumed that each test checks for a single defect type (IDtl = 1), so the probability, d/t, that a component will be accepted by test l is the union of compound events: (1) the component is good relative to defect type k and is correctly identified as such (with probability Yjkt e/~a where Yjkl is the Pr
(6)
Given that it is accepted at component-level tests, the probability
Pr [a type j component is good relative to all defects checked by component-level test Tj I accepted] = Hl~rj Hk~o, Y~kr
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The set of assembly processes Zi is required to assemble circuit card type i. Process m~Zi may introduce defects keO,,, through faulty operations or by damaging components. For example, leads may be tarnished in storage, incorrect components may be kitted, and an insertion machine may insert the wrong component or fail to insert one. It is assumed that processes do not detect defects and are not affected by them. A component input to process m is good with probability Pikm,,, and it is good upon output if the process does not introduce a defect:
REJECT
ACCEPT
REJECT
ACCEPT
D"ikmn :
Pikmn rkm"
(8)
Equation (8) models each process in the routing of product i, me Zi, for each component n and defect keOm; several additional measures of quality are summarized in the following. The probability that a component is good relative to an assembly defect is given by Equation (8); the Pr [bad relative to insertion defect k] : Pikmn Ykm
REJECT
Pr [bad relative to handling defect k] = 1-pikm n II,n~r ' rl,m
ACCEPT
(10)
in which Equation (9) describes the incidence of a defect that may be introduced at only one process, while Equation (10) gives the likelihood of one that may be introduced by a number of processes. Since a single component may be vulnerable to more than one defect type (i.e., I U~,, I>- 1), its quality upon output at process m is described by a vector {p' 'it,m,,
Figure 1 Two Independent Tests in Series at the Component Level
If components are pooled after component-level test l rather than before, ~l' 'jkl :
(9)
Circuit Card Quality The probability that a circuit card is good relative to defect k as it leaves process m is the probability that no constituent components are bad. Components neNik are vulnerable to defect type k; each has the probability P"ikmn of being good relative to defect k so circuit card quality (i.e., the probability that the card is free of defects of type k upon output from process m, H"ik) is
~v~Vj Pjkv ejkt Ojv,
a weighted average over all suppliers of the probability that a vendor supplies a good component and it is accepted by the test. Processes Component Quality An inventoried component is allocated to assemble a specific product, for example, as it is placed in the kit of components required to assemble the product. After components are assigned to cards, quality is best analyzed by treating the N'~ individual components assigned to a particular card.
n"ik
:
[IneNjk P"ikmn"
(11)
The probability that the card is defect-free is the product of the probabilities that it is good relative to each type of defect: Pr [card has no defects] = IIk~v, H"ik.
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Of the INikl components assembled at process m (which may introduce defect type k), the number of components with defect type k is a random variable with the binomial distribution, so
Circuit Card Test and R e w o r k
The probability of accepting all components in the set Nik on cycle c {c I c = 1 . . . . . Ct} is IN,d
l~neJV ik aikntc = aikntc'
E [number of components with no defect type k] = rkm I Nik I E [number of components with defect type k] = rkm I N/kl.
and the probability of accepting the circuit card on test cycle c, Air~, is
Aitc
(13)
:
tN,klc iik~o, ii,,~v,, aikntcO aiknt
E [number of components reworked on cycle c] = ~k~o, ~iikntc INikl.
(15)
(16)
The distribution of the number of rejected components is important, since it describes the workload placed on rework operations. The probability that a card is rejected Ct times and, thus, handled as an exception is
Component Test~Rework
Entering the first cycle of test t (c = 1) component quality is denoted g~knt~ for keD t. A component accepted on the c th cycle may be good and correctly identified as such, or bad and incorrectly accepted. The probability that a component will be accepted is gikntc eikntc + g ikntcfikntc"
likeD,
The card is rejected with probability ~itc. The number of rejected components in the set Nik has the binomial distribution with expected value dik,,tc INit,I, and the expected number of components reworked for all defect types keD t is
Test and Rework Operations Assembled circuit cards are subjected to a series of in-circuit and function tests, t¢T i. If a circuit card is rejected by test t, it must be reworked and subsequently retested; after C t rejections, it is assumed that it will be handled as an exception.
aikntc :
:
Sit :
(17)
l-Ict l -Aitc.
S i m i l a r l y , Bitc, for c : 1 . . . . . C t, gives the Pr [card is accepted by test t on the Cth cycle] as
(14)
Conditioned upon acceptance, the quality of a component is:
r
Pr [component is good relative to defect k I accepted on cycle c] = gikntc eikntc / aikntc"
Bit c
Tests for multiple defects (IO t I > 1) may be modeled either by defining g to reflect all k¢D t or by using Equation (14) for each k¢D t and basing acceptance on all defects:
:
Ait c
for c = 1
J
c-! 1 7"itc' f o r 1. Aitc He'=
(18) c -- 2 . . . . . C,
The E [number of test and rework cycles for a card] = E c - i c Bit c q- C t Sit
Pr [accept component relative to all kcDt] =
(19)
likeD, aikntc.
Rework Rework may entail a variety of procedures since some defects are reparable and others require component replacement.
One test and rework cycle (c -- 1) for a component is depicted in Figure 2 (only subscript c is shown for clarity). A rejected c o m p o n e n t is reworked (R~); if it is bad, the rework operation would make it good again with probability u 1 (1) or fail to do so with probability ~l (2). If the component is good, rework could introduce a defect with probability w~ (3) or yield a good component with probability wz (4). These outcomes, shown in Figure 2, define component quality as it enters the next test cycle.
Repair
Reparable defects include solder bridging and misoriented components. It is assumed that defects are mutually independent and that they are repaired one at a time. Figure 3 depicts a test and rework cycle relative to a card (only subscript c = 1 is shown for clarity).
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1
ot ~
gl~ux
C 5]
g~Exw~
REJECT
gl~l~/l BOARD REJECTED
ACCEI~I" glel
'~(~)
:
(20)
Qik~tc = Pr [circuit card is rejected due to defects identified on components other than n] 1-Air c / IIkeu,jqD, aiknt c
g,g,
r,.
g,f,
4.s. g,e,x,w,
Replacement Equation (20) must be modified if rework entails replacement rather than repair. Suppose component n is to be replaced on circuit card i. The replacement component must be of type j = Jin, and its quality (i.e., the probability that the replacement component is good relative to defect type K~Uin, "q')k) must be described as a function of the componentlevel tests and intervening handling processes that it experiences. With replacement, the probability that a component is good as it begins the (c + 1)st cycle is determined by three compound events: (1) the component was bad, correctly rejected, replaced with a good one and a defect is not introduced during rework; (2) the component was good, incorrectly rejected, replaced with a good one, and a defect is not introduced during rework; or (3) the component was good, correctly accepted, and not damaged during the rework of rejected components
in which the probabilities of compound events (1)-(3) are listed in order. Tests may induce interdependencies, since components that are not the cause of a circuit card being rejected still must travel with the rejected card through rework operations. This possibility may be expressed as:
:
g,~,
4.
An effective rework operation should improve identified defects, but it may also introduce additional defects (e.g., due to overloading, soldering, and thermal damage) or unmask 7 others that might be detected upon retesting. Actual test and rework operations may induce inter-dependencies among components (e.g. See Equation (21)). Such a dependency may be a function of the circuitry on a particular card and is beyond the scope of this paper, which invokes the assumption that test and rework operations are independent and lead to certain inherent approximations. In any event, gikntc is not necessarily constant for all cycles.
g"ikntc gikntc fikntc Uktc Wktc -~- gikntc ~ikntc Yktc Wktc -~- gikntc eikntc Qikntc Wktc
~,r,
a.
Test/Rework Cycle for a Circuit Card
Cycle for a Component
The probability that a component is good as it emerges from the c th repair [beginning the (c + 1)st cycle] is determined by three compound events: (1) a bad component is rejected, repaired correctly and a defect is not introduced during rework (path 6-7 in Figure 3); (2) a good component is rejected, repaired correctly and a defect is not introduced during rework (path 4-8 in Figure 3); or (3) a good component is accepted at test, must cycle through rework because other component(s) are rejected, and a defect is not introduced during rework (path 3-9 in Figure 3): giknt,c + 1 :
g,¢,
Figure 3
Figure 2 Test/Rework
t. 2.
(21)
in which the defect types in set Ui. N D t are those checked at test t to which component n is vulnerable.
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giknt, c + 1 ~--- -gikntc fikntc ~ j k Wktc qgikntc ~ikntc "q j k Wktc q- gikntc eikntc Qikntc W--ktc
System variety and scale are limited in this example only to focus on underlying relationships. Test cases were defined by the parameters used to describe vendor, process, test, and rework capabilities. To facilitate understanding of results, parameters (r = e = f = u = w = x for all ikntc) were set equal to 0.9, 0.99, 0.9999 and 0.999999, respectively, to define the four test cases. These quality measures reflect a range of capabilities from relatively poor to relatively good (one part per million error). C t was set to 5 and the ultimate disposition of exceptions was not considered. This data defines the two vendors to be identical with respect to quality and also makes repair and replacement types of rework equivalent, since u~tc qq'' jk. Measures of quality are displayed in Table 3; the equation used to calculate each is noted. Rejected components are scrapped at componentlevel tests l = 1 and l = 2. The measure E [lot size after test l] indicates the expected number of components that are accepted at test I and quantifies the reject rate at that test. Clearly, tests should be ordered, if possible, with the one expected to reject the largest number of components first, so that effort is not expended to test a component for several defects before it is likely to be rejected for another cause at test 1. This analysis indicates the damning effects of multiple components on a circuit card. Even though a given component is of high quality, the likelihood that the card will be defect free is relatively small. If a card is vulnerable to a total of K defects and its quality must be within e of 1.0, then the (assumed equal) probability, t~, of being good relative to each defect must satisfy
(22)
in which the probabilities of the compound events (1)-(3) are given in order. R e p a i r or R e p l a c e m e n t
Some defects may be reworked either by repair or replacement. Data on actual operations could be used to estimate the relative frequencies of these two procedures: pN = P r [type j component is replaced] pF = P r [type j component is repaired].
Component quality entering the (c + 1)st test cycle is then giknt, c+ l -- p N giknt, c+ l(22) + p p giknt, c + 1 (20)
in which the arguments indicate defining Equations (20) and (22).
Analysis of Test and Rework Operations This section is intended to foster insight into the effects that test and rework operations have on material flow in circuit card assembly.
Numerical Example An example composed of hypothetical, representative data is discussed in this subsection. J' --- 2 types of components are considered; each is supplied by two vendors (I V j I = 2 and oj, = 0.5). The system is composed of five processes (M' = 5): 2 vendors, 2 assembly machines, and 1 soldering process. Each component is vulnerable to five (I Ui, I = 5) types of defects: mechanical and electrical defects "as received," assembly fault at one of the two machines, damage by handling, and faulty soldering. Vendors supply components in lots of size P = 1000, and two component-level tests check for the "as received" defects. Subsequently, a circuit card is assembled using 100 of each component type. This scenario reflects the features found in actual systems; a circuit card may, in fact, contain two types of components that progress through five stages: vendor preparation, pooling, component-level test, assembly, and soldering.
1.0--e <- qjx < 1.0 and is given by --- + - < I . 0
.
As K increases, the effect of multiple components can be ameliorated only by requiring each component to be of very high quality, t~. Tests t = 3, 4, and 5, performed after assembly, check for defect types k = 3, 4, and 5, respectively. Components rejected at test 4 require replacement, while those rejected at tests 3 and 5 can be repaired. Since Uktc = ~q"j k is assumed, all tests give the same results, so only one is described in Table 3.
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Table 3
Due to the effect of multiple components, there is a relatively high probability of rejecting a circuit card, but the expected number of components that require rework is small. Consequently, many components are exposed to handling defects while a few are reworked. With poor quality capabilities (Case 1), it is highly likely that a circuit card will be treated as an exception after five test cycles. Component quality is actually degraded by poor workmanship at rework and the expected number of components reworked increases with c. In this case, the probability of rejecting a circuit card and the amount of rework required increases at every test and rework cycle. Clearly, this result could lead to bottlenecks in work flow that would not be predicted by the usual assumptions discussed in the introduction. With good quality capabilities (Case 4), a circuit card will be accepted, likely on an early cycle. Test fallibility may, in fact, lead to more rejected components than will component quality itself if a good component is rejected with a greater likelihood (gi*ntc eikntc) than that of accepting a bad component (git,,tc Jit,,,tc). Rework may either maintain or improve quality as c increases. In high quality cases, good components that are falsely rejected may constitute the primary workload on a rework station. If replacement components have relatively poor quality or if defects are likely to be introduced by rework, quality might actually be degraded as c increases. On the other hand, test fallibility may introduce another paradox: the actual quality of a circuit card may be good if it is accepted after a number of cycles, but may be relatively poor if it is accepted on an early cycle, since bad components may be accepted erroneously on the first test cycle. This example demonstrates that test and rework operations must be analyzed carefully to correctly assess their impact on material flow. Bottlenecks that cannot be predicted by simple, pragmatic analysis may develop due to process capabilities as demonstrated in this example.
Test Results + Deseript Ion
Symbol
VENDORS Ptlgond w/r kl Prlgcod wit all k] INCOMING TESTS Prlaccept /=11 Pr[good hccept]
I~rrorlnan~ Mcuures Case #3 Case #3
Case #4
I 2
09 081
0.99 0.9801
0.9999 0.9998
0.999999 0.999998
dj~
3 4
0.82 0.987805
0.9802 0.999898
0.9998 1,0
0,999998 1,0
6 6 7
820.0 672.4 0975759
980.2 960.792 0,999796
9998 999.6 1.0
999.998 999.996 1.0
8 lI 12 13
0,9 0.000027 1.8E-14 10,0
0.99 0366032 0490408 10
0,9999 099049 0.97174 0.01
0.999999 0.9999 0.9997 O.t3001
18 18 18 18 18 18 19
0.2E-08 0.19E-09 0 13E-09 0.12E-09 0.12E-09 1.0 5.0
0.135354 0.113631 0.986406 0.856839 0,7443 0.492261 3.82337
0.980199 0.019409 0.000384 0.76E-05 O. 15E-06 0.30E-08 1.0202
0.9998 0.11001)99 0 4E~07 08E-11 0.2E-14 0.3E-18 1.0002
20 20 20 20 20 16 16 16 16 16
0.9 08748 0870718 0.870056 0.869949 18,0 20.016 20,M26 20.3955 20.4041
0.99 0.989705 0.989699 0.989699 0.989699 1.98 2.00891 200948 Z00949 2,00949
0.9999 0.9999 0.9999 0,9999 0.9999 0,019999 0.020001 0.020~1 0.020001 0.0200O1
0.999999 0.999999 0.999999 0.999999 0.999999 0.0002 0.0002 0.0002 0.0002 0.0GO2
Y'jk~
ASSEMBLY PROCESSES pr[good w/r k] p"Lj~ Pr[CC good w/r kl Ha Pt~CC good w/r all kJ E[# components with kl
Pr[exception]
Case #1 9"j~
E[Lot size after/=11 E[Lot size after/=21 prlgood w/r all kl
TEST CYCLES Pr[accept ]c=li Pr[accept [c=2l Prlaccept ~c=31 Pr[accept ~c=41 Pr~accepc~-51
ElI
B,~ Bia Bio B,,( B,~ S,~
E[# cycles]
REWORK Pr[good k= I ] Pr[good 1c=21 Prigood [c=-31
g~ g,~z 8~ Pdgood ~c=41 g~ Pr[good ]c=51 ga~o El# comp rcworked on c=l] El# comp reworked on c=2) E[# comp n~workedon c=31 El# comp reworked on C--41 El# comp reworked on c=5]
LEGEND CC indicates "circuit card" w/r indicates "with respect to" + To 6 decimal place accuracy unless given in scientific notation
operations (column 7) is linear in each parameter. The last column tallies the total number of operations in the large-scale example defined at the bottom of the table. At a speed of 100,000 operations/second, a runtime of only 2.3 minutes would be required to model this hypothetical large-scale system.
Discussion The cost associated with test and rework cycles are, of course, a matter of primary concern to the manager and may be described by accumulating the costs of each cycle using the notation
T/g
~---
total cost of test and rework at test t cost of queueing at rework on cycle c
Computational Analysis Computational requirements to implement the model discussed in this paper are described in T a b l e 4, which itemizes the number of arithmetic operations required by each equation. The total number of
176
c ./c =
cost of queueing at test t on cycle c
cL=
rework cost for the c th cycle at test t
c,'.,c =
cost of testing on the c th cycle at test t
C~t
cost of handling a card as an exception on cycle C v
=
Journal of Manufacturing Systems V o l u m e l I/No. 3
Table 4
This paper describes an approach for modeling test and rework operations in circuit card assembly, applies the approach to derive models that are representative of typical systems, and uses a numerical example to foster insight into the effects of test and rework operations on material flow. The example demonstrates that it is possible to quantify the effects of component quality, process capability, test fallibility, replacement parts, and imperfect rework on material flow at test and rework operations. For example, in an environment with high quality parts (e.g., with one defect per million parts), test fallibility may lead to more rejects than will bad components. Furthermore, poor workmanship at rework may degrade the quality of a circuit card, requiring more rework at each cycle. Thus, in some cases, a good card could be falsely rejected initially and its quality could be degraded by successive rework operations. It is important to balance the quality capabilities of the various elements in the quality control plan. For instance, only incremental gains may be achieved by improving component quality without also improving test fallibility and rework workmanship. Each of these elements has an important influence on material flow and upon the creation of bottlenecks at test and rework operations. Industry typically assigns the cause of a rejection to one of a few causes that lump together defects that might actually be attributed to a variety of causes. This practice is expedient, but it masks the real reasons for problems and precludes appropriate process corrections. The modeling approach presented in this paper, as well as more sophisticated models that might be developed through future research to incorporate dependencies between circuitry and function, should help to understand the process and the product so that necessary process corrections can be identified and implemented more readily.
ComputationalR e q u i r e m e n t s Step
Eq # Div
Exp
Add
Mult
# Ops
xl04
]Vj [-1
IVj I
J'(2 Iv, l- l)
0.5
t
3
5J' tr, I
1
r~l ~,1
13 6.0
2
3 I' C, tY,[
0.1
~Dt I
l'C~ ~r,[ ( b , ~ b
2.7
10 + ]U= c~ D, I
I ' c , ~I',1(14 + IU=nDO
3.I
Tit, may be expressed as = + C,'.] + Ci, S,t + c,c=2 Aitc,] [c~tr~'-t + Crt:'-, + C~ttc' + C,t,~']•
(23)
Pooling I Com!aonent Test 3,4 Process
8
Test
15
Cycle c
16
Rework
22
1
I 1 1
3
lo~l
REPRESENTATIVE PARAMETER VALUES FOR A LARGE-SCALE APPLICATION V~riable Number I' 3000 J' 50OOO 5
I
40
~. I
10
~71
5
,
3
c,
3
tD, I
loo
lug-o, I i00
LEGEND Eq# Div Exp Add Muir #Ops # l06
Equation number Number of divisions Number of exponenfiations Number of addition operations Number of multiplication operations Number of aritbematic Operations Number of operations in numerical example (xl06)
Total cost,
Tit includes the cost of queueing and testing on the first cycle, the expected cost of being handled as an exception, and the expected cost for other cycles, counting rework (cycle c'-l) and test (cycle c') in the last term in Equation (23). The product term in the brackets defines the probability that c test cycles will be incurred. The costs of in-process inventories, C~tr and C~tt~,may be estimated by inputting the reject probabilities and rework workload described by the model into another model, z6 which would estimate the queueing that would result in the flow of materials due to the quality control plan. The total cost model in Equation (23) gives a detailed way of relating costs to each element in the quality control plan. In comparison, Fu et al. 9 estimate costs using only the probability that a circuit card is accepted, scrapped, or reworked. Suri, Sanders, and Mody z° describe the importance of evaluating all cost components to overall competitiveness.
Acknowledgements This material is based on work supported by the National Science Foundation under grant numbers DMC-8500898 and DDM-9114396.
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Journal of Manufacturing Systems Volume I I/No. 3
References
Slam, John Wiley and Sons, 1979. 15. J. Richards, "Integrated Assembly, Testing and Rework in Automated Electronics Manufacturing," Proceedings, Annual Industrial Engineering Conference, 1984, pp. 495-501. 16. S. Saboo, L. Wang, and W.E. Wilhelm, "Development and Application of Models to Manage Material Flow in Printed Circuit Board Assembly," Management Science, Vol. 35, No. 6, 1989, 722-42. 17. A. Seidmann and S.Y. Nof, "Unitary Manufacturing Cell Design with Random Product Feedback," liE Transactions, Vol. 17, No. 4, December 1985, p. 403. 18. A. Seidmann, P.J. Schweitzer, and S.Y. Nof, "Performance Evaluation of a Flexible Manufacturing Cell with Random Multi Product Feedback Flow," International Journal of Production Research, Vol. 23, No. 6, November/December 1985, pp. 1171-85. 19. A.J. Strumar, "Flexible Manufacturing Systems for Electronics," Proceedings, Electronics Assembly Conference, Atlanta, GA, October 1985. 20. R. Suri, J.L. Sanders, and A. Mody, "International Implications of Modem Technologies and Practices: Some Initial Findings," Ricerca Operativa, Vol. 55, 1990, pp. 59-99. 21. L.S. White, "Shortest Route Models for the Allocation of Inspection Effort of a Production Line," Management Science, Vol. 15, No. 5, January 1969, pp. 249-59. 22. B.J. Yum and E.D. McDowe[I, "The Optimal Allocation of Inspection Effort in a Class of Nonserial Production Systems," liE Transactions, Vol. 13, No. 4, December 1981, pp. 285-93.
1. "Soldering, Cleaning, Test and Rework in Electronics Assembly," Assembly Engineering, May 1985, pp. 66-74. 2. D.P. Ballou and H.L. Pazer, "The Impact of Inspector Fallibility on the Inspection Policy in Serial Production Systems," Management Science, Vol. 28, No. 4, 1982, pp. 387-99. 3. R.R. Britney, "Optimal Screening Plans for Nonserial Production Systems," Management Science, Vol. 18, No. 9, May 1972, pp. 550-59. 4. J.A. Buzacott and D.H.W. Cheng, "Quality Models of Assembly Systems," Proceedings, Winter Simulation Conference, 1982, pp. 361-71. 5. J.A. Buzacott and B. LeBlanc, "Quality Models of Printed Circuit Board Assembly," Presented at the TIMS/ORSAJoint National Meeting, Los Angeles, CA, April 14-16, 1986. 6. R.D. Collins, K.E. Case, and G.K. Bennett, "Inspection Error and Its Adverse Effects: A Model with Implications for Practitioners," liE Transactions, Vol. 10, No. I, 1978, pp. 2-9. 7. B.J. Dooley, " A Model for the Prediction of Assembly, Rework and Test Yields," IBM Journal of Research and Development, Vol. 27, No. 1, 1983, pp. 59-67. 8. T.S. Ellington, "Cost Optimization Utilizing Reference Techniques (COURT)," Western Electric Engineer, Vol. 15, No. 1, January 1971, pp. 25-32. 9. B. Fu, C. Falkner, R. Suri, and S. Garlid, "Combining Economic Analysis and System Modeling to Evaluate Test Strategies for Circuit Board Assembly Lines," Productivity and Quali~ Improvement in Electronics Assembly, Chapter 34, McGraw-Hill, 1989. 10. A. Garcia-Diaz and J.W. Foster, "Optimal Allocation of Repeated Inspection in a Class of Nonserial Production Processes," Proceedings, Annual Industrial Engineering Conference, 1982, pp. 566-7 I. 11. A. Garcia-Diaz, J.W. Foster, and M. Bonyuet, "Dynamic Programming Analysis of Special Multi-Stage Inspection Systems," liE Transactions, Vol. 16, No. 2, June 1984, pp. 115-26. 12. S.I. Gunter and L.A. Swanson, "Inspector Location in Convergent Production Lines," International Journal of Production Research, Vol. 23, No. 6, November/December 1985, pp. 1153-70. 13. G.F. Lindsay and A.B. Bishop, "Allocation of Screening Inspection Effort--A Dynamic Programming Approach," Management Science, Vol. 10, No. 2, January 1964, pp. 342-52. 14. A.A.B. Pritsker and C.D. Pegden, Introduction to Simulation and
Author's Biography Dr. Wilbert Wilhelm is a Professor in the Industrial Engineering Department of Texas A&M University. He received his BS in mechanical engineering from West Virginia University and his MS and PhD degrees from the Department of Industrial Engineering and Operations Research at Virginia Polytechnic Institute. He is a registered Professional Engineer and a member of ORSA, liE, and SME. He is currently the Director-Elect of the ORSA Special Interest Group on Manufacturing Management (SIGMA), a Co-Editor of the Department of Planning/Scheduling/Control for liE Transactions, and the Editor of the special issue on lie Transactions on scheduling and logistics, and a member of CICMHE.
178
The Effects of Test and Rework Operations on the Flow of Materials in Circuit Card Assembly W.E. Wilhelm, Texas A&M University, College Station, TX
Abstract
The incidence of test and rework cycles is determined by the system-wide quality control plan that integrates the quality of vendor-supplied components, the capabilities of assembly processes, the strategy of testing, and the workmanship at rework stations to achieve corporate objectives for product quality. Models used to analyze material flow often take a pragmatic view of this complex phenomenon, assuming an equal probability of rejection on each test cycle as well as independent and identically distributed operation times at each cycle. 14A5'17'18 Models that invoke these assumptions typically do not predict the bottlenecks that frequently occur at test and rework operations. The objective of this paper is to apply the fundamental axioms of the probability theory to better understand the phenomena that might lead to flow bottlenecks at test and rework operations in circuit card assembly systems. Since each assembly system may be unique (for example, due to product design or the assembly processes employed), a systematic approach is required so that a model may be easily derived for each specific case of interest. To achieve this objective, the fundamental axioms of the probability theory are utilized to suggest such a systematic approach. Circuit cards are used as a focus because they are crucial to numerous modern products and present certain worst case challenges to analysis. Results are thus applicable to circuit card assembly, but it is expected that the method of analysis may find general application in industry. Models that describe quality capabilities have been based on the binomial distribution, 4 Markov chains, 3 thruput rates,13 and fundamental probability axioms. In related models, a rejected product may be scrapped, 10'12 replaced by a good one, 21 repaired instantaneously, 22 reworked, 4's'15 or cycled through test and rework until accepted. 17-18
This paper presents a structured approach for analyzing the effects of test and rework operations on material flow in systems that assemble circuit cards. Stages that affect quality (e.g., vendor preparation of components, pooling, assembly processes, and test and rework) are identified and representative models of each are presented. Each product is treated as a composite of multiple components, each of which is vulnerable to a variety of defects. Test is treated as fallible and rework as imperfect. Several procedures that accomplish rework are considered. Examples demonstrate some fundamental effects of test and rework operations on material flow. Management implications for improving material flow are discussed.
Keywords: Material Flow Management, Effects of Quality on Material Flow, Test and Rework Operations, Probability Model of Quality, Circuit Card Assembly
Introduction Material flow may interact with quality control in a number of ways. For example, the length of a queue may influence the production rate of an operator and affect the quality of his work. Tests may identify defective workpieces that must be scrapped, reducing flow rates. Other types of defects can be repaired so that materials are cycled between test and rework stations until deemed acceptable. Test and rework operations are particularly important in systems that assemble circuit cards, since they are typically lengthy, require highly variable times, and often lead to flow bottlenecks. As systems automate, understanding the nature of test and rework operations becomes even more important since rejects may require specialcase routing and handling.
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Journal of Manufacturing Systems Volume l l/No. 3
Tablel Notation
P r o d u c t s are t y p i c a l l y a s s u m e d to e x h i b i t a single t y p e o f d e f e c t , a l t h o u g h m u l t i p l e d e f e c t s h a v e also b e e n m o d e l e d . 4'7 I n s p e c t i o n s are m o s t o f t e n a s s u m e d to b e p e r f e c t , b u t fallible i n s p e c t i o n ( g o o d p r o d u c t s m a y be r e j e c t e d a n d d e f e c t i v e o n e s accepted),2'4'7 repeated inspection,l~ and sampling 6 h a v e b e e n treated. A n u m b e r o f studies deal w i t h q u a l i t y c o n t r o l o f e l e c t r o n i c s in g e n e r a l 8'ls a n d circuit c a r d a s s e m b l y in particular. ~'~9 C i r c u i t c a r d test p r o c e d u r e s h a v e been studied using simulation, 4 and rules for sequencing r e w o r k h a v e b e e n e v a l u a t e d , s'15 D o o l e y 7 d e v e l o p e d a m o d e l o f circuit c a r d q u a l i t y . His m o d e l is l i m i t e d , h o w e v e r , s i n c e it c o n s i d e r s the f l o w o f d e f e c t s r a t h e r than circuit c a r d s . F u et al. 9 a n a l y z e the relative c o s t s o f w o r k in-process (WIP), materials, equipment, labor, maintenance, and overhead using a macroscopic m o d e l that relates these c o s t s to the p r o b a b i l i t y that a circuit c a r d is a c c e p t e d at test. T h e i r m o d e l d o e s not, h o w e v e r , d e v e l o p the p r o b a b i l i t y o f a c c e p t a n c e as a f u n c t i o n o f the s y s t e m - w i d e q u a l i t y c o n t r o l p l a n as d o e s this p a p e r . Suri, S a n d e r s , a n d M o d y 2° d e s c r i b e an e m p i r i c a l s t u d y that c o m p a r e s the c o s t s o f a s s e m b l i n g circuit c a r d s in d e v e l o p e d c o u n t r i e s , n e w l y i n d u s t r i a l i z e d c o u n t r i e s , a n d less d e v e l o p e d c o u n t r i e s . T h e y e m p h a s i z e that n e w l y i n d u s t r i a l i z e d countries gain a competitive advantage through h i g h e r q u a l i t y , w h i c h entails less s c r a p a n d l o w e r W I P costs.
Indices c = 1..... Ct i -- 1..... I' j = 1..... J' k = 1..... K' l = 1..... L' m = 1..... M' n = 1..... N'~ t = 1..... T' v = 1, .... V' Sets Dt Mk N~, O,. Ti Tj
U~, U'i Vl W~ Zl 5v
numberof times test t is performed products(i.e., circuit cards) componenttypes defecttypes tests at the component level processes
individual components on card i tests at the circuit card level vendors
= = = = = = = = = =
{k I defect type k is detectable at test t} {m I process m can introduce defect type k} {n [ component n is vulnerable to defect type k} [k [ defect type k may be introduced at process m} {t [ test t is performed on card i after assembly} {l I test I is conducted on component type j } {k [ defect type k affects component type j on card i} {k [ defect type k affects circuit card i} {v I vendor v supplies component type j} {j I component type j is assembled on card i} {m I process m is required to assemble card type i} = {k [ defect type k introduced by vendor v}
Parameters
oi, J,.
= portion of type j components supplied by vendor v = type of (specific) component n on card i
Probabilities Associated with Process Capabilities e~t, = Pr[test calls component good ] component is good] f ~ = Pr[test calls component good [ component is bad] r~ = Pr[defect type k is NOT introduced at process m] uk~ = Pr[rework yields good component I defect k existed] wm = Pr[defect type k is introduced by c~ rework cycle] Xkffi = Pr[rework yields good component I defect did not exist] Probabilities for Component Quality .a~,, = Pr[accept component on cth test/rework cycle] dj~ = Pr[accept component at test/] g~,, = Pr[component is good coming into cth test cycle] ~a = Pr[type j component is good relative to defect type k at test/] Y'iu = Pr[type j component is good I accepted by test/] rl"~, = Pr[replacement component of type j is good w/r defect type k]
Fundamental Concepts T h e m o d e l i n g a p p r o a c h classifies e a c h step in the a s s e m b l y p r o c e s s l o g i c a l l y as a stage s u c h as p r o c e s s , test, o r r e w o r k ; e a c h is d e s c r i b e d in this s e c t i o n . N o t a t i o n is d e f i n e d as it is i n t r o d u c e d in this p a p e r , b u t it is also s u m m a r i z e d in T a b l e 1 f o r r e a d e r c o n v e n i e n c e . T h e n o t a t i o n that d e f i n e s the p r o b a b i l i t y that a c o m p o n e n t is g o o d as it enters o r l e a v e s e a c h stage is s u m m a r i z e d in T a b l e 2. T h e s y m b o l that d e n o t e s the q u a l i t y input to a stage is a s s i g n e d the suffix " to i n d i c a t e q u a l i t y o u t p u t f r o m that stage. T h e o u t p u t o f o n e s t a g e is the input to the n e x t so that stages m a y b e l i n k e d in series to m o d e l the ( p o s s i b l y u n i q u e ) r o u t i n g o f e a c h p r o d u c t . By appropriate subscripting, a probability notation is m a d e s p e c i f i c to a p a r t i c u l a r c o m b i n a t i o n o f indices; f o r e x a m p l e ,
Probabilities for Circuit Card Quality AL,~ = Pr[accept card on c'~ test cycle [ c cycles] Bi,~ = Pr[accepted card on cth test cycle] I%, = Pr[card is good relative to defect type k] Q~.= = Pr[card is rejected due to components other than n] Sit = Pr[card type i is treated as an exception at test t]
gikntc = P r [ c o m p o n e n t n o n c a r d i is g o o d relative to d e f e c t t y p e k as it enters the c th c y c l e at test t]. T h u s , s u b s c r i p t s r e f l e c t the f u n d a m e n t a l r e l a t i o n s h i p s that d e t e r m i n e q u a l i t y , the l i k e l i h o o d that a c i r c u i t c a r d will be r e j e c t e d at test, a n d the potential o u t c o m e s o f r e w o r k o p e r a t i o n s . T h e s e
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Table 2 Notation Defining Pr [GOOD] for Input to and Output From Each Stage
relationships must be made explicit to understand the effects of test and rework operations on material flow. To apply the models discussed in this paper, a number of parameters must be estimated. An extensive set of data must be collected and statistical issues related to sample size must be addressed (i.e., parameters representing rare events would have to be estimated). Such an activity is beyond the scope of this paper. Nevertheless, this paper does suggest a meaningful approach that could be adopted in practice to analyze operations. Other standard notation is the overbar, which indicates the complement of a probability, for example, gikntc :
QUALITY MEASURES FOR
INPUT
OUTPUT
STAGE CAPABILITy
Vendor
--
~"~
pooling
Pjk,
P"j,
"rest
vj.
?',~
Replacement
__
~"~
Process
p~
p"~
r~
Test
g~
__
ea,~
f~
Rework
__
g"~
u~ x~
w~
Process
H~
H"ik
Test
G.~
__
Rework
__
G"a.
COMPONENTS
Component Level
e,,,,
f~,
Product Level
CIRCUIT CARDS
1--gikntc,
and the symbol ', which is used to indicate a conditional probability, for example, given that a component has been accepted by a test. An assembly system typically produces a variety of products (i.e., circuit cards) indexed by i {i I i = 1 . . . . . I'}. A set of component types ( W i) comprises card i; each is identified individually by the indexn {n I n = l . . . . . N'i}, and the type of each (e.g., a transistor) is denoted Jin.
* Suffix " indicates an output from a stage
requires definition of an additional defect type, k', and, therefore, another set Nit,'. The number of components in each Na, set may thus be small to correctly account for all possible variations. Some types of defects may affect a number of components due to inter-dependencies induced by the circuitry; for example, the failure of an overload protecting device may lead to the failure of several components. Each component may be included in a number of sets, Uu,, because it may be vulnerable to a number of defect types. The quality of a circuit card is evaluated by modeling its quality relative to the set of defects, U' i, to which it is vulnerable. The in-service reliability of a circuit card depends upon the manner in which components are interrelated by circuitry. For example, serial and parallel structures yield different reliability structures. Redundant components may be included in the circuit to extend product lifetime. Nevertheless, the objective of manufacturing is to produce a defectfree product, so that a defective redundant component is just as serious as a defective component connected in series (i.e., one that is not redundant). Circuitry may induce inter-dependencies among components so that a defect type may relate such a set of components in set Nik. Models presented in this paper allow for such possibilities, although a detailed circuit analysis is beyond the scope of this work.
Approach To model test and rework operations, product quality is defined by describing the quality of each component (i.e., the probability that it is good relative to a defect) as it progresses through the system. Each stage has a different impact on quality and is modeled as a logical device that transforms input quality to an output value. For most stages, output quality is determined by a compound event and is modeled by the product of event probabilities; exceptions are discussed in detail. Defects A structured treatment of defects is employed. First, a list of mutually exclusive and collectively exhaustive types of defects {k I k = 1 . . . . . K'} must be prepared. 7 Next, each product must be analyzed to identify the set of components, Nik, that are vulnerable to defect type k. Membership in set Ng k is restricted to ensure homogeneity of constituents; any variation in process, test, rework, or defect
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Processes Each process {m I m -- 1 . . . . . M'} (e.g., component preparation, pre-assembly, assembly, and post-assembly operations) may introduce a set of defect types, 0 m, but it cannot detect or repair defects. It is assumed that each defect is introduced independently of others. The capability of a process is defined by r,m, the probability that process m does not introduce a defect of type k.
component; in fact, it may introduce additional defects through handling and workmanship. The process capabilities of rework operations are described by probabilities u,t c, the P r [rework yields good component I defect k existed]; wt, tc, the P r [defect type k is introduced by c th rework cycle]; and x , t ~, the P r [rework yields good component I defect did not exist]. Should the data be available, these measures could be made more specific by adding a subscript i to indicate characteristics that relate to a particular product. After rework, a circuit card is retested, and may undergo a number of test and rework cycles c {c I c : 1 . . . . , Ct} until it is accepted. However, if it is rejected on cycle Ct at test t, the circuit card is typically treated as an exception, since further attempts using routine procedures would be futile. Exceptions are usually reworked by a skilled specialist to avoid the cost of scrapping. After in-circuit and functional tests, circuit cards progress through additional processes (e.g., storage, handling, system assembly, and burn-in), then system-level test stages, which usually return rejected cards to functional test for diagnosis and fault isolation. In addition, in-service conditions may be modeled as processes that introduce defects, followed by tests that return rejected cards, creating additional test and rework cycles.
Tests A test stage may entail either visual inspection or electronic test, but it cannot introduce or rework defects. Tests may be performed at the component or card (in-process, in-circuit, function, system, and in-warrantee) levels. To distinguish these levels, tests at the component level (e.g., test Tj for component j {j I j = 1 . . . . . J'}) are indexed by 1 {l I 1 = 1 . . . . . L'}; and those at the card level (e.g., test Ti) are indexed by t {t I t = 1 . . . . . T'}. Each test is capable of detecting a certain set of defects, Dt or Dt, including those that are of primary focus as well as others that might be identified incidentally (i.e., as by-products), but cannot introduce or repair defects. Tests are fallible and may identify a defect that does not exist or fail to identify one that does exist. The probabilities of these errors, -eikntc and fi*ntc, respectively, specify test effectiveness. The models described in this paper are based upon the assumption that 100% testing is accomplished at each test. This assumption appears to be realistic in an automated environment in which components are routinely inspected individually, every insertion is checked by assembly equipment, and each circuit card is subjected to a final test. Models could be adapted to reflect sampling plans, should they be of interest in a particular application. Again, this paper discusses a systematic approach for analysis and demonstrates it in deriving models for one scenario of operation; the specific models themselves may not represent all systems.
Sets Relationships among various sets may be clarified by noting that each test may detect a certain set of defects, D t, each process may introduce a set of defects, 0 m, and each type of defect may be introduced by a set of processes, M k. A circuit card is vulnerable to a set of defects, U'i, the union of all sets of defects, Uin, to which its N ' i constituent components are vulnerable.
Modeling Approach Representative models of stages are described in this section. The motivation for modeling all types of stages is to provide a unified description of product quality and test and rework operations.
Rework If a component is rejected by a component-level test, it is eliminated (e.g., by scrapping it). However, defects identified by tests at the card level may be corrected by a rework stage that repairs or replaces rejected components. Rework is an imperfect procedure that may or may not yield a good
Pooling The quality history of a type j component starts with the set of vendors, Vj, that supply it. Each
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vendor, v {v I v = 1 . . . . . V'}, is a process that supplies a portion, O/v, of the requirements for part type j. A component delivered by vendor v has the probability 13"jkv of being good relative to defect k~8~. The term pooling describes a situation in which all components of type j are intermingled so that the probability that a randomly selected component was supplied by vendor v is o/,. If components from the set of vendors are pooled upon delivery Pr [component good on input to pooling[ = P/k~ = Pr [component good as output from vendor] = [3"jk" for all j,k and v. The probability that a randomly selected, pooled component of type j is good relative to defect k is
[type j component is good relative to defect type k at test 1]), or (2) the component is bad relative to defect type k but is incorrectly identified as good (with probability Yjt,l fit,l):
djl = "Yjkl ejkl -]- Vjkl fjkl"
Subscript i is not used, since the components have not yet been assigned to a circuit card. "Yjkl must be set equal to the output probability of the preceding stage, for example, P"jk if pooling precedes this test, or [3"jkv if components are not pooled. Figure 1 depicts the two acceptance conditions for test l I (only subscript k = 1 is shown for clarity). A component accepted by test l = 1 is good with probability gl and defective with probability b 1. A second test l = 2, which checks for defect type k = 2, may be modeled again using Equation (3). Four acceptance conditions result (g~ g2, gl b2, bl g2, and b I b2) a s indicated by Figure 1. A set of L* tests is represented by a series of L* stages, each modeled by Equation (3) and each providing the input quality to the subsequent stage. 2L* states of quality result upon completion of the L* tests. Component quality may thus be defined by a vector in which element k gives the probability that the component is good relative to defect type k. The probability that a component of typej is good relative to defect k given that it is accepted at test l, Y'jkt, may be determined by dividing the probability that a good component is accepted (Yjkl ejkl) by the probability of acceptance
P'~ik ---- ~v, Vj Pjkv O/v ---- ~'v~Vj ~"jkv Ojv; for each ke8 v-
(1)
P"jk is, thus, a weighted average of all vendorsupplied qualities. The quality of a pooled component of type j is defined by the vector with elements {P"jk I k~8,} that relate to the set of defects 8~ that may be introduced by vendor v. The probability that a component of type j is good with respect to all defects introduced by vendors is:
Pr [pooled component is good relative to all keSv] = IIk,~v i f ) k ,
(3)
(2)
and the number of good components in a pool of size P has the binomial distribution with mean E [number of good components] = P Ilk~v p"jt,.
Y'jkt = Y/k, e/k,/ d/,.
If components are not pooled, the subscript v must be retained so that the quality of a component is given by 13"jkv. The capability of tracking vendor-supplied materials may be important, for example, in systems that produce military hardware, since they are usually required to record the source of all materials assembled into a product.
(4)
Similarly, the conditional probability that an accepted component is not good is: ~ )kl = ~ / k l & l / djl"
(5)
The number of components of type j that will be accepted from a lot of size P has the binomial distribution, so
Component-Level Tests
E [number components accepted by test l] = P d/1.
Component-level tests, I~Tj, screen defectives. It is assumed that each test checks for a single defect type (IDtl = 1), so the probability, d/t, that a component will be accepted by test l is the union of compound events: (1) the component is good relative to defect type k and is correctly identified as such (with probability Yjkt e/~a where Yjkl is the Pr
(6)
Given that it is accepted at component-level tests, the probability
Pr [a type j component is good relative to all defects checked by component-level test Tj I accepted] = Hl~rj Hk~o, Y~kr
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The set of assembly processes Zi is required to assemble circuit card type i. Process m~Zi may introduce defects keO,,, through faulty operations or by damaging components. For example, leads may be tarnished in storage, incorrect components may be kitted, and an insertion machine may insert the wrong component or fail to insert one. It is assumed that processes do not detect defects and are not affected by them. A component input to process m is good with probability Pikm,,, and it is good upon output if the process does not introduce a defect:
REJECT
ACCEPT
REJECT
ACCEPT
D"ikmn :
Pikmn rkm"
(8)
Equation (8) models each process in the routing of product i, me Zi, for each component n and defect keOm; several additional measures of quality are summarized in the following. The probability that a component is good relative to an assembly defect is given by Equation (8); the Pr [bad relative to insertion defect k] : Pikmn Ykm
REJECT
Pr [bad relative to handling defect k] = 1-pikm n II,n~r ' rl,m
ACCEPT
(10)
in which Equation (9) describes the incidence of a defect that may be introduced at only one process, while Equation (10) gives the likelihood of one that may be introduced by a number of processes. Since a single component may be vulnerable to more than one defect type (i.e., I U~,, I>- 1), its quality upon output at process m is described by a vector {p' 'it,m,,
Figure 1 Two Independent Tests in Series at the Component Level
If components are pooled after component-level test l rather than before, ~l' 'jkl :
(9)
Circuit Card Quality The probability that a circuit card is good relative to defect k as it leaves process m is the probability that no constituent components are bad. Components neNik are vulnerable to defect type k; each has the probability P"ikmn of being good relative to defect k so circuit card quality (i.e., the probability that the card is free of defects of type k upon output from process m, H"ik) is
~v~Vj Pjkv ejkt Ojv,
a weighted average over all suppliers of the probability that a vendor supplies a good component and it is accepted by the test. Processes Component Quality An inventoried component is allocated to assemble a specific product, for example, as it is placed in the kit of components required to assemble the product. After components are assigned to cards, quality is best analyzed by treating the N'~ individual components assigned to a particular card.
n"ik
:
[IneNjk P"ikmn"
(11)
The probability that the card is defect-free is the product of the probabilities that it is good relative to each type of defect: Pr [card has no defects] = IIk~v, H"ik.
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Of the INikl components assembled at process m (which may introduce defect type k), the number of components with defect type k is a random variable with the binomial distribution, so
Circuit Card Test and R e w o r k
The probability of accepting all components in the set Nik on cycle c {c I c = 1 . . . . . Ct} is IN,d
l~neJV ik aikntc = aikntc'
E [number of components with no defect type k] = rkm I Nik I E [number of components with defect type k] = rkm I N/kl.
and the probability of accepting the circuit card on test cycle c, Air~, is
Aitc
(13)
:
tN,klc iik~o, ii,,~v,, aikntcO aiknt
E [number of components reworked on cycle c] = ~k~o, ~iikntc INikl.
(15)
(16)
The distribution of the number of rejected components is important, since it describes the workload placed on rework operations. The probability that a card is rejected Ct times and, thus, handled as an exception is
Component Test~Rework
Entering the first cycle of test t (c = 1) component quality is denoted g~knt~ for keD t. A component accepted on the c th cycle may be good and correctly identified as such, or bad and incorrectly accepted. The probability that a component will be accepted is gikntc eikntc + g ikntcfikntc"
likeD,
The card is rejected with probability ~itc. The number of rejected components in the set Nik has the binomial distribution with expected value dik,,tc INit,I, and the expected number of components reworked for all defect types keD t is
Test and Rework Operations Assembled circuit cards are subjected to a series of in-circuit and function tests, t¢T i. If a circuit card is rejected by test t, it must be reworked and subsequently retested; after C t rejections, it is assumed that it will be handled as an exception.
aikntc :
:
Sit :
(17)
l-Ict l -Aitc.
S i m i l a r l y , Bitc, for c : 1 . . . . . C t, gives the Pr [card is accepted by test t on the Cth cycle] as
(14)
Conditioned upon acceptance, the quality of a component is:
r
Pr [component is good relative to defect k I accepted on cycle c] = gikntc eikntc / aikntc"
Bit c
Tests for multiple defects (IO t I > 1) may be modeled either by defining g to reflect all k¢D t or by using Equation (14) for each k¢D t and basing acceptance on all defects:
:
Ait c
for c = 1
J
c-! 1 7"itc' f o r 1. Aitc He'=
(18) c -- 2 . . . . . C,
The E [number of test and rework cycles for a card] = E c - i c Bit c q- C t Sit
Pr [accept component relative to all kcDt] =
(19)
likeD, aikntc.
Rework Rework may entail a variety of procedures since some defects are reparable and others require component replacement.
One test and rework cycle (c -- 1) for a component is depicted in Figure 2 (only subscript c is shown for clarity). A rejected c o m p o n e n t is reworked (R~); if it is bad, the rework operation would make it good again with probability u 1 (1) or fail to do so with probability ~l (2). If the component is good, rework could introduce a defect with probability w~ (3) or yield a good component with probability wz (4). These outcomes, shown in Figure 2, define component quality as it enters the next test cycle.
Repair
Reparable defects include solder bridging and misoriented components. It is assumed that defects are mutually independent and that they are repaired one at a time. Figure 3 depicts a test and rework cycle relative to a card (only subscript c = 1 is shown for clarity).
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1
ot ~
gl~ux
C 5]
g~Exw~
REJECT
gl~l~/l BOARD REJECTED
ACCEI~I" glel
'~(~)
:
(20)
Qik~tc = Pr [circuit card is rejected due to defects identified on components other than n] 1-Air c / IIkeu,jqD, aiknt c
g,g,
r,.
g,f,
4.s. g,e,x,w,
Replacement Equation (20) must be modified if rework entails replacement rather than repair. Suppose component n is to be replaced on circuit card i. The replacement component must be of type j = Jin, and its quality (i.e., the probability that the replacement component is good relative to defect type K~Uin, "q')k) must be described as a function of the componentlevel tests and intervening handling processes that it experiences. With replacement, the probability that a component is good as it begins the (c + 1)st cycle is determined by three compound events: (1) the component was bad, correctly rejected, replaced with a good one and a defect is not introduced during rework; (2) the component was good, incorrectly rejected, replaced with a good one, and a defect is not introduced during rework; or (3) the component was good, correctly accepted, and not damaged during the rework of rejected components
in which the probabilities of compound events (1)-(3) are listed in order. Tests may induce interdependencies, since components that are not the cause of a circuit card being rejected still must travel with the rejected card through rework operations. This possibility may be expressed as:
:
g,~,
4.
An effective rework operation should improve identified defects, but it may also introduce additional defects (e.g., due to overloading, soldering, and thermal damage) or unmask 7 others that might be detected upon retesting. Actual test and rework operations may induce inter-dependencies among components (e.g. See Equation (21)). Such a dependency may be a function of the circuitry on a particular card and is beyond the scope of this paper, which invokes the assumption that test and rework operations are independent and lead to certain inherent approximations. In any event, gikntc is not necessarily constant for all cycles.
g"ikntc gikntc fikntc Uktc Wktc -~- gikntc ~ikntc Yktc Wktc -~- gikntc eikntc Qikntc Wktc
~,r,
a.
Test/Rework Cycle for a Circuit Card
Cycle for a Component
The probability that a component is good as it emerges from the c th repair [beginning the (c + 1)st cycle] is determined by three compound events: (1) a bad component is rejected, repaired correctly and a defect is not introduced during rework (path 6-7 in Figure 3); (2) a good component is rejected, repaired correctly and a defect is not introduced during rework (path 4-8 in Figure 3); or (3) a good component is accepted at test, must cycle through rework because other component(s) are rejected, and a defect is not introduced during rework (path 3-9 in Figure 3): giknt,c + 1 :
g,¢,
Figure 3
Figure 2 Test/Rework
t. 2.
(21)
in which the defect types in set Ui. N D t are those checked at test t to which component n is vulnerable.
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giknt, c + 1 ~--- -gikntc fikntc ~ j k Wktc qgikntc ~ikntc "q j k Wktc q- gikntc eikntc Qikntc W--ktc
System variety and scale are limited in this example only to focus on underlying relationships. Test cases were defined by the parameters used to describe vendor, process, test, and rework capabilities. To facilitate understanding of results, parameters (r = e = f = u = w = x for all ikntc) were set equal to 0.9, 0.99, 0.9999 and 0.999999, respectively, to define the four test cases. These quality measures reflect a range of capabilities from relatively poor to relatively good (one part per million error). C t was set to 5 and the ultimate disposition of exceptions was not considered. This data defines the two vendors to be identical with respect to quality and also makes repair and replacement types of rework equivalent, since u~tc qq'' jk. Measures of quality are displayed in Table 3; the equation used to calculate each is noted. Rejected components are scrapped at componentlevel tests l = 1 and l = 2. The measure E [lot size after test l] indicates the expected number of components that are accepted at test I and quantifies the reject rate at that test. Clearly, tests should be ordered, if possible, with the one expected to reject the largest number of components first, so that effort is not expended to test a component for several defects before it is likely to be rejected for another cause at test 1. This analysis indicates the damning effects of multiple components on a circuit card. Even though a given component is of high quality, the likelihood that the card will be defect free is relatively small. If a card is vulnerable to a total of K defects and its quality must be within e of 1.0, then the (assumed equal) probability, t~, of being good relative to each defect must satisfy
(22)
in which the probabilities of the compound events (1)-(3) are given in order. R e p a i r or R e p l a c e m e n t
Some defects may be reworked either by repair or replacement. Data on actual operations could be used to estimate the relative frequencies of these two procedures: pN = P r [type j component is replaced] pF = P r [type j component is repaired].
Component quality entering the (c + 1)st test cycle is then giknt, c+ l -- p N giknt, c+ l(22) + p p giknt, c + 1 (20)
in which the arguments indicate defining Equations (20) and (22).
Analysis of Test and Rework Operations This section is intended to foster insight into the effects that test and rework operations have on material flow in circuit card assembly.
Numerical Example An example composed of hypothetical, representative data is discussed in this subsection. J' --- 2 types of components are considered; each is supplied by two vendors (I V j I = 2 and oj, = 0.5). The system is composed of five processes (M' = 5): 2 vendors, 2 assembly machines, and 1 soldering process. Each component is vulnerable to five (I Ui, I = 5) types of defects: mechanical and electrical defects "as received," assembly fault at one of the two machines, damage by handling, and faulty soldering. Vendors supply components in lots of size P = 1000, and two component-level tests check for the "as received" defects. Subsequently, a circuit card is assembled using 100 of each component type. This scenario reflects the features found in actual systems; a circuit card may, in fact, contain two types of components that progress through five stages: vendor preparation, pooling, component-level test, assembly, and soldering.
1.0--e <- qjx < 1.0 and is given by --- + - < I . 0
.
As K increases, the effect of multiple components can be ameliorated only by requiring each component to be of very high quality, t~. Tests t = 3, 4, and 5, performed after assembly, check for defect types k = 3, 4, and 5, respectively. Components rejected at test 4 require replacement, while those rejected at tests 3 and 5 can be repaired. Since Uktc = ~q"j k is assumed, all tests give the same results, so only one is described in Table 3.
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Table 3
Due to the effect of multiple components, there is a relatively high probability of rejecting a circuit card, but the expected number of components that require rework is small. Consequently, many components are exposed to handling defects while a few are reworked. With poor quality capabilities (Case 1), it is highly likely that a circuit card will be treated as an exception after five test cycles. Component quality is actually degraded by poor workmanship at rework and the expected number of components reworked increases with c. In this case, the probability of rejecting a circuit card and the amount of rework required increases at every test and rework cycle. Clearly, this result could lead to bottlenecks in work flow that would not be predicted by the usual assumptions discussed in the introduction. With good quality capabilities (Case 4), a circuit card will be accepted, likely on an early cycle. Test fallibility may, in fact, lead to more rejected components than will component quality itself if a good component is rejected with a greater likelihood (gi*ntc eikntc) than that of accepting a bad component (git,,tc Jit,,,tc). Rework may either maintain or improve quality as c increases. In high quality cases, good components that are falsely rejected may constitute the primary workload on a rework station. If replacement components have relatively poor quality or if defects are likely to be introduced by rework, quality might actually be degraded as c increases. On the other hand, test fallibility may introduce another paradox: the actual quality of a circuit card may be good if it is accepted after a number of cycles, but may be relatively poor if it is accepted on an early cycle, since bad components may be accepted erroneously on the first test cycle. This example demonstrates that test and rework operations must be analyzed carefully to correctly assess their impact on material flow. Bottlenecks that cannot be predicted by simple, pragmatic analysis may develop due to process capabilities as demonstrated in this example.
Test Results + Deseript Ion
Symbol
VENDORS Ptlgond w/r kl Prlgcod wit all k] INCOMING TESTS Prlaccept /=11 Pr[good hccept]
I~rrorlnan~ Mcuures Case #3 Case #3
Case #4
I 2
09 081
0.99 0.9801
0.9999 0.9998
0.999999 0.999998
dj~
3 4
0.82 0.987805
0.9802 0.999898
0.9998 1,0
0,999998 1,0
6 6 7
820.0 672.4 0975759
980.2 960.792 0,999796
9998 999.6 1.0
999.998 999.996 1.0
8 lI 12 13
0,9 0.000027 1.8E-14 10,0
0.99 0366032 0490408 10
0,9999 099049 0.97174 0.01
0.999999 0.9999 0.9997 O.t3001
18 18 18 18 18 18 19
0.2E-08 0.19E-09 0 13E-09 0.12E-09 0.12E-09 1.0 5.0
0.135354 0.113631 0.986406 0.856839 0,7443 0.492261 3.82337
0.980199 0.019409 0.000384 0.76E-05 O. 15E-06 0.30E-08 1.0202
0.9998 0.11001)99 0 4E~07 08E-11 0.2E-14 0.3E-18 1.0002
20 20 20 20 20 16 16 16 16 16
0.9 08748 0870718 0.870056 0.869949 18,0 20.016 20,M26 20.3955 20.4041
0.99 0.989705 0.989699 0.989699 0.989699 1.98 2.00891 200948 Z00949 2,00949
0.9999 0.9999 0.9999 0,9999 0.9999 0,019999 0.020001 0.020~1 0.020001 0.0200O1
0.999999 0.999999 0.999999 0.999999 0.999999 0.0002 0.0002 0.0002 0.0002 0.0GO2
Y'jk~
ASSEMBLY PROCESSES pr[good w/r k] p"Lj~ Pr[CC good w/r kl Ha Pt~CC good w/r all kJ E[# components with kl
Pr[exception]
Case #1 9"j~
E[Lot size after/=11 E[Lot size after/=21 prlgood w/r all kl
TEST CYCLES Pr[accept ]c=li Pr[accept [c=2l Prlaccept ~c=31 Pr[accept ~c=41 Pr~accepc~-51
ElI
B,~ Bia Bio B,,( B,~ S,~
E[# cycles]
REWORK Pr[good k= I ] Pr[good 1c=21 Prigood [c=-31
g~ g,~z 8~ Pdgood ~c=41 g~ Pr[good ]c=51 ga~o El# comp rcworked on c=l] El# comp reworked on c=2) E[# comp n~workedon c=31 El# comp reworked on C--41 El# comp reworked on c=5]
LEGEND CC indicates "circuit card" w/r indicates "with respect to" + To 6 decimal place accuracy unless given in scientific notation
operations (column 7) is linear in each parameter. The last column tallies the total number of operations in the large-scale example defined at the bottom of the table. At a speed of 100,000 operations/second, a runtime of only 2.3 minutes would be required to model this hypothetical large-scale system.
Discussion The cost associated with test and rework cycles are, of course, a matter of primary concern to the manager and may be described by accumulating the costs of each cycle using the notation
T/g
~---
total cost of test and rework at test t cost of queueing at rework on cycle c
Computational Analysis Computational requirements to implement the model discussed in this paper are described in T a b l e 4, which itemizes the number of arithmetic operations required by each equation. The total number of
176
c ./c =
cost of queueing at test t on cycle c
cL=
rework cost for the c th cycle at test t
c,'.,c =
cost of testing on the c th cycle at test t
C~t
cost of handling a card as an exception on cycle C v
=
Journal of Manufacturing Systems V o l u m e l I/No. 3
Table 4
This paper describes an approach for modeling test and rework operations in circuit card assembly, applies the approach to derive models that are representative of typical systems, and uses a numerical example to foster insight into the effects of test and rework operations on material flow. The example demonstrates that it is possible to quantify the effects of component quality, process capability, test fallibility, replacement parts, and imperfect rework on material flow at test and rework operations. For example, in an environment with high quality parts (e.g., with one defect per million parts), test fallibility may lead to more rejects than will bad components. Furthermore, poor workmanship at rework may degrade the quality of a circuit card, requiring more rework at each cycle. Thus, in some cases, a good card could be falsely rejected initially and its quality could be degraded by successive rework operations. It is important to balance the quality capabilities of the various elements in the quality control plan. For instance, only incremental gains may be achieved by improving component quality without also improving test fallibility and rework workmanship. Each of these elements has an important influence on material flow and upon the creation of bottlenecks at test and rework operations. Industry typically assigns the cause of a rejection to one of a few causes that lump together defects that might actually be attributed to a variety of causes. This practice is expedient, but it masks the real reasons for problems and precludes appropriate process corrections. The modeling approach presented in this paper, as well as more sophisticated models that might be developed through future research to incorporate dependencies between circuitry and function, should help to understand the process and the product so that necessary process corrections can be identified and implemented more readily.
ComputationalR e q u i r e m e n t s Step
Eq # Div
Exp
Add
Mult
# Ops
xl04
]Vj [-1
IVj I
J'(2 Iv, l- l)
0.5
t
3
5J' tr, I
1
r~l ~,1
13 6.0
2
3 I' C, tY,[
0.1
~Dt I
l'C~ ~r,[ ( b , ~ b
2.7
10 + ]U= c~ D, I
I ' c , ~I',1(14 + IU=nDO
3.I
Tit, may be expressed as = + C,'.] + Ci, S,t + c,c=2 Aitc,] [c~tr~'-t + Crt:'-, + C~ttc' + C,t,~']•
(23)
Pooling I Com!aonent Test 3,4 Process
8
Test
15
Cycle c
16
Rework
22
1
I 1 1
3
lo~l
REPRESENTATIVE PARAMETER VALUES FOR A LARGE-SCALE APPLICATION V~riable Number I' 3000 J' 50OOO 5
I
40
~. I
10
~71
5
,
3
c,
3
tD, I
loo
lug-o, I i00
LEGEND Eq# Div Exp Add Muir #Ops # l06
Equation number Number of divisions Number of exponenfiations Number of addition operations Number of multiplication operations Number of aritbematic Operations Number of operations in numerical example (xl06)
Total cost,
Tit includes the cost of queueing and testing on the first cycle, the expected cost of being handled as an exception, and the expected cost for other cycles, counting rework (cycle c'-l) and test (cycle c') in the last term in Equation (23). The product term in the brackets defines the probability that c test cycles will be incurred. The costs of in-process inventories, C~tr and C~tt~,may be estimated by inputting the reject probabilities and rework workload described by the model into another model, z6 which would estimate the queueing that would result in the flow of materials due to the quality control plan. The total cost model in Equation (23) gives a detailed way of relating costs to each element in the quality control plan. In comparison, Fu et al. 9 estimate costs using only the probability that a circuit card is accepted, scrapped, or reworked. Suri, Sanders, and Mody z° describe the importance of evaluating all cost components to overall competitiveness.
Acknowledgements This material is based on work supported by the National Science Foundation under grant numbers DMC-8500898 and DDM-9114396.
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Journal of Manufacturing Systems Volume I I/No. 3
References
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Author's Biography Dr. Wilbert Wilhelm is a Professor in the Industrial Engineering Department of Texas A&M University. He received his BS in mechanical engineering from West Virginia University and his MS and PhD degrees from the Department of Industrial Engineering and Operations Research at Virginia Polytechnic Institute. He is a registered Professional Engineer and a member of ORSA, liE, and SME. He is currently the Director-Elect of the ORSA Special Interest Group on Manufacturing Management (SIGMA), a Co-Editor of the Department of Planning/Scheduling/Control for liE Transactions, and the Editor of the special issue on lie Transactions on scheduling and logistics, and a member of CICMHE.
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