MOS into MSI and LSI components

Microelectronics and Reliability, Vol.15, pp. 85 to 92. Pergamon Press, 1976. Printed in Great Britain

The Evolution of COS/MOS into MSI and LSI Components by R Tarrant Although the threshold voltage of n-channel transistors can easily be reduced to zero, the threshold voltage of p-channel transistors can only be substantially decreased by use of a gate material, such as p-type silicon instead of the conventional aluminlum gate.

History of COSIMOS Development The advent of IC MOS technology paved the way for the practical application of complementary techniques to digitat switching. The basic building block for MOS is the inverter pair, shown in Fig. 1. Development in this region in 1963 resulted in the bread-boarding of a COS/MOS flip-flop assembled from discrete inverters. Subsequently, this led to the development of the first COS/MOS IC in 1964, a three input N A N D / N O R gate.

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Well Implant (Fig. 3) processing does away with the need to expose silicon slices to dopant materials in a high temperature furnace. Instead, dopant materials are introduced into the silicon substrate by using a high energy ion beam which is magnetically focussed onto the slice in a vacuum chamber. This process is used to enhance threshold voltage control and to improve packing density.

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RCA's announcement of the availability of commercial COS/MOS circuits in 1968, resulted in 15 standard parts and the emergence of the CD4000 series. The plastic package versions introduced by RCA in 1970 were o great advance towards lower COS/MOS device costs and made possible the application of C-MOS in such important market areas as industrial control, instrumentat ion, telecommunications and computers.

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By early 1971 significant advances in COS/MOS processing had been achieved. These developments were particularly directed towards the reduction of MOS thresholds by lowering surface state densities and by optimising other important parameters, such as channel oxide thickness and substrate concentration. The success of these efforts made possible the large scale production of lower threshold CMOS on an economical basis.

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Silicon-on-Sapphire (SOS) Sillcon-on-Sapphire (Fig. 4) processing is employed to remove much of the parasitic capacitance inherent in a Planar Monolithic circuit. This is achieved by allowing each discrete MOS device to be fabricated within an island of silicon which is chemically bonded to a substrate. Sapphire is used because it is stable, inert, relatively cheap and offers a good compromise of electrical and thermal characteristics.

Silicon Gate Silicon gate complementary MOS processing (Fig. 2) has been developed specifically to meet the lower threshold voltage ( 1.0 - 1.5V) requirements necessary for certain market areas, e.g. wrist-watch market.

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CD4OIO1B - 9 Bit Parity Generator and Checker (Fig. 6) This product utilizes exclusive OR gates to generate even or odd parity at theoutputs from the data inputs. Bath outputs will be low if the inhibit input is activated. This part will find general use for generating or decoding error check bits in digital communications systems.

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RCA's initial SOS products will be introduced in three market areas: 1. 2. 3.

Time pieces (i.e. watch and clock) Memories (TA6780) General purpose logic.

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A total of 9 products including one 1K RAM will be announced during 1975.

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CD4OIO2B / CD4OIO3B - Presettable 8 Bit BCD/Binary Down Counter (Fig. 7) Presetting of the 8 data inputs may be accomplished

With improved processing capabilities the CD4000 range of COS/MOS products has been extended to 111 different parts. The following new products are among the latest to be made available utilizing the well implant process, as previously defined:

synchronously or asynchronously by activotlng one of two separate control inputs. A reset input is also provided for maximum ease of use. Acarry output, which also functions as a zero stage detector allows devices to be cascaded in either parallel or ripple clocking modes.

CD4OIOOB - 32 Bit Left/Right Shift Register (Fig. 5)

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A single clock input (pin 3) and a single shift left/rlght control llne (pin 13) will transfer data serially throughout 32 stages of static shift register. This is the longest CMOS shift register available which can both inernal ly shift left as well as shift right, for either shift left or shift right dedicated inputs and outputs are available. Additional controls include a clock inhibit (pin 2) and a recirculate (pin 9). Suitable application areas are data processing, arithmetic operations and digital communications.

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Evolution of COS/MOS into MSI and LSI Components Mode select pins are available to select left or right shift and parallel or serial inputs. Data outputs can be switched to a high impedance state (Three state) for bus orientated applications.

87

This part can be used for simple logic inversion in a system, for pulse shaping or for increasing noise rejections. VDO

Suitable application areas are serial to parallel data conversion, data processing and digital communications. MODE SELECT

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These buffers are designed to sink high currents for significant load-driving interfaces. Their configuration is similar to the TTL 'open-collector' circuits in that no p-device is included on the outputs, hence they have no sourcing capability. Produced in a plastic 8 pin minidip package the CD40/07B can be used for level shifting and power interfacing.

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This is a data handling device suitable for register files and small scratch-pad memories.

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CD4010OB - Hex Schmitt Trigger I nverters

(Fig. I0) Six inverters, each exhibiting hysteresis, in a package with the same pln-outs as the CD4069B.

CD40181B - 4 Bit Arithmetic Logic Units

(Fig. 13) A COS/MOS implementation of the popular 74181 TTL part, the CD40181B will find use as 4-bit building blocks in arithmetic units. Sixteen arlthmetic operations including add, subtract, shift and compare are available,

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This unit can be used in areas that require absolute or difference counting and timing.

as well as 16 possible logic functions of two Boolean variables without the use of external circuitry. When used in conjunction with the CD40182B look-ahead carry, high speed arithmetic operations can be performed. Ripple carry input and output pins are available if high speed is not important.

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CD40182B - Look-Ahead Carry Block (Fig. 14) Used in conjunction with the CD40181B to provide carry, generate carry and propagate-carry functions for high speed arithmetic operations. Units are cascadable to build systems of n-bits.

CD40192B - Synchronous 4 Bit BCD Up/Down Counter (Fig. 15) A COS/MOS implementation of the 74192 TTL part, the CD40192B is provided with two clock inputs, one for incrementing and one for decrementing. The counter has 4 asynchronously presettable inputs, with preset enable and reset, to zero, input. Outputs include the 4 counter

CD40194B - 4 Bit Left/Right Shift Register (Fig. 16) Equivalent to the TTL part 74194 and is simiIar to the CD40104B except the CD40194B does not have 3 state outputs. A reset input pin is available. Applications areas include data processing arithmetic operations, dlgltal communications, code conversions and serial-to-parallel data conversion.

CD4508B - Dual 4 Bit Latch (Fig. 17) These COS/MOS Latches transfer data through from input to output when the strobe signal is high and latch present data when the strobe goes low. Each 4-blt latch has independent Reset and three state control. These units will be suitable for bus organized digital systems for interfacing and data storage.

Evolution of COS/MOS into MSI and LSI Components

emerge with the abiJity to provide complete stored program computers at a fraction of current mlni-computer costs. Consumer, educational, small business and communications markets are prime targets for truly lowcost microcomputer based products. The architecture described here was developed to satisfy the requirements of these potential new markets. Practical, stand alone systems (including input/output device control and memory) requiring as few as 6 LSI chips are now feasible. Such systems have been breaclboarded and programmed. Based on this experience, the microcomputer described satisfies the requirements of a much wider range of applications than originally intended. It is also simpler than most existing microcomputers.

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Since LSI improvements are permitting ever larger numbers of devices per chip, there are definite long term advantages in minimizing microcomputer complexity. If the microcomputer is prevented from growing in complexity as the device per chip ratio improves, more of the system can be pulled back into a single chip.

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The LSI Component of the Future The COSMACMicroprocessor. Summary For 20 years computer hardware has become increasingly complex, languages more devious, and operating systems less efficient. Now, microcomputers afford some of us the opportunity to return to simpler systems. Simple, LSI microcomputers could open up vast new markets. A number of these devices are available in the market place today for use in both special purpose and general purpose applications. COSMAC, a COS/MOS LSI microprocessor designed for use as a general purpose computing element has been developed by the RCA Corporation.

An eight bit parallel register oriented architecture was chosen for COS/MAC as being best suited to the requirements of optimlslng performance, memory usage, and processor complexity. An eight bit machine provides sufficient width to effectively manipulate the standard code and data units of a majority of the communications and information processing fields, while providing a significant performance advantage over bit serial and four bit machines. A register oriented structure was chosen to provide convenience in implementing programs utilising interpretive subroutine coding techniques, for macroprogramming, as well as the ability to efficiently manipulate data when programming in the machine language and to effectively implement foreground/background processing using the processor's interrupt facility. The block diagram of figure 18 shows the general architecture of the microprocessor. The register matrix, R, is an array of sixteen 16 bit registers (essentially a 16 x 16 bit RAM) which may be addressed by the P, X or N registers. The I, P, X and N registers are all four bits in width. Me,

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This paper describes a simpllfled microcomputer architecture that offers maximum flexibility at minimum cost. Experience with breadboard versions of this architecture have verified its usefulness over a wide range of potential applications.

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Overview The basis of the LSI (Large Scale Integration) revolution is the ability to provide complex electronics at greatly reduced prices. Major cost reduction opens up entirely new markets and is as significant a development as the invention of the vacuum tube or transistor. The four function electronic calculator represents the first wave of the revolution. Further new markets will

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COSMAC Internal Architecture.

The I and N registers are used to hold the instruction fetched from main memory: the contents of the I register determine the generic instruction type to be executed and,

90

R. TARRANT

depending upon the contents of the I register, the contents of the N register are used to select one of the matrix registers, to control the Input/Output devices, or to provide further definition of the instruction to be executed, The contents of the P register determine which of the 16 matrix registers is being used as the current program counter, The X register is used to address the Register Matrix to fetch the address of memory operands for certain memory reference instructions. The T register is an eight bit register used to store the contents of the P and X registers whenever a program state change occurs in response to an interrupt. The A register is a 16 bit register used to temporarily hold the date fetched from the Register Matrix. A 16 bit Increment/Decrement network is used to update information fetched from the Register Matrix. One eight bit multiplexer is used to gate the contents of the A register to the eight bit memory address bus and a second multiplexer is used to gate the contents of the A register to the eight bit, bi-dlrectional data bus. The D register is an eight bit accumulator with associated zero decode and carry, or link, indicator which may be interrogated with the branch instruction. The ALU is an eight bit parallel arithmetic and logic unit capable of performing binary add, and substract, logical AND, OR, exclusive OR, and shift operations. One operand is contained in the D Register and the other is contained in memory and present on the data bus. The add, subtract, and shift operations may modify the carry indicator. As shown in Figure 18 the COSMAC Memory System shares the microprocessor I/© interface with the system peripheral devices. Although the memory address is sent to the memory system separately, data is transferred between the processor and memory via the I/O data bus.

COSMAC Instruction Set The following notation convention has been developed to describe the operation of" the COSMAC microprocessor. R(N) is used to denote the specific R register selected by the 4 bit hex digit contained in the N register. RO(N) denotes the low order 8 bits (byte) of the R register selected by N, and RI(N) denotes the high order byte. R(X) and R(P) is used to denote the matrix register specified by the X and P registers respectively. The contents of a selected R register (2 bytes) can be transferred to the A register and the 16 bits used to address an external memory byte via an 8 bit multiplexed memory address bus. The 16 bit word in A can be incremented or decremented by "1" and written back into a selected R register. Similarly, M will designate the contents of a memory location and therefore M(R ( X ) ) will designate the contents of the memory location addressed by the matrix register specified by the X register. All of the COSMAC instructions use the same fetch and execute cycle sequence. Each instruction requires two machine cycles. The first cycle causes an 8-bit instruction, as detailed in Fig. 19, to be fetched from external memory and placed in the I and N Registers. During this fetch cycle the four bit addi'ess contained in the P register is used to select the matri:~ register which has been designated as the current program counter. The contents of the selected matrix register are gated into the A register and are then sent to the memory system via the memory' address multiplexer. The con~ents of the A

register are incremented by one in the Increment/" Decrement network, and the result is stored in the matrix register specified by the P register. Finally, the contents of the addressed memory location are gated into the I and N registers via the eight bit bi-directional data bus. The most significant 4 bits of M(R ( P ) ) is placed in I and the least significant 4 bits are placed in N. This operation is written as M(R ( P ) ) - I, N. H S B

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The next machine cycle always causes the instruction contained in I and N to be executed. This Fixed 2 cycle, fetch-execute sequence simplifies control logic and permits program interruption or DMA cycle stealing to occur only between instructions. Since the operation code in I is limited to 4 bits only 16 instruction types need be decoded. The 16 possible operations specified by the Hex digit in I are listed below: Register Operations (1) Increment R(N)by 1 (2) Decrement R(N) by 1 (8) Transfer RO(N) to D (9) Transfer RI(N} to D (A) Transfer D to RO(N) (B) Transfer D to RI(N) (C) Transfer DO to ROO(N) Memory Operations (4) Load D from M(R ( N ) ) and increment R(N) (5) Store D in M(R ( N ) ) Misc. Operations (0) Idle (3) Branch (6) Input/output byte transfer (7) Interrupt control (D) Set P to value in N (E) Set X to value in N (F) ALU operations The first group of instructions permits selecting any 16-bit general purpose register (R) and incrementing or decrementing it. Upper or lower halves of selected R registers can be copied into D or set from D by these instructions. Operation "C" permits the least significant 4 bits of D to be set into the least significant 4 bit positions of any R register. This facilitates table lookup operations using 4 bit digit arguments. The two basic memory operations permit loading D from memory and storing D in memory. Used in combination with the register operations, selected general purpose registers can be set or stored. When N = P instruction 4 permits a byte to be retrieved directly from the program stream and placed in D. Since R (N) is the program counter, incrementing it maintains program counter integrity. The last group of operations provide a variety of functions The idle state can be entered via program or a next llne provided in the microprocessor interface; it waits for

Evolution of COS/MOS into MSI and LSI Components externally generated program interrupts or DMA requests. The branch instruction performs a test specified by the value in N. Test specified by N include zero in D, the states of four externally-activated flags, and the status of the ALU overflow register. Two instructions "D" and "E" permit the current digit in the P or X register to be modified. The "D" instruction provides the ability to change program counters at any point in a program. The E instruction permits changing the ALU operand or input/ output byte address printer. Instructlon"F" permits 8bTf ALU operations, "N" designating the specific ALU operation to be performed. One of the operands comprises the byte contained in D, the other operand comes from memory. The result of ALU operations always replaces the original byte in D. Instruction "6" permits byte transfers between memory and input/output devices via the common byte bus, the value of Nspeclf;esthedirection of the byte transfer. Instruction "7" with N equal to 1 stores the contents of T in the memory location specified by R(X). If N is 0, instruction "7" causes M(R ( X ) ) to be placed in P and X, R(X) ;s incremented and an Tnterrupt maskbit is set. This instruction provides a ':return after interrupt" function.

91

information transfer f'rom the processor memory to the I/O devices. The four external flag signals are provlded on the COSMAC Interface to enable the Control Electronic Units (CE's) to quickly transfer status information to the processor. These signals may be tested directly by the Test and Brand InstrucHon. A cycle stealing D Trect Access I/© facility was incorporated into the COSMAC processor to provide a high speed data path between the I/© devices and the processor. Two of the I/© signals, Input Request and Output Request, may be used by the I/© devices to ;nltiate a data transfer via th~s D~rect Access Channel. Only one device at a time may operate in the Direct Access Mode. A Program Load Facility using the Direct Access Channel is provided to enable users to enter programs into the C COSMAC memory. This facility provldesa simple, one step means for initially entering programs into the microprocessor system and eliminates the requirement for specialized R©MS ~n main memory to bootstrap user programs into the system.

I nput/0utput Interface

Chip Technology

One area of maior concern in any processing system is the computer's Input/Output interface. All of the peripheral devices in a system must use the interface when communicating with the processor and, therefore, the level of complexity and the efficiency of this interface hove a great effect on the overall cost and performance of any given system.

COSMAC is presently implemented on two chips employing RCA's standard COS/MOS technology. Both chips were laid out manually using standard cell techniques with computer-alded mask generation and checking. Onechip contains the Register Matrix, the Increment/Decrement network, the A register, and the A register multiplexers shown in Fig. 18; the second chip contains the remainder of the processor elements shown in Fig. 18. Thereg;ster Matrix chip is 236x 246 mils and the Arithmetic and Control chip is 256x 254 mils. Both chips contain approximately 3000 transistors. The COS/MOS technology was chosen because it provides many features which are advantageous in the design of inexpensive systems. The two chip processor is capable of operating with any supply voltage from5 to 12 volts; this wide operating voltage range enables direct connecHon to a variety of Ercult types. Inexpensive, unregulated power supplies can be used. The current drain on the power supply is negligible - each chip dissipates only about 100 microwatts.

[n order to extend the useful operating range of the COSMAC microprocessor, considerable emphasis was placed on its !nput/Output structure. The processor interface, physically composed of twenty-three signal lines (Fig. 20) [s capable of supporting devices operat[ng in polled, interrupt driven, and direct access modes. The processor is equipped with a set of very flexible Input/ Output [nstructlons, a built-in Direct Access I,/O copabillty, an I/O interrupt line, four External Timing Pulses, and an eight bit, bi-directional data bus.

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Eight of the sixteen sub instructions to the I/C, Instruct;on, "6", provide for information transfer from the I/O devTces to the processor memory; and, the other eight provide for

Although the COSMAC devices are new, future enhancements are already being developed. It is anticipated that the processor will soon be implemented on a single chip, and the implementation of a high speed version of COSMAC using a Silicon on Sapphire technology Ts presently under Tnvestigation.

Software and Software Support To ensure that the system is easy to program, a complete machine language assembler and simulator/debugger system has been created and made available on P,CA's corporate time-sharln9 service. This interactive assembler system provides the ability to easily program the microprocessor using the COSMAC machine language or the repertoire of macro Tnstructlon subroutines.

92

R. TARRANT

A standard Fortran version of the above mentioned assembler/simulator/debugger is being made availgble for batch processing as well as for use on any IBM Timesharing Operating System.

Hardware To facilitate the breadboarding of potential systems, a number of standard building block devices and control electronics units have been designed. Processor boards providing a full TTL interface and up to 24K bytes of memory have been implemented. I//O devices and their associated control electronics which have been built, include I/O typewriters, tape cassettes, floppy discs, dot matrix TV displays, video data terminals, keyboards, and various communications controllers for teletypewriter equipment and acoustice coupled data terminals.

Typical Systems Fig. 21 indicates o possible microcomputer-based calculator. ROM and RAM might be provided on one chip resulting i n a b a s l c 3 - c h i p c a l c u l a t o r . Functions could easily be added with ROM increments. This type of system could also provide a programmable calculator.

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COSMAC Word

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and system logic requirements. Hopefully, microcomputers of this class will accelerate the development of maior new markets. Currently high input/output device costs might be used as an argument against minimizing microcomputer cost. This is extremely short sighted. The availability of ten dollar microcomputer chips will, by itself, exert considerable pressure on the development of compatible low-cost I/'© and bulk storage devices. Even now there are many potential new products that demand minimum cost microcomputers of the type described. Because of its flexibility and potential for low-cost systems, RCA is currently developing a COS/MOS LSI version of this microcomputer. SOS versions ore also being developed for applications requiring higher instruction execution rates. Both implementationsare expected to find wide application in a variety of future products.

Fig. 21

Calculator System

Fig. 22 shows a Word Processing System employing the COSMAC processor and 4K bytes of main memory storage. The system uses inexpensive audio cassette tape recorders as mass storage units as well as for voice system operating instructions. The Shift Register CE is used as an intermediate storage device for on line data manipulation. The hexidecimal keyboard is used for entering initiaTization parameters into the system, and the I/O typewriter is used as a hard copy, manual input/output device. The system has been programmed to generate and edit form letters for storage on the tape drives as well as to process the form letters using a recorded mailing llst. Programs have been generated to process payroll information and to print pay-cheques. And, an inventory control and accounts receivable processing system has been investigated.

Conclusions Much current microcomputer development effort appears to be directed toward improved performance. There is, however, a need for simple, minimum Cost structures that will satisfy large volume applications which do not require mlni-computer performance levels. These microcomputers must also be organised to reduce total system cost. One such microcomputer architecture has been developed. It promises low cost together with minimum external memory