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The future of equipment development and semiconductor production
Materials Science and Engineering A302 (2001) 1 – 5 www.elsevier.com/locate/msea
The future of equipment development and semiconductor production Dan Maydan * Applied Materials, 3050 Bowers A6enue, Santa Clara, CA 95054, USA
Abstract The semiconductor industry has experienced exceptional double-digit growth over the past 25 years, fueled by strong demand in end-use markets such as computing, communications, consumer appliances, and industrial applications. Its future, however, depends on the ability of semiconductor manufacturers and equipment suppliers alike to lower cost while pushing the technological limits of lithography, materials science, and further the development of new manufacturing techniques like dual damascene. This paper will describe in detail those technology challenges that semiconductor manufacturers and equipment suppliers must overcome to extend Moore’s law into the next century, as well as highlight areas where equipment productivity has added, and can continue to add, tremendous value to the growth of the industry. Finally, a new paradigm called Process Module Systems will be put forth to address the increasingly complex manufacturing requirements as well as economic challenges that the industry, as a whole, faces. © 2001 Published by Elsevier Science B.V. Keywords: Equipment development; Semiconductor production; Process module systems
The invention of the integrated circuit in 1958 provided a fundamental building block for the Information Age, which by all measures, is expanding and thriving today. This era, though infant, is notable already for its dramatic growth and impact on our world. As shown in Fig. 1, it has surpassed in size the giant plastics industry, and is on a path of approaching the even larger steel sector. In a brief 25 years, the semiconductor industry has increased almost 40-fold, or 16% on average annually, fueled by demand for personal computers, communication devices, electronic consumer products, as well as many other electronic goods that consume millions and millions of chips each year. The wafer processing equipment industry, growing at the same annual rate as the semiconductor industry, has played a pivotal role in enabling this growth. Whether this historical growth rate continues into the new millennium depends on several factors. Demand for personal electronic products like computers or games could fall affecting both chip unit volume as well as production revenue. On the device side, the theoretical physical limits of semiconductors and lithography * Tel.: +1-408-9863176. E-mail address: [email protected] (D. Maydan).
capability are also potential showstoppers, especially at technologies below 0.10 mm. The integration portion of wafer processing at sub-0.10 mm presents a new set of challenges as well given the relative complexity of advanced devices. Furthermore, the sheer expense of new factories could result in fewer fabs built, affecting the overall rate of capital investment by semiconductor manufacturers. Taken alone or in combination, these factors have the potential to slow semiconductor growth. From a broader perspective, however, the opportunities in the Information Age appear enormous. The combination of an improving global macroeconomic environment as well as the world’s embrace and rapid implementation of the worldwide web are fueling strong demand for electronic products and services today. Of the world’s population, for example, the percentage of people with personal computers is just under 2%. Penetration of electronic devices on a personal level throughout the world is under-saturated and providing the basis for a prosperous future in the electronics sector. At the semiconductor level, meeting the increasing demand for electronic goods means producing more capability-enabling chips at lower and lower cost. To
0921-5093/01/$ - see front matter © 2001 Published by Elsevier Science B.V. PII: S0921-5093(00)01345-9
2
D. Maydan / Materials Science and Engineering A302 (2001) 1–5
date, the semiconductor industry has been able to do this through innovative chip design and by investing in advanced manufacturing technologies provided by the semiconductor equipment suppliers. Incorporating new technologies into a manufacturing line, besides imparting inherent advantages to chip performance like increased speed and storage capability, also has the effect of reducing die cost as each new generation of semiconductor manufacturing equipment is more productive than the last. Over the last 15 years, contributions from the equipment industry in the form of advanced wafer processing technologies have had a substantial effect on increasing fab output and, consequently, reducing the cost per bit. From 1984 to 1999, the ability of IC manufacturers to shrink their devices by shrinking minimum feature sizes resulted in an increase of 250 times more bits out per fab. In conjunction with improvements in equipment productivity, such as larger wafer sizes, higher reliability, better utilization of the wafer area, improved yields from particle reductions, equipment extendibility, and larger fab sizes that increase in the number of good bits out per fab explodes to 3000 times, regardless of the
Fig. 1. Comparison of industries.
Fig. 2. Contribution from the equipment industry to fab output.
type of device being manufactured. Fig. 2 shows the growth in fab output from 1984 to 1999 from equipment-enabling technology and productivity factors. The exponential increase in fab productivity, where the number of good bits out per fab triples every 2 years and thereby dramatically reduces bit cost, is a market enabler for the electronics sector as a whole. In keeping pace with the progress made over the last 15 years, the industry is now looking ahead to devices manufactured at 0.1 mm technology. In moving to 0.1 mm, however, semiconductor manufacturers are faced with problems associated with scaling transistors and capacitors as well as higher device delays from using traditional materials and designs in the interconnect portion of the chip. The equipment industry today is preparing for these technical challenges by characterizing new materials, developing new manufacturing techniques, and looking at novel ways of building structures that can enhance device performance while providing benefits to IC manufacturers in time to market, lower cost, and overall improved fab efficiency. At the transistor level, for example, scaling the device requires finer tuning and control of the implant process as well as thinner, higher k dielectric gates. Controlling the implant angle and ion beamline length results in more accurate doping and control of the junction profile. This, in turn, results in smaller threshold voltage shifts and less leakage current and, consequently, improves transistor reliability and performance. In gate stack applications, Applied Materials has demonstrated greater than two orders of magnitude improvement in leakage current by integrating the individual gate stack processes onto one single-wafer multichamber system platform. Eliminating the air-break between process steps preserves the integrity of the film interfaces while providing manufacturers with the capability of multiple processes in one tool. Using singlewafer processing chambers allows greater control and flexibility of the processes and, consequently, results in more uniform thermal films within the wafer as well as wafer-to-wafer. As transistors continue to scale down even further, where the thickness requirement of the gate approaches 15 A, and below, materials with higher k values like zirconium and hafnium silicates may need to be incorporated. Scaled capacitor structures must be optimized to make use of the reduced capacitor area while keeping the same capacitance. In order to scale, then, new materials as well as structures are being considered for the 0.1 mm technology node. Where most capacitors today are built using a metal-insulator –silicon scheme, tomorrow’s capacitors will use a metal-insulator –metal stack. Under consideration for the metal electrodes are materials like platinum and rubidium. New insulator materials include tantalum oxide, which is being used in many advanced devices today, and in the future may
D. Maydan / Materials Science and Engineering A302 (2001) 1–5
Fig. 3. Damascene process using low k dieletric and copper films.
shift to barium–strontium – titanate (BST) for the necessary higher k dielectric value. Again, applied materials has demonstrated today not only individual film capabilities but also integration of these processes onto one platform for better control of the final capacitor properties. One of the biggest challenges facing the non-memory IC manufacturers today is the problem of the interconnect. As device designs incorporate more and more functionality, the performance of the chips become limited by the interconnect. The number of wiring layers in the chip increases to accommodate the added functionality, but the problems of interconnect delay and device reliability become significant issues. By incorporating copper and lower k dielectrics into the interconnect scheme, manufacturers can both lower the interconnect delay and build their structures with fewer
3
layers as compared with advanced devices using traditional materials like aluminum and silicon dioxide. In changing materials, however, the conventional techniques and process sequences to deposit, etch, and planarize no longer apply. Where in the conventional interconnect process aluminum is deposited, etched, and then blanketed by a silicon dioxide film that is subsequently chemically mechanically planarized (CMP), the new techniques for copper and low k dielectrics is just the opposite. As shown in Fig. 3, a low k dielectric film is deposited (material with a dielectric constant of 2.8 or less), patterned, and etched. The troughs and lines are then filled with a very thin barrier film like tantalum or tantalum nitride (used to prevent copper migration to the silicon level) followed by a thin copper seed layer for the subsequent copper electroplating process. Once the bulk copper is put down through the electroplating process, the metals are planarized with a CMP process specific to copper and tantalum/tantalum nitride. This process is known as the Damascene process. The performance of the resulting interconnect stack using the Damascene process flow depends very heavily on the individual film properties as well as the interdependencies between sequential processes. For example, as shown in Fig. 4, it is critical that the individual film characteristics meet their respective specification requirements, like sheet resistance uniformity of the tantalum or copper layers, or sidewall coverage specifications for the metal deposition steps. However, it is also critical that the interdependencies of these films are characterized so that the resulting stack yields the desired result. Adding the bulk copper fill step to
Fig. 4. Typical product specifications and SEMs for individual pieces of equipment that are used to fabricate a copper wire.
4
D. Maydan / Materials Science and Engineering A302 (2001) 1–5
Fig. 5. ‘System Module’ approach using the copper wire example.
the equation means that the Barrier/Seed processes and the copper electroplating process together need characterizing, and once again with the addition of the copper CMP step. From the chip performance point of view, the first and foremost concern clearly is that the individual process results meet physical and electrical specifications. When integrated, again these stacks must meet electrical performance parameters. These processes, however, also need to be optimized from the fab productivity perspective. If throughput per system varies among processing tools, or maintenance schedules differ dramatically, a fab may take hits to its overall productivity. Given all of these new challenges, a novel approach to what has traditionally been called the ‘system’ has developed. Rather than looking at the device ‘layer by layer’ or ‘film by film’, one may look at the device ‘structure by structure’. In that way, the ‘system’ is defined by an input and an output in the context of a device structure such as a transistor, a capacitor, or interconnect. Using the copper wire within the interconnect as an example, to build the wire manufacturers need the three individual tools mentioned earlier. When used in sequence, the resulting structure is a functional copper wire. By defining a ‘system’ as a ‘Copper Wire System Module’, the three sub-components’ individual processes, their interdependencies, their throughput and their maintenance/service schedules can be optimized together to yield a solution that meets the specification for the wire itself. This ‘System Module’ approach is shown conceptually in Fig. 5. As a consequence, IC manufacturers are able to reduce their own development burden and shorten their time to market while taking advantage of processing improvements and a lower cost of manufacturing from increased fab efficiencies.
A fundamental requirement for ‘System Modules’ is that the reliability of these new systems will be equivalent to that of the individual tools. Throughput matching between the individual components and total service and support is key to the efficient operation of the whole system. Integrated metrology and inspection will also play a role in the real-time identification and classification of defects, either at the individual tool level or at the ‘System Module’ level. Integrating this function at the tool or Module level can eliminate the need for monitor and test wafers as well as reduce the use of tool time for running non-product wafers. To complete the new paradigm, additional software at the Module level, in the form of a Module controller, will communicate directly to the fab through the manufacturing execution system (MES) software. Most of the challenges mentioned have dealt with wafer processing issues, either from a technological point of view or an economic one. Detecting, measuring and characterizing sub-0.25 mm defects, however, will also present a formidable challenge to manufacturers in the future. This capability, although a necessary part of the chip manufacturing process for process control reasons, does not explicitly add value to the wafer. Hence, it is a natural function that should either be incorporated into the tool or System Module itself or attempts should be made to eliminate it entirely. Today, the process diagnostics and control (PDC) market exceeds $1 billion, and includes such sub-markets as mask and reticle inspection, defect review, critical dimension scanning electron microscopes (CD-SEM), and patterned wafer defect inspection. They function primarily as stand-alone tools in the manufacturing line. By the year 2003, this market is forecasted to be close to a $3 billion market. By folding naturally-fitting diagnostic and control functions into
D. Maydan / Materials Science and Engineering A302 (2001) 1–5
wafer processing tools and System Modules, however, the number of these non-processing stand-alone tools and, consequently, the expense related to them, can be reduced. The net outcome is a completely integrated wafer processing solution, with a guaranteed output, process result, and service profile. Addressing the needs of the semiconductor industry, both today and the future, is the fundamental mission of equipment suppliers. Providing the technology to get to smaller and smaller feature sizes as well as delivering
.
5
higher productivity equipment solutions is the first step toward meeting our customer’s needs. Applied Materials is committed to taking that even further by not only delivering enabling technology at the individual process level but also at the device structure level, and increasing focus on solutions for the entire fab. If we are successful, we will see a new period of expansive industry growth made possible by the gains from higher fab productivity as well as by greater accessibility to affordable electronic goods by new users around the world.
The future of equipment development and semiconductor production Dan Maydan * Applied Materials, 3050 Bowers A6enue, Santa Clara, CA 95054, USA
Abstract The semiconductor industry has experienced exceptional double-digit growth over the past 25 years, fueled by strong demand in end-use markets such as computing, communications, consumer appliances, and industrial applications. Its future, however, depends on the ability of semiconductor manufacturers and equipment suppliers alike to lower cost while pushing the technological limits of lithography, materials science, and further the development of new manufacturing techniques like dual damascene. This paper will describe in detail those technology challenges that semiconductor manufacturers and equipment suppliers must overcome to extend Moore’s law into the next century, as well as highlight areas where equipment productivity has added, and can continue to add, tremendous value to the growth of the industry. Finally, a new paradigm called Process Module Systems will be put forth to address the increasingly complex manufacturing requirements as well as economic challenges that the industry, as a whole, faces. © 2001 Published by Elsevier Science B.V. Keywords: Equipment development; Semiconductor production; Process module systems
The invention of the integrated circuit in 1958 provided a fundamental building block for the Information Age, which by all measures, is expanding and thriving today. This era, though infant, is notable already for its dramatic growth and impact on our world. As shown in Fig. 1, it has surpassed in size the giant plastics industry, and is on a path of approaching the even larger steel sector. In a brief 25 years, the semiconductor industry has increased almost 40-fold, or 16% on average annually, fueled by demand for personal computers, communication devices, electronic consumer products, as well as many other electronic goods that consume millions and millions of chips each year. The wafer processing equipment industry, growing at the same annual rate as the semiconductor industry, has played a pivotal role in enabling this growth. Whether this historical growth rate continues into the new millennium depends on several factors. Demand for personal electronic products like computers or games could fall affecting both chip unit volume as well as production revenue. On the device side, the theoretical physical limits of semiconductors and lithography * Tel.: +1-408-9863176. E-mail address: [email protected] (D. Maydan).
capability are also potential showstoppers, especially at technologies below 0.10 mm. The integration portion of wafer processing at sub-0.10 mm presents a new set of challenges as well given the relative complexity of advanced devices. Furthermore, the sheer expense of new factories could result in fewer fabs built, affecting the overall rate of capital investment by semiconductor manufacturers. Taken alone or in combination, these factors have the potential to slow semiconductor growth. From a broader perspective, however, the opportunities in the Information Age appear enormous. The combination of an improving global macroeconomic environment as well as the world’s embrace and rapid implementation of the worldwide web are fueling strong demand for electronic products and services today. Of the world’s population, for example, the percentage of people with personal computers is just under 2%. Penetration of electronic devices on a personal level throughout the world is under-saturated and providing the basis for a prosperous future in the electronics sector. At the semiconductor level, meeting the increasing demand for electronic goods means producing more capability-enabling chips at lower and lower cost. To
0921-5093/01/$ - see front matter © 2001 Published by Elsevier Science B.V. PII: S0921-5093(00)01345-9
2
D. Maydan / Materials Science and Engineering A302 (2001) 1–5
date, the semiconductor industry has been able to do this through innovative chip design and by investing in advanced manufacturing technologies provided by the semiconductor equipment suppliers. Incorporating new technologies into a manufacturing line, besides imparting inherent advantages to chip performance like increased speed and storage capability, also has the effect of reducing die cost as each new generation of semiconductor manufacturing equipment is more productive than the last. Over the last 15 years, contributions from the equipment industry in the form of advanced wafer processing technologies have had a substantial effect on increasing fab output and, consequently, reducing the cost per bit. From 1984 to 1999, the ability of IC manufacturers to shrink their devices by shrinking minimum feature sizes resulted in an increase of 250 times more bits out per fab. In conjunction with improvements in equipment productivity, such as larger wafer sizes, higher reliability, better utilization of the wafer area, improved yields from particle reductions, equipment extendibility, and larger fab sizes that increase in the number of good bits out per fab explodes to 3000 times, regardless of the
Fig. 1. Comparison of industries.
Fig. 2. Contribution from the equipment industry to fab output.
type of device being manufactured. Fig. 2 shows the growth in fab output from 1984 to 1999 from equipment-enabling technology and productivity factors. The exponential increase in fab productivity, where the number of good bits out per fab triples every 2 years and thereby dramatically reduces bit cost, is a market enabler for the electronics sector as a whole. In keeping pace with the progress made over the last 15 years, the industry is now looking ahead to devices manufactured at 0.1 mm technology. In moving to 0.1 mm, however, semiconductor manufacturers are faced with problems associated with scaling transistors and capacitors as well as higher device delays from using traditional materials and designs in the interconnect portion of the chip. The equipment industry today is preparing for these technical challenges by characterizing new materials, developing new manufacturing techniques, and looking at novel ways of building structures that can enhance device performance while providing benefits to IC manufacturers in time to market, lower cost, and overall improved fab efficiency. At the transistor level, for example, scaling the device requires finer tuning and control of the implant process as well as thinner, higher k dielectric gates. Controlling the implant angle and ion beamline length results in more accurate doping and control of the junction profile. This, in turn, results in smaller threshold voltage shifts and less leakage current and, consequently, improves transistor reliability and performance. In gate stack applications, Applied Materials has demonstrated greater than two orders of magnitude improvement in leakage current by integrating the individual gate stack processes onto one single-wafer multichamber system platform. Eliminating the air-break between process steps preserves the integrity of the film interfaces while providing manufacturers with the capability of multiple processes in one tool. Using singlewafer processing chambers allows greater control and flexibility of the processes and, consequently, results in more uniform thermal films within the wafer as well as wafer-to-wafer. As transistors continue to scale down even further, where the thickness requirement of the gate approaches 15 A, and below, materials with higher k values like zirconium and hafnium silicates may need to be incorporated. Scaled capacitor structures must be optimized to make use of the reduced capacitor area while keeping the same capacitance. In order to scale, then, new materials as well as structures are being considered for the 0.1 mm technology node. Where most capacitors today are built using a metal-insulator –silicon scheme, tomorrow’s capacitors will use a metal-insulator –metal stack. Under consideration for the metal electrodes are materials like platinum and rubidium. New insulator materials include tantalum oxide, which is being used in many advanced devices today, and in the future may
D. Maydan / Materials Science and Engineering A302 (2001) 1–5
Fig. 3. Damascene process using low k dieletric and copper films.
shift to barium–strontium – titanate (BST) for the necessary higher k dielectric value. Again, applied materials has demonstrated today not only individual film capabilities but also integration of these processes onto one platform for better control of the final capacitor properties. One of the biggest challenges facing the non-memory IC manufacturers today is the problem of the interconnect. As device designs incorporate more and more functionality, the performance of the chips become limited by the interconnect. The number of wiring layers in the chip increases to accommodate the added functionality, but the problems of interconnect delay and device reliability become significant issues. By incorporating copper and lower k dielectrics into the interconnect scheme, manufacturers can both lower the interconnect delay and build their structures with fewer
3
layers as compared with advanced devices using traditional materials like aluminum and silicon dioxide. In changing materials, however, the conventional techniques and process sequences to deposit, etch, and planarize no longer apply. Where in the conventional interconnect process aluminum is deposited, etched, and then blanketed by a silicon dioxide film that is subsequently chemically mechanically planarized (CMP), the new techniques for copper and low k dielectrics is just the opposite. As shown in Fig. 3, a low k dielectric film is deposited (material with a dielectric constant of 2.8 or less), patterned, and etched. The troughs and lines are then filled with a very thin barrier film like tantalum or tantalum nitride (used to prevent copper migration to the silicon level) followed by a thin copper seed layer for the subsequent copper electroplating process. Once the bulk copper is put down through the electroplating process, the metals are planarized with a CMP process specific to copper and tantalum/tantalum nitride. This process is known as the Damascene process. The performance of the resulting interconnect stack using the Damascene process flow depends very heavily on the individual film properties as well as the interdependencies between sequential processes. For example, as shown in Fig. 4, it is critical that the individual film characteristics meet their respective specification requirements, like sheet resistance uniformity of the tantalum or copper layers, or sidewall coverage specifications for the metal deposition steps. However, it is also critical that the interdependencies of these films are characterized so that the resulting stack yields the desired result. Adding the bulk copper fill step to
Fig. 4. Typical product specifications and SEMs for individual pieces of equipment that are used to fabricate a copper wire.
4
D. Maydan / Materials Science and Engineering A302 (2001) 1–5
Fig. 5. ‘System Module’ approach using the copper wire example.
the equation means that the Barrier/Seed processes and the copper electroplating process together need characterizing, and once again with the addition of the copper CMP step. From the chip performance point of view, the first and foremost concern clearly is that the individual process results meet physical and electrical specifications. When integrated, again these stacks must meet electrical performance parameters. These processes, however, also need to be optimized from the fab productivity perspective. If throughput per system varies among processing tools, or maintenance schedules differ dramatically, a fab may take hits to its overall productivity. Given all of these new challenges, a novel approach to what has traditionally been called the ‘system’ has developed. Rather than looking at the device ‘layer by layer’ or ‘film by film’, one may look at the device ‘structure by structure’. In that way, the ‘system’ is defined by an input and an output in the context of a device structure such as a transistor, a capacitor, or interconnect. Using the copper wire within the interconnect as an example, to build the wire manufacturers need the three individual tools mentioned earlier. When used in sequence, the resulting structure is a functional copper wire. By defining a ‘system’ as a ‘Copper Wire System Module’, the three sub-components’ individual processes, their interdependencies, their throughput and their maintenance/service schedules can be optimized together to yield a solution that meets the specification for the wire itself. This ‘System Module’ approach is shown conceptually in Fig. 5. As a consequence, IC manufacturers are able to reduce their own development burden and shorten their time to market while taking advantage of processing improvements and a lower cost of manufacturing from increased fab efficiencies.
A fundamental requirement for ‘System Modules’ is that the reliability of these new systems will be equivalent to that of the individual tools. Throughput matching between the individual components and total service and support is key to the efficient operation of the whole system. Integrated metrology and inspection will also play a role in the real-time identification and classification of defects, either at the individual tool level or at the ‘System Module’ level. Integrating this function at the tool or Module level can eliminate the need for monitor and test wafers as well as reduce the use of tool time for running non-product wafers. To complete the new paradigm, additional software at the Module level, in the form of a Module controller, will communicate directly to the fab through the manufacturing execution system (MES) software. Most of the challenges mentioned have dealt with wafer processing issues, either from a technological point of view or an economic one. Detecting, measuring and characterizing sub-0.25 mm defects, however, will also present a formidable challenge to manufacturers in the future. This capability, although a necessary part of the chip manufacturing process for process control reasons, does not explicitly add value to the wafer. Hence, it is a natural function that should either be incorporated into the tool or System Module itself or attempts should be made to eliminate it entirely. Today, the process diagnostics and control (PDC) market exceeds $1 billion, and includes such sub-markets as mask and reticle inspection, defect review, critical dimension scanning electron microscopes (CD-SEM), and patterned wafer defect inspection. They function primarily as stand-alone tools in the manufacturing line. By the year 2003, this market is forecasted to be close to a $3 billion market. By folding naturally-fitting diagnostic and control functions into
D. Maydan / Materials Science and Engineering A302 (2001) 1–5
wafer processing tools and System Modules, however, the number of these non-processing stand-alone tools and, consequently, the expense related to them, can be reduced. The net outcome is a completely integrated wafer processing solution, with a guaranteed output, process result, and service profile. Addressing the needs of the semiconductor industry, both today and the future, is the fundamental mission of equipment suppliers. Providing the technology to get to smaller and smaller feature sizes as well as delivering
.
5
higher productivity equipment solutions is the first step toward meeting our customer’s needs. Applied Materials is committed to taking that even further by not only delivering enabling technology at the individual process level but also at the device structure level, and increasing focus on solutions for the entire fab. If we are successful, we will see a new period of expansive industry growth made possible by the gains from higher fab productivity as well as by greater accessibility to affordable electronic goods by new users around the world.