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The Heidelberg Polyp system
R&D reports 'Parallel image-processing system based on the TMS32010 digital signal processor' lEE Proc. E Vol 134 No 2 (March 1987) pp 119-124 The parallel image processor described comprises eight parallel TMS32010 DSP chips controlled by a 68000-based single-board computer. An image is loaded into an image buffer which is divided into eight segments to be processed by each of the 32010s. Two common pattern recognition algorithms, edge detection and thinning, have been implemented, giving a processing time of less than 1 s for a 256 X 256 pixel image, the authors claim.
Instrumentation and control Benedetti, M and Christiansen, C F 'Universal microprocessor controller for thyristor phase control of multiphase converters' Int. J. Electron. Vo162 No 3 (March 1987) pp 385-392 The authors describe a digital trigger system for thyristor converters, using a dedicated 6800 microprocessor, two 6 8 2 1 peripheral interface adaptors, I kbyte of ROM for main program and linearization tables and 56 kbyte of RAM for data storage. Only one program is needed for all circuit configurations due to a novel synchronization system.
Memoff Anon. 'Expand memory addressing capabilities of 16-bit microprocessor' IBM Tech. Disclosure Bull Vol 29 No 9 (February 1987) pp 3821-3822 Memory expansion from 512 kbyte up to 896 kbyte is detailed for IBM PCs etc.
Furht, B and Milutinovic, V 'A survey of microprocessor architectures for memory management' IEEE Computer Vol 20 No 3 (March 1987) pp 48-67 Implementation of memory management techniques such as address
Vol 11 No 5 June 1987
translation schemes, associative cache memory and virtual memory support are discussed. These techniques are illustrated with reference to today's 16- and 32-bit microprocessors (Intel 80286, 386 and 432; Motorola 68010 and 68020; National Semiconductor 32032; Zilog Z80000).
Microprocessors Burns, D and Jones, D 'Enter the 68030' SysL InL Vol 15 No 4 (April 1987) pp 75-77 The authors, microprocessor applications engineers for Motorola UK, detail the new features of the second-generation 32-bit MC68030 CPU.
channels: a main memory bus, which has the usual structure of a parallel backplane bus; and a second bus which typically uses serial transmission, for interprocessor communications, for example. The paper describes work on the design, test and building of a serial transmission system for the M3 multiprocessor architecture developed by the Italian National Research Council (CNR) and the Politecnico di Torino.
Hori, M, Doi, K, Tezuka, H, Yosida, T, Kimura, N and Yamashita, Y 'Sony packs power into low-cost work stations' Electronics Vo160 No 6 (19 March 1987) pp 79-81
Cole, B C 'Dallas Semiconductor's microcontroller updates itself on the fly' Electronics Vol 60 No 5 (6 March 1987)
Sony's News 'network station' uses two 68020s -- one as a CPU and one as an I/O processor--and a 68881 floating-point coprocessor. It has a VMEbus interface, is networked via Ethernet and the TCP/IP upper-level protocol, and runs under Unix 4.2 BSD. Design considerations and features of the system are covered in this adaptation of an original article.
Describes the DS5000 microcontroller from US firm Dallas Semiconductor, an 8051-compatible device with piggybacked static RAM to allow remote reprogramming within nanoseconds. Built-in logic gives data and microcode security.
Li, K F, Dinopoulous, N J and Atwood, l A 'The HM-Nucleus: distributed kernel design for the homogeneous multiprocessor' IEEE Micro Vol 7 No I (February 1987) pp 14-23
Schopmeyer, R 'System timing sets microprocessor performance' Comput. Des. Vol 26 No 6 (15 March 1987) pp 67-70
Architectural features, the hardwaresoftware interface and memory management on the multi-68000 Homogeneous Multiprocessor are described.
The design and implementation of an 80286-based workstation with no wait states or cache memory, the Convergent Technologies CP002, are described.
Multiprocessors Del Corso, D, Civera, P L, Reyneri, L and Sanscoe, C 'An integrated controller for modified inter-integrated circuit protocol' Microprocess. Microprog. Vol 19 No 2 (February 1987) pp 153-166 Recent multiprocessor buses specify a set of independent communication
Maenner, R, Shoemaker, R L and Bartels, P H 'The Heidelberg Polyp system' IEEE Micro Vol 7 No 1 (February 1987) pp 5-I 3 The Polyp 'polyprocessor' allows users to configure the appropriate number of processing elements (PEs) for a particular task, and allows them to choose between, for example, PEs based on a 68000 CPU for simple tasks and PEs based on a 68020 with 68881 coprocessor for number crunching. The design and architecture of Polyp, and its Polybus and Syncbus systems, are described here.
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Instrumentation and control Benedetti, M and Christiansen, C F 'Universal microprocessor controller for thyristor phase control of multiphase converters' Int. J. Electron. Vo162 No 3 (March 1987) pp 385-392 The authors describe a digital trigger system for thyristor converters, using a dedicated 6800 microprocessor, two 6 8 2 1 peripheral interface adaptors, I kbyte of ROM for main program and linearization tables and 56 kbyte of RAM for data storage. Only one program is needed for all circuit configurations due to a novel synchronization system.
Memoff Anon. 'Expand memory addressing capabilities of 16-bit microprocessor' IBM Tech. Disclosure Bull Vol 29 No 9 (February 1987) pp 3821-3822 Memory expansion from 512 kbyte up to 896 kbyte is detailed for IBM PCs etc.
Furht, B and Milutinovic, V 'A survey of microprocessor architectures for memory management' IEEE Computer Vol 20 No 3 (March 1987) pp 48-67 Implementation of memory management techniques such as address
Vol 11 No 5 June 1987
translation schemes, associative cache memory and virtual memory support are discussed. These techniques are illustrated with reference to today's 16- and 32-bit microprocessors (Intel 80286, 386 and 432; Motorola 68010 and 68020; National Semiconductor 32032; Zilog Z80000).
Microprocessors Burns, D and Jones, D 'Enter the 68030' SysL InL Vol 15 No 4 (April 1987) pp 75-77 The authors, microprocessor applications engineers for Motorola UK, detail the new features of the second-generation 32-bit MC68030 CPU.
channels: a main memory bus, which has the usual structure of a parallel backplane bus; and a second bus which typically uses serial transmission, for interprocessor communications, for example. The paper describes work on the design, test and building of a serial transmission system for the M3 multiprocessor architecture developed by the Italian National Research Council (CNR) and the Politecnico di Torino.
Hori, M, Doi, K, Tezuka, H, Yosida, T, Kimura, N and Yamashita, Y 'Sony packs power into low-cost work stations' Electronics Vo160 No 6 (19 March 1987) pp 79-81
Cole, B C 'Dallas Semiconductor's microcontroller updates itself on the fly' Electronics Vol 60 No 5 (6 March 1987)
Sony's News 'network station' uses two 68020s -- one as a CPU and one as an I/O processor--and a 68881 floating-point coprocessor. It has a VMEbus interface, is networked via Ethernet and the TCP/IP upper-level protocol, and runs under Unix 4.2 BSD. Design considerations and features of the system are covered in this adaptation of an original article.
Describes the DS5000 microcontroller from US firm Dallas Semiconductor, an 8051-compatible device with piggybacked static RAM to allow remote reprogramming within nanoseconds. Built-in logic gives data and microcode security.
Li, K F, Dinopoulous, N J and Atwood, l A 'The HM-Nucleus: distributed kernel design for the homogeneous multiprocessor' IEEE Micro Vol 7 No I (February 1987) pp 14-23
Schopmeyer, R 'System timing sets microprocessor performance' Comput. Des. Vol 26 No 6 (15 March 1987) pp 67-70
Architectural features, the hardwaresoftware interface and memory management on the multi-68000 Homogeneous Multiprocessor are described.
The design and implementation of an 80286-based workstation with no wait states or cache memory, the Convergent Technologies CP002, are described.
Multiprocessors Del Corso, D, Civera, P L, Reyneri, L and Sanscoe, C 'An integrated controller for modified inter-integrated circuit protocol' Microprocess. Microprog. Vol 19 No 2 (February 1987) pp 153-166 Recent multiprocessor buses specify a set of independent communication
Maenner, R, Shoemaker, R L and Bartels, P H 'The Heidelberg Polyp system' IEEE Micro Vol 7 No 1 (February 1987) pp 5-I 3 The Polyp 'polyprocessor' allows users to configure the appropriate number of processing elements (PEs) for a particular task, and allows them to choose between, for example, PEs based on a 68000 CPU for simple tasks and PEs based on a 68020 with 68881 coprocessor for number crunching. The design and architecture of Polyp, and its Polybus and Syncbus systems, are described here.
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