The impact of packaging on the reliability of flip-chip solder bonded devices

1050

World Abstracts on Microelectronics and Reliability

The impact of packaging on the reliability of flip-chip solder bonded devices. KEVINJ. LODGEand DAVID J. PEDDER. IEEE Trans. Compon. Hybrids mfg TechnoL 13(4), 847 (1990). Flip-chip solder bonding offers numerous advantags over other, more conventional interconnection methods. In particular, the small bond size and short bond length lead to minimal electrical parasitics and to excellent high frequency behavior. The designable, selfaligning nature of the bonding technique also makes it well suited for micro-optic applications. In addition, flip-chip solder bonding offers very high interconnection density and the ability to place connections over the whole active area of the flip-chip solder bonding has, to date, been limited to relatively few users operating in closely controlled environments. This is related, in part, to concern over the reliability of this particular bonding technique. In flip-chip bonded devices, all mechanical and electrical interconnections pass through the solder bonds which, even at normal operating temperatures, are working at over two thirds of their absolute melting points. At such temperatures, yield strengths are low and processes such as creep and recrystallization can occur. Cyclic stresses caused by differential expansion between dissimilar materials or similar materials at differing temperatures in a device assembly can then lead to solder joint plastic deformation and to potential failure by a low cycle fatigue mechanism. There is currently a resurgence of interest in flip-chip solder bonding for a variety of applications, including interconnection of sensor arrays, VLSI integrated circuits, and in multichip module (MCM) construction. The question of flip-chip reliability, therefore, requires renewed attention in the context of these emerging device structures. This paper reports on the assessment of flip-chip solder joint reliability for a hybrid device assembly in which a zirconium-titanium-stannate (ZTS) dielectric ceramic chip is flip-chip bonded to a silicon circuit. This device assembly was subjected to severe thermal cycling testing, involving up to 2000 cycles from - 5 5 to + 125°C. A range of device solder bond geometries and chip passivation structures was investigated, with devices packaged in both hermetic and nonhermetic enclosures. The results showed that flip-chip solder bonds can be extremely reliable under such tests, with no failures being detected in devices that were hermetically packaged. Fatigue failures were observed in nonhermetically packaged devices. Extrapolation to likely operating conditions predicted field lifetimes of between 15 and 300 a. A review of thermal enhancement techniques for electronic systems. LEROY S. FLETCHER. IEEE Trans. Compon. Hybrids mfg Technol. 13(4), 1012 (1990). The demand for electronic components which will satisfy performance standards over a wide range of environmental conditions requires the use of thermal enhancement techniques. This paper reviews recent thermal enhancement techniques for maximizing the thermal contact conductance, including greases, metallic foils, and screens, composite materials and cements, and surface treatments. The relative merits of the various enhancement techniques are summarized and comparisons are made for selected thermal enhancement materials. The results of this review will be useful in selecting thermal enhancement materials for use in improving the thermal performance of electronic systems. Preparation, structure, and fracture modes of Pb-Sn and Pb-ln terminated flip-chips attached to gold capped micro6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S , Improved and new surface analysis and depth profiling methods for the analysis of semiconductor technology problems. R. V. CRIEGERN. Vacuum 41(7-9), 1611 (1990). Following the ceaseless miniaturization of semiconductor

sockets. KARL J. PUTTLITZ. IEEE Trans. Compon. Hybrids mfg Technol. 13(4), 647 (1990). Solder-bump flip-chip (SBFC) interconnection technology has proven to be reliable, cost-effective, and extendable. This type of chip-tosubstrate connection, also referred to as a controlledcollapse chip connection or C-4, is used in IBM's multilayer ceramic (MLC), metallized ceramic (MC), and thick film packages. On MLC substrates, flip-chip interconnects are achieved by placing diced chips face down and simultaneously reflowing the chip I/Os directly to corresponding substrate pads, termed microsockets. The substrate's molybdenum thick film conductor material is not directly wet by lead-tin or lead-indium terminated chips. Several preparatory metallization steps are required to render the surface suitable for solderability and chip attach. Fatigue life of thermal cycled solder joints directly depends upon the integrity and metallurgical properties of the joint interfaces and bulk solder characteristics. This paper discusses the effect of selecting nickel, deposited from an electroless phosphorus-based bath, as the base metal to achieve solder wetting. Specifically discussed are the degrading effects on solder wetting due to precipitate formation during process thermal exposure and the use of a gold cap to prevent the problem. Also addressed are the overall metallurgical characteristics of both lead-tin and lead indium C-4 joints, as well as their relation to performance (e.g. fracture mode and fatigue life). New method of water cleaning for circuit substrate. NAO TAKAYAMA, TOMIJI SUGIYAMAand KAZUHIKOTAKAHASHI. IEEE Trans. Compon. Hybrids mfg Technol. 13(4), 685 (1990). Soldering technology using rosin flux has been developed in the electronics industry due to the advantageous characteristics that it does not cause corrosion of conductors and the stability of the flux is high. Recently, however, the solvent which is commonly used for postcleaning of rosin flux residue (CFC-II3) has been linked to environmental pollution, especially ozone depletion. Many engineers are now wrestling with the difficult problem of developing an alternative cleaning method. Until now various kinds of water soluble flux have been practically used only for the wave soldering process. Utilization of the same type of flux in solder paste for the reflow soldering process has not been successful. This is because the solder particle and the flux of solder paste are required to contact each other under chemically stable conditions for extended periods, and this technical barrier made it fairly difficult to make practical use of solder pastes containing water soluble flux. We have developed a water soluble flux paste that has excellent characteristics equivalent to those of rosin flux by improving the activator and rheological modifier. Also, we have simultaneously developed original and novel cleaning equipment. The new solder paste and cleaning method was applied to on board power supply (OBP) products, and these products passed 1500 h of temperature, humidity, bias (THB) testing. This ensures that the new method, combining the newly developed water soluble paste and the cleaning equipment, can provide the same reliability of reflow soldered product as that of the product processed by the conventional cleaning method using rosin flux and solvent. SYSTEMS

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circuits, the analytical technological processes This applies particularly new specific analytical

EQUIPMENTS

techniques used to develop their must be continuously improved. to the lateral resolution, but also to needs, for example the sensitive