- Email: [email protected]
The impact of silicon brick polishing on thin (120 μm) silicon wafer sawing yields and fracture strengths in diamond-wire sawing
Materials Science in Semiconductor Processing 105 (2020) 104751
Contents lists available at ScienceDirect
Materials Science in Semiconductor Processing journal homepage: http://www.elsevier.com/locate/mssp
The impact of silicon brick polishing on thin (120 μm) silicon wafer sawing yields and fracture strengths in diamond-wire sawing Halubai Sekhar *, Tetsuo Fukuda **, Katsuto Tanahashi, Hidetaka Takato Renewable Energy Research Center, Fukushima Renewable Energy Institute (FREA), National Institute of Advanced Industrial Science and Technology (AIST), 2-2-9 Machi-ikedai, Koriyama, Fukushima, 963-0298, Japan
A R T I C L E I N F O
A B S T R A C T
Keywords: Silicon bricks Diamond wires Three-line bending Wafer fracture strength Ground brick Mirror-polished brick
The present study recommends sawing thin (120 μm) silicon (Si) wafers using thin (120 μm) diamond wire with higher throughputs and sawing yields (>96%). In a multi-wire saw, an improved type of diamond wire (100 d/ M6-12) is employed to saw ground (g) and mirror-polished (p) Si bricks into thin (120 μm) Si wafers. Im provements in both diamond wire and Si brick surface allow us to saw thin (120 μm) Si wafers with higher fracture strengths and sawing yields of over 96%. The wafers sawn from g and p Si bricks are labeled as g- Si wafers and p- Si wafers. Depending on wire wear position, sawn wafers are labeled as fresh-wire and worn-wire sides. In a three-line bending test, mechanical loads were applied perpendicular to the wire saw marks on the middle of each wafer to measure its fracture strength. Two fundamental differences are observed in the fracture strengths of g- and p- Si wafers. The g- Si wafers fractured at lower strengths compared with the p- Si wafers. Both g- and p- Si wafers from the fresh-wire side fractured at lower strengths compared with worn-wire-side wafers. To address the fracture strength difference, edge chipping and fractographic studies were carried out. The wafer edges were observed at wire entrance and wire exit sides in the Si brick. At the wire exit side, the wafer surface contains a large number of pits followed by longer chipping lengths and widths compared with the wire entrance side. The fractographic studies were performed on fractured samples collected from the middle of the wafer by observing its cross-sections. The wafers fractured at low-strength samples follow mirror mechanisms, and the wafers fractured at intermediate- and higher-strength samples follow any one of mirror–mist, mist, hackle, branching or a mixture of these mechanisms.
1. Introduction In the semiconductor industry, silicon (Si) is an essential material for the applications of integrated circuits and photovoltaic cells [1–8]. First-generation wafer-based crystalline and multi-crystalline Si (c-Si and mc-Si) solar cells possess an overwhelming market share of above 90% because of their excellent device performance and longer lifetimes [2]. To manufacture Si wafers for application in photovoltaics (PVs), the following pre- and post-processing steps are required: grow high-quality Si crystal, crop the crystal into a brick shape, grind, polish, saw wafers, and etch out saw damage [8–10]. Currently, state-of-the-art c-Si wafers, with a thickness of 180–170 μm, are used in the industry to produce solar cells. The Si wafer itself constitutes approximately 52% of the module price [2,4]. Thus, there is ample space to minimize the cost by minimizing the bulk material in the form of thin wafers. It is
recommended to saw a greater number of wafers from a given amount of raw material by lowering the Si wafer thickness and its kerf. Because of the intrinsic brittle nature of Si, sawing thinner wafers leads to higher breakage, nullifying the gain made by lower material consumption (thin wafer), so a special way is needed to overcome the breakage problem [4]. During the period 2018–2029, the international technology road map for photovoltaic (ITRPV) predicts that sawn wafer thickness will decrease from 180 to 130 μm for c-Si, and to 150 μm for mc-Si [2]. In this introduction we primarily discuss various technologies to saw Si bricks into wafers, and the feasibility to adopt each one for mass-scale production. It has been reported that the Si bricks are sawn into wafers in two ways: internal diameter (ID) saw, and multi-wire saw [2,9–11]. In an ID saw, nickel-bonded diamond grits are coated on a thin annular blade that is used to cut the wafers. It cuts only one wafer at a time and therefore consumes more time to process the whole Si brick into wafers.
* Corresponding author. ** Corresponding author. E-mail addresses: [email protected], [email protected] (H. Sekhar), [email protected] (T. Fukuda). https://doi.org/10.1016/j.mssp.2019.104751 Received 9 June 2019; Received in revised form 29 August 2019; Accepted 22 September 2019 1369-8001/© 2019 Published by Elsevier Ltd.
H. Sekhar et al.
Materials Science in Semiconductor Processing 105 (2020) 104751
Fig. 1. (a) SEM image of a developed diamond wire 100 d/M6-12. (b) Ground (g) Si brick. (c) Mirror-polished Si brick.
It is not economically viable for an ID saw to meet industrial needs or perform well in cost competition because of its low productivity and cutting yields [11]. To address these issues in the industry, multi-wire sawing technology has been introduced. In this, wires are wrapped on the guiding roller which run parallel to each other with a constant pitch. It allows the entire Si brick to be processed into wafers at once, which makes it economically feasible to scale up to larger volumes [11]. In the last few decades, the advantages provided by multi-wire sawing tech nology have been inspiring the industry to cut Si bricks into wafers in this way [2]. In multi-wire sawing, hard, abrasive particles are used to abrade the Si brick into the form of wafers. Depending upon the abrasives on the wire, multi-wire sawing is categorized into two types: loose-abrasive (slurry) and fixed-abrasive (diamond) wire. The material abrasion mechanism in loose-abrasive and fixed-abrasive wires is different [12–14]. In slurry wire sawing, the wire moves forward and exerts force on the abrasive particles (SiC particles with irregular shape) allows to roles between the wire and the brick and induct the Si brick. In slurry
cutting, the material abrasion occurs in brittle mode finished by three-body wear, and deforms the Si brick into the form of wafers. In the abrasion, the wire loses its strength through the indentation of sharp abrasive particles on the wire [13–16]. For each new cutting, both the wire and abrasives need to be replaced, which has an impact on pro duction costs. In this cutting, thin Si wafer sawing yields were improved by polishing (by conventional and mirror polishing) Si bricks [16]. Conventional polishing of Si bricks allows the sawing of Si wafers with thicknesses of 120 μm and 100 μm, with sawing yields of 71% and 60%, respectively. Mirror polishing allows the sawing of Si wafers with thicknesses of 120 μm and 100 μm, with sawing yields of 80% and 83.6%, respectively [16]. In this cutting, micro-cracks are randomly distributed on the wafer surface and propagated over several tens of microns inside the bulk material [15,16], which limits progress on thinner wafers by yield loss. In diamond-wire sawing (DWS), the abrasive particles are attached to a steel wire surface by resin bonding or electroplating techniques. In DWS, the wire moves in forward and backward (cyclic) motion and
Fig. 2. (a) Schematic of multi-wire diamond saw. (b) As-sawn Si wafers (120 μm) stuck to a supporting substrate. (c) Schematics of three-line bending tester [17,18]. 2
H. Sekhar et al.
Materials Science in Semiconductor Processing 105 (2020) 104751
scratches the Si surface by indentation, which excites the Si surface layers in different phases (ductile mode) [17–22]. The material chipping (flaking) in ductile mode allows a decrease in subsurface micro-cracks, which encourages progress toward lower wafer thickness with higher yields than before. In this cutting, material abrasion finished by two-body wear, which involves the direct interaction of the diamond abrasives with the Si brick [23]. In physical sawing, the high-speed sliding contacts of diamond abrasives on Si brick generates huge pres sure on both. As a result, there is a high probability that resin-bonded diamond grits easily attract wear and tear compared with electro plated diamond grits [23–25]. To cut Si materials during the period 2018–2029, ITRPV predicts that electroplated diamond wire will dominate with a higher market share (90%) compared with resin-bonded diamond wire [2]. It also reports that the growth in sawing c-Si and mc-Si wafers using diamond wires is going to see it occupy a market share of over 90% by 2022 [2]. In DWS, wire and Si brick feed speeds are relatively high, which allows higher cutting speeds (three times faster), with higher efficiencies, lower processing time, lower power consumption, and less wearing down of the core metal wire [26]. To achieve the objectives of the ITRPV road map for the years 2018–2029, the present study provides an opportunity to progress on thin (120 μm) Si wafer sawing using thin diamond wire, particularly as sawn thin Si wafers have higher fracture strengths with sawing yields above 96%.
Fig. 3. Surface profile of DWS Si wafer surface.
comes from fresh-wire-side wafer breakage. To measure the fracture strength of Si sawn wafers, we employed a simple uniaxial three-line bending test performed using a Shimadzu Autograph AG-X plus tester [17,18]. In our bending test, the loads were applied on the middle of the wafer to generate the maximum peak stress under a loading axis (Fig. 2 (c)) on the wafer surface, and minimum negligible stress on both wafer edges parallel to the loading bar [18,19]. The wafer sat on two supporting line bars. A variable mechanical load was attached to the third line bar. In Fig. 2 (c), the loads are shown as red arrows and are operated from an automated computer-controlled pro gram, and the loads were applied with an incremental speed of 3 mm/min onto the middle of the wafer. By measuring the load at the moment of wafer fracture, we were able to calculate and statistically analyze the wafer fracture strength using the following equation [18, 19]:
2. Experimental conditions With a precise control on the electroplating technique, the diamond particles are attached on the wire with less agglomeration and higher dispersion, as shown in Fig. 1 (a). The wire is known as improved dia mond wire, labeled 100 d/M6-12, where diamond particles (diameter 6–12 μm) are attached to the core steel wire (diameter 100 μm) with the help of metal particles as a coating layer. To address the impact of the Si brick surface condition on its wafer fracture strengths in DWS, the Si bricks are ground and mirror polished, as shown in Fig. 1(b) and (c). The surface roughness of Si bricks is measured using Surftest SJ-310 (Mitu toyo). Thin wafer sawings are performed under commercial multi-wire saw for large-scale production machines, a rough schematic of which is shown in Fig. 2 (a). By employing improved diamond wire, both ground and mirror-polished Si brick saw separately into wafers. Here inafter we refer to the wafers sawn from ground Si brick as g- Si wafers, and to those from mirror-polished Si brick as p- Si wafers. The diamond wire (length ~25 km) is wrapped onto the wire spool and labeled as new wire spool, and it feeds the diamond wire into the wire web. In the wire web, the wire passes from the grooves of equidistant pitch (240 μm) onto the guiding roller, where the wire lengths run parallel to each other as shown in the schematic in Fig. 2 (a). The Si brick is attached with glue onto the support bar. The brick sawing parameters are as follows [17, 18]. The tension on the wire is 19 N. The wire speed is 1000 m/min. The wire moves in forward and backward motion with a cyclic moment of 2 min/c. The mono c-Si brick with a pseudo-square cross-section of 156 � 156 mm2 feeds towards the wire web with a speed of 0.53 mm/min. The used wire is collected from a worn wires pool on the other side. The used wire length per wafer is 2–4 m. As the sawing progresses, the scratching and indenting of the abrasives removes the material in the form of wafers from the workpiece. The mono c-Si bricks are sawn into thin (120 μm) Si wafers stuck to a supporting substrate as shown in Fig. 2 (b). Depending on the wire wear position on the Si brick, the sawn wafers are labeled as either fresh-wire (diamond wire entrance) side or worn-wire (diamond wire exit) side wafers. The wafers are separated manually, cleaned with soapy water, rinsed under distilled water, dried with nitrogen flow, and forwarded to process the next measurement. In the present case, the thin (120 μm) Si wafer sawing yields of ground and mirror-polished Si bricks are above 90% and 96%, respectively. In ground Si brick, surface defects are a cause of wafer breakage during the sawing process, and the sawing yield loss primarily
Fracture strength:σfrac ¼
3FL 2bh2
where F is the load at the point of wafer fracture, L is the distance be tween the two supporting bars (80 mm), b is the width of the sample wafer (156 mm), and h is the thickness of each sample wafer (120 μm). To evaluate strength distributions, a total of 120 wafers were bent up to the point of fracture. The DWS sawn wafer surface contains wire saw marks in the sawing direction (Fig. 3). Depending on the bending direction of the wire saw marks on the wafer surface, bare DWS Si wafers have asymmetry (bidirectional) in their fractural strengths, a lower strength in parallel bending, and a higher strength in perpendicular bending [18,19]. The explanation for the strength difference (asymmetry) is as follows. In parallel bending, the elongated surface cracks and surface pits are considered to be long scratch lines. Under this bending, both terrace and elongated surface cracks and pits directly fall under the loading axis [18]. When bending in this direction, all wafer fractures have approxi mately equal strengths [18]. In bending perpendicular to the wire saw marks, the surface and sub-surface damage (both terrace and pits) are considered as individual defects. In this bending, wafers are exposed to various fracture strengths, depending on their damage (surface, sub-surface and edge damage) states under the loading bar. The maximum (subsurface micro-cracks or edge cracks) damage caused by diamond wire leads the wafer to fracture in perpendicular bending. In the present study, the mechanical loads were applied perpendicular to the wire saw marks on the wafer surface. The wafer edges and cross-sections of fractured samples (shattered pieces from the middle of the wafers) were examined under a scanning electron microscope (SEM) (JCM-6000PLUS NeoScope Benchtop). 3
H. Sekhar et al.
Materials Science in Semiconductor Processing 105 (2020) 104751
distribution of fracture strengths. These fracture strengths are repre sented as X � Y MPa [18], where X is average fracture strength and Y is standard deviation. The fracture strength distributions of as-sawn g- Si wafers and p- Si wafers in perpendicular bending are shown in Fig. 4. The average fracture strengths and standard deviations are noted in Table 2. Two notable differences are observed from Fig. 4 and Table 2. The first dif ference indicated, for both g- Si wafers and p- Si wafers, is that the freshwire-side wafers have lower strength compared with the worn-wire-side wafers. The second difference indicated is that the g- Si wafers have lower strength compared with the p- Si wafers. The explanation for the first difference (lower strength on the freshwire-side compared with worn-wire-side wafers) is as follows. On the fresh-wire-side, the diamond abrasives have sharp tips; material chip ping with sharp tips generates deeper microscopic cracks inside the Si [18]. As sawing is under way, on the fresh-wire side the sharp tips of diamond particles participate in chipping the Si by simultaneous scratching and inducting, and the wire progresses to move inside the Si bricks. As time progresses, the sharp tips become blunt and the wire passes from the fresh to the worn side. The previous experimental results on indentation of Si with sharp tips (conical, Berkovich, and Vickers) leads the initiation of hemispherical plastic-zone and sub-surface cracks (lateral, median cracks) [20,21,28,29]. The lateral cracks seem to be parallel with the Si surface, and their depths are approximately equal to the plastic zone size. The median cracks go deeper into the bulk of the sample and their depths are equal to subsurface damage depth (SSD) [12,21]. The blunt tips, such as flat or spherical indenters, initiate only surface cracks at the ductile-to-brittle transition point. In diamond saw, the fresh-wire-side diamond particle sharp tips penetrate into the sur face and sub-surface layer of the plastic zone, and start to propagate as median cracks in the bulk. At the worn-wire side, the chipping with blunt diamond particles generates shallow surface and subsurface cracks. The damage to wafers cut from the worn-wire side might be less
Table 1 Surface roughness of ground and mirror-polished Si bricks. Si brick polishing type
Ground (g) brick Mirror-polished (p) brick
Arithmetic mean surface roughness Ra (μm) 1
2
3
4
Average
0.485 0.010
0.417 0.014
0.370 0.013
0.401 0.014
0.418 0.013
3. Results and discussion The arithmetic mean surface roughness (Ra) of ground and mirrorpolished Si bricks were measured at four different points in the middle of the bricks, and their average values are shown in Table 1. The average surface roughness (Ra) of ground Si bricks is 0.418 μm and that of mirrorpolished Si bricks is 0.013 μm. The improvements in Si brick surface conditions (mirror polishing) allow us to saw thin (120 μm) Si wafers with sawing yields of over 96%. The surface profile of a bare diamondwire-sawn thin Si wafer is shown in Fig. 3. The wafer surface contains a periodic pattern of wire saw marks in the form of terraces, pits, and surface cracks distributed along the wire-cutting direction [17–22]. In ductile chipping, an amorphous Si layer was manifested locally on the machined wafer surface in the form of terrace. The forward and back ward (cyclic) motion of the diamond wire abrasives was responsible for ploughing the amorphous layer, and the cause for the formation of pits on the machined wafer surface. The fracture strength is defined as the maximum energy needed for the wafer to resist breakage, or the maximum energy needed to separate the two atoms. In Si solar cell module fabrication, the wafer experiences large thermal and mechanical stresses on its surfaces and edges. If these stress fields exceed the wafer strength, a large number of wafers will break during the solar cell production-line process, strongly impacting the production costs and yields in industry. Therefore, it is very important to supply higher-fracture-strength thin Si wafers. It was reported that Si wafer fracture can arise from any of bulk, surface, or edge defects [11]. Crystal growth is the source of bulk de fects, which can be minimized by optimizing growth conditions. Me chanical sawing is the source of surface and edge defects, which can be minimized by using high-quality diamond wires, polishing the Si brick surface with ultra-low roughness, and optimizing wafer-sawing param eters by the trial and error method [16]. Si is an intrinsically brittle material and anisotropic in nature [27]. Depending upon the damage on their surface, subsurface, and edge regions, Si wafers are exposed to a
Table 2 Average fracture strengths and standard deviations of DWS g- Si wafers and p- Si wafers. Wafer type g- Si wafers p- Si wafers
Facture strength (MPa) (X � Y MPa) Fresh-wire-side
Worn-wire-side
195 � 16 312 � 18
235 � 18 336 � 24
Fig. 4. The fracture strength distributions of DWS thin (120 μm) g- Si wafers and p- Si wafers. 4
H. Sekhar et al.
Materials Science in Semiconductor Processing 105 (2020) 104751
(100 μm) Si wafers sawn from mirror-polished bricks (95 MPa) is little bit higher than that of conventional polished bricks (85 MPa) [16]. However, we found that the difference in strength between wafers cut from mirror-polished and ground bricks is substantially larger than re ported. This is because they processed wafers with free abrasive (silicon carbide, SiC) wire, whereas we processed them with fixed diamond abrasives. It is well known that in free abrasive cutting the material abrasion takes place in brittle mode, and cracks penetrate deeply up to several microns into the wafer. These deep micro-cracks dominate the wafer fracture and are responsible for the slight strength gap. However, in our results, we can clearly distinguish a large strength difference between DWS g- Si wafers and p- Si wafers, i.e. the subsurface micro-cracks are shallower. In mechanical cutting, the Si brick is fed towards the wire web, resulting in sharp, brittle chipping at the wire entrance and exit sides of the wafer edges. The sharp, brittle edges are considered to be a prime obstacle to progress in sawing thin Si wafers. To address the impact of wafer edge chipping on the fracture strengths of g-wafers and p-wafers, the edges are observed at three different places, denoted by (1), (2), and (3) in Fig. 5. The edge chipping at the wire entrance and exit in the Si bricks is termed as wire entrance side (1) and wire exit side (2), respectively, on the Si wafer. The edge chipping perpendicular to the direction of wire motion on the Si wafer is denoted by (3). The SEM images of g- Si wafer and p- Si wafer edge chipping profiles are shown in Figs. 6–8. Observing Figs. 6 and Fig. 7, we find two differences between the wire entrance (1) and wire exit (2) edges. The edge chipping heights and widths are higher at the wire exit side (2) (Figs. 6 (b–1) and Figs. 7 (b–1)) compared with those at the wire entrance side (1) (Figs. 6 (a–1) and Figs. 7 (a–1)). The wafer surface is left with high pit density (Figs. 6 (b–2) and Figs. 7 (b–2)) at the wire exit side (2) compared with the wire entrance side (1) (Figs. 6 (a–2) and Figs. 7 (a–2)). In g- Si wafers, the edge chipping heights at the wire entrance and wire exit sides are 12–14
Fig. 5. Diagram of diamond wire at the entrance and exit side in an Si brick, and schematic diagram of wafer edge chipping measurement.
than that to the wafers cut from the fresh-wire side because the worn-wire-side wafers were cut by blunt diamond particles. The wafer breakage strength strongly depends on the damage state in the wafer area under maximal stress. Therefore, the fresh-wire-side wafers have lower fracture strengths compared with the worn-wire-side wafers. The explanation for the second difference is as follows. The g- Si wafers (both fresh-wire side and worn-wire side) are fractured at a lower strength compared with the p- Si wafers. From the surface roughness measurement, the ground Si brick surface (roughness 0.418 μm) suffered higher damage than the mirror-polished Si brick surface (roughness 0.013 μm). In wafer sawing, the g- Si wafer edges carry excess damage from their parent Si brick, which is responsible for their lower fracture strength compared with the p- Si wafers. Normally, in thin wafers, a small difference in damage state (surface, sub-surface, or edge damage) has a strong impact on its wafer fracture strength. It can be seen in Fig. 4 that both g- Si wafers and p- Si wafers fracture at a variety (distribution) of strengths. The previous reports show that the fracture strength of thin
Fig. 6. SEM images of edge-chipping profiles on the fresh-wire-side g- Si wafer (a) at the wire entrance side (1) (a-1 edge cross-sectional view and a-2 edge surface), (b) at the wire exit side (2) (b-1 edge cross-sectional view and b-2 edge surface). 5
H. Sekhar et al.
Materials Science in Semiconductor Processing 105 (2020) 104751
Fig. 7. SEM images of edge-chipping profiles on fresh-wire-side p- Si wafer (a) at the wire entrance side (1) (a-1 edge cross-sectional view and a-2 edge surface), (b) at the wire exit side (2) (b-1 edge cross-sectional view and b-2 edge surface).
Fig. 8. (a) SEM images of edge-chipping profiles perpendicular to the direction of wire motion on the wafer surface (3) for (a) g- Si wafer, (b) p- Si wafer.
μm and 16–18 μm (Fig. 6(a and b)). In p- Si wafers, the edge chipping heights at the wire entrance and wire exit sides are 8–12 μm and 13–15 μm (Fig. 7(a and b)). In g- Si wafers, both sides of edge chipping are higher compared with those in p-wafers. The explanation for the higher chipping and number of pits at the wire exit side is as follows. The Si brick is attached to the supporting bar with glue, as shown in Fig. 9 (a). As sawing progresses, the wire ad vances in the Si brick by cutting material and the wire comes closer towards the brick edge, as shown in Fig. 9 (a), and the wire is ready to transfer from Si to glue. At this point, most of the Si brick is already cut into wafer form, only small parts of Si are left out and it needs to be sawn to grow as a full wafer. At this point, both the wire and the wafer suffer from small fluctuations in the form of vibrations, resulting in punches on each other. The punching causes diamond abrasives to induct the Si and plug the ductile phase (a-Si layer) from the wafer surface in the
Fig. 9. (a) Schematic of diamond wire (DW) at the exit side of an Si brick. (b) Schematic diagram of wafer edge-chipping profile in <1 0 0> crystal orienta tion in thin Si wafers.
6
H. Sekhar et al.
Materials Science in Semiconductor Processing 105 (2020) 104751
Fig. 10. The cross-sectional cleavages of broken samples from the middle of g-wafers at different strengths: (a) 132 MPa, (b) 185 MPa, (c) 218 MPa, (d) 267 MPa.
scratching. This gives the wafer surface a high pit density at the wire exit side compared with the wire entrance side. There is significant scope to increase fracture strengths and sawing yields further by redefining the process parameters (wire speed, brick feed rates, and tension on the wire) at the wire exit side. The edge-chipping profiles of the g- Si wafer and p- Si wafer perpendicular to the direction of wire motion (3) are shown in Fig. 9. In both wafers the chipping heights are approximately 2–5 μm. Under perpendicular bending, the wafer experiences a negli gible stress at position (3) as shown in Fig. 2(c). This may not have a strong impact on its wafer fracture. In thin Si wafers, the edge-chipping profiles and chipping mecha nisms are not well understood. In the present study, we attempted to improve the understanding of edge-chipping profiles and chipping mechanisms by considering crystallographic orientation, as shown in Fig. 9 (b). The elucidation for edge-chipping profiles is as follows. Thin wafer crystal orientations and cleavage planes are considered to be dominant to decide edge-chipping shapes. The Si is a diamond lattice cubic structure followed by three {100}, {110}, and {111} crystalline planes. The angle between the <1 0 0> and <1 1 0> crystal orientations is 45� , and the {111} plane is the lowest energy cleavage plane with the smallest binding force [7]. In previous reports on the application of IC packaging, involving the grinding of thick (100) Si wafers to thin wafers, cracks are preferentially developed in its {111} cleavage planes. Edge chipping typically starts and propagates along the <1 1 0> crystal orientation on the {111} planes, and the edge chipping profile becomes an isosceles right triangle in the <1 0 0> crystal orientation [7]. In thin (100) Si wafer sawing, the Si brick is forced towards the wire web, which allows the cracks to initiate on the lower energy cleavage plane {111}, propagate in <1 1 0> crystal orientation, and chip the Si in brittle mode as shown in Fig. 9 (b) [7]. From Figs. 6 (a–1 and a-2) and Figs. 7 (a–1 and a-2), it is clear that thin Si wafer edges becomes sharp and cracks are
initiated on the low energy cleavage plane {111}, and chips in the <110> crystal direction [7]. As the wire starts to move into the Si brick by scratching and indenting of diamond particles, the ductile chipping becomes real. To understand the wafer fracture mechanism in the three-line bending test, the broken samples under the loading bar were analyzed with a fractographic method of electron microscopy. Normally, the cross-sections of fractured samples hold valuable information on how the damages (cracks) are responsible for opening the material. Because of the anisotropic nature of Si, the {1 1 1} and {1 1 0} crystal planes are considered to have lower toughness. In this sense, crystal low energy cleavage ({1 1 1} and {1 1 0}) planes are the dominant areas to fracture the Si (1 0 0) in the <1 1 0 > crystal direction [27,30,31]. Previous experiments on three-line bending of c-Si (1 0 0) samples with various pre-crack lengths on its surface exhibited fractures of various (low- kinetic-energy (mirror) and high-kinetic-energy (mirror-mist, mist, hackle, and branching)) mechanisms [32–38]. In the three-line bending experiment, under continuous loading, the wafer experienced a compressive stress on its front surface and a tensile stress on its back surface, and the applied stress accumulated as strain energy at the crack. Under loading, the wafer sustained up to a certain load by bending and then, when the load exceeded the wafer strength, cracks started to propagate by releasing strain energy in this direction, and opened the material by fracturing the wafer. To understand the fracture mechanism in g-wafers and p-wafers, the lower and higher fracture strength samples (from the middle of the wafer) had their cross-sections recorded and shown in Fig. 10 and Fig. 11. In Fig. 10 (a), the lower-strength (132 MPa) fractured sample followed the mirror mechanism. In mirror fracture, sample crosssections seem to be atomically smooth or mirror-like, with little or no surface perturbations [32–34]. The cracks propagate in a stable manner, 7
H. Sekhar et al.
Materials Science in Semiconductor Processing 105 (2020) 104751
Fig. 11. The cross-sectional cleavages of broken samples from the middle of p-wafers at different strengths: (a) 312 MPa, (b) 364 MPa.
and the fracture follows the low-kinetic-energy mechanism. In this case the wafer fractured into a few large pieces [19]. The wafers that fractured at intermediate strengths (185, 218, and 267 MPa) are shown in Fig. 10(b) and (c), and (d). The fractured sample cross-sectional surface accommodates fluctuations on its mirror surface. The cracks propagate at an unstable manner that leads to surface perturbation in this direction, and the fracture follows the high-kineticenergy mechanism. In this case, the wafer fracture follows the mirrormist and hackle mechanisms. The wafers that fractured at higher strengths are shown in Fig. 11(a) and (b). In this case, the overgrowing stress on the wafer surface results in bifurcation. In Fig. 11 (b), one can clearly see crack branching (bifurcation) taking place, and cracks follow longer paths and propagate less stably in a tortuous way, from the top surface to the bottom surface and vice versa. Therefore, the samples of wafers that fractured at higher strengths have more complex crosssectional surface morphologies. In this fracture, the wafers are made to fracture into many tiny pieces. From Figs. 10 and 11, we conclude that as the wafer strength increases, the cross-sectional surface perturbations of the fractured samples gradually increases and the cracks follow more complex paths. From fractographic studies we can conclude that the wafers that fracture at lower strengths have deeper damage caused by the mirror-fracture mechanism. The wafers that fracture at higher strength have shallow damages caused by the mirror-mist, hackle, and branching fracture mechanisms.
Appendix A. Supplementary data Supplementary data to this article can be found online at https://doi. org/10.1016/j.mssp.2019.104751. References [1] G.-S. Jeong, W. Bae, D.-K. Jeong, Review of CMOS integrated circuit technologies for high-speed photo-detection, Sensors 17 (2017) 1962. https://www.ncbi.nlm. nih.gov/pmc/articles/PMC5620527/. [2] International Technology Roadmap for Photovoltaics (ITRPV), 9th ed. (2018) and 10th ed, 2019. https://itrpv.vdma.org/. [3] K. Yamamoto, K. Yoshikawa, H. Uzu, D. Adachi, High-efficiency heterojunction crystalline Si solar cells, Jpn. J. Appl. Phys. 57 (1–8) (2018) 08RB20. https://iopsc ience.iop.org/article/10.7567/JJAP.57.08RB20/meta. [4] J. Walters, K. Sunder, O. Anspach, R.P. Brooker, H. Seigneur, Challenges associated with diamond wire sawing when generating reduced thickness mono-crystalline silicon wafers, IEEE Photovolt. Spec. Conf. (2016) 0724–0728. https://ieeexplore. ieee.org/document/7749697. [5] S. Wieghold, A.E. Morishige, L. Meyer, T. Buonassisi, E.M. Sachs, Crack detection in crystalline silicon solar cells using dark-field imaging, Energy Procedia 124 (2017) 526–531. https://www.sciencedirect.com/science/article/pii/S1876610 217341838. [6] T.S. Liang, M. Pravettoni, C. Deline, J.S. Stein, R. Kopecek, J.P. Singh, W. Luo, Y. Wang, A.G. Aberle, Y.S. Khoo, A review of crystalline silicon bifacial photovoltaic performance characterisation and simulation, Energy Environ. Sci. 12 (2019) 116–148. https://pubs.rsc.org/en/content/articlelandi ng/2019/ee/c8ee02184h#!divAbstract. [7] S. Gao, R. Kang, Z. Dong, B. Zhang, Edge chipping of silicon wafers in diamond grinding, Int. J. Mach. Tool Manuf. 64 (2013) 31–37. https://www.sciencedirect. com/science/article/pii/S0890695512001587. [8] M. Li, Y. Dai, W. Ma, B. Yang, Q. Chu, Review of new technology for preparing crystalline silicon solar cell materials by metallurgical method, IOP Conf. Ser. Earth Environ. Sci. 94 (1–11) (2017) 012016. https://iopscience.iop.org/article/ 10.1088/1755-1315/94/1/012016. [9] W.F. Struth, K. Steffens, W. Konig, Wafer slicing by internal diameter sawing, Precis. Eng. 10 (1988) 29–34. https://www.sciencedirect.com/science/article/pii/ 014163598890092X. [10] Z.J. Pei, G.R. Fisher, J. Liu, Grinding of silicon wafers: a review from historical perspectives, Int. J. Mach. Tool Manuf. 48 (2008) 1297–1307. https://www.scienc edirect.com/science/article/pii/S0890695508001089. [11] G. Fisher, M.R. Seacrist, R.W. Standley, Silicon crystal growth and wafer technologies, Proc. IEEE 100 (2012) 1454–1474. https://ieeexplore.ieee.org/do cument/6178756. [12] X. Li, Y. Gao, P. Ge, L. Zhang, W. Bi, The effect of cut depth and distribution for abrasives on wafer surface morphology in diamond wire sawing of PV polycrystalline silicon, Mater. Sci. Semicond. Process. 91 (2019) 316–326. https:// www.sciencedirect.com/science/article/pii/S1369800118312046. [13] A. Bidiville, K. Wasmer, J. Michler, P.M. Nasch, M. Van der Meer, C. Ballif, Mechanisms of wafer sawing and impact on wafer properties, Prog. Photovoltaics 18 (2010) 563–572. https://onlinelibrary.wiley.com/doi/full/10.1002/pip.972. [14] J.D. Gates, Two-body and three-body abrasion: a critical discussion, Wear 214 (1998) 139–146. https://www.sciencedirect.com/science/article/pii/S0043164 897001889. [15] H. Wu, Wire sawing technology: a state-of-the-art review, Precis. Eng. 43 (2016) 1. https://www.sciencedirect.com/science/article/pii/S0141635915001531. [16] S. Choi, B. Jang, J. Kim, H. Song, T. Baek, M. Han, Effects of mirror polishing brick surface on process yield of multi-wire slicing for thin single-crystalline silicon solar cells, Sol. Energy 122 (2015) 1170–1179. https://www.sciencedirect.com/science/ article/pii/S0038092X15005733. [17] H. Sekhar, T. Fukuda, K. Tanahashi, K. Shirasawa, H. Takato, K. Ohkubo, H. Ono, Y. Sampei, T. Kobayashi, The impact of subsurface damage on the fracture strength of diamond-wire-sawn monocrystalline silicon wafers, Jpn. J. Appl. Phys. 57
4. Conclusions The goal of this paper is to bring some insight into the cutting of thin Si wafers using thin diamond wires to fulfill the objectives of the ITRPV 2018–2029 road map. The breakage of thin Si wafers during manufacturing is an important issue and has a strong impact on its production yields and costs. The diamond wire quality and Si brick polishing are the deciding factors in thin (120 μm) Si wafer-slicing yields and fracture strengths. The ground (g) and mirror-polished (p) Si bricks are sawn into thin (120 μm) silicon (Si) wafers. The higher damage on gwafer edges is responsible for their lower sawing yields (>90%) and lower fracture strengths. By polishing an Si brick with ultra-low surface roughness (mirror polish), we achieved higher sawing yields (>96%) and higher fracture strengths in thin Si wafers. There is still room to improve the sawing yields and fracture strengths by controlling both wire and wafer dynamics at the wire exit in between the Si brick and the glue. Depending on the wafer damage (surface, subsurface, and edge) state, wafers are made to fracture via low- or high-energy mechanisms. Acknowledgment The authors thank Noritake Co., Ltd. for supporting the experiment and helping us to receive a large amount of diamond wire for this study.
8
H. Sekhar et al.
[18]
[19]
[20] [21]
[22]
[23]
[24] [25]
[26]
[27]
Materials Science in Semiconductor Processing 105 (2020) 104751
(2018) 08RB08. https://iopscience.iop.org/article/10.7567/JJAP.57.08RB08/met a. H. Sekhar, T. Fukuda, K. Tanahashi, K. Shirasawa, H. Takato, K. Ohkubo, H. Ono, Y. Sampei, T. Kobayashi, The impact of saw mark direction on the fracture strength of thin (120 μm) monocrystalline silicon wafers for photovoltaic cells, Jpn. J. Appl. Phys. 57 (2018) 095501. https://iopscience.iop.org/article/10.7567/JJAP.57.09 5501/meta. H. Sekhar, T. Fukuda, K. Tanahashi, H. Takato, The impact of damage etching on fracture strength of diamond wire sawn monocrystalline silicon wafers for photovoltaics use, Jpn. J. Appl. Phys. 57 (2018) 126501. https://iopscience.iop. org/article/10.7567/JJAP.57.126501/meta. A.M. Kovalchenko, YuV. Milman, On the cracks self-healing mechanism at ductile mode cutting of silicon, Tribol. Int. 80 (2014) 166–171. https://www.sciencedirec t.com/science/article/pii/S0301679X14002618. T. Liu, P. Ge, W. Bi, Y. Gao, Subsurface crack damage in silicon wafers induced by resin bonded diamond wire sawing, Mater. Sci. Semicond. Process. 57 (2017) 147–156. https://www.sciencedirect.com/science/article/pii/S136980011630 4383. J. Yan, T. Asami, H. Harada, T. Kuriyagawa, Fundamental investigation of subsurface damage in single crystalline silicon caused by diamond machining, Precis. Eng. 33 (2009) 378–386. https://www.sciencedirect.com/science/article/ pii/S0141635908001530. Y. Chiba, Y. Tani, T. Enomoto, H. Sato, Development of a high-speed manufacturing method for electroplated diamond wire tools, CIRP Annals 52 (2003) 281–284. https://www.sciencedirect.com/science/article/pii/S000785060 7605848. Y. Gao, P. Ge, T. Liu, Experiment study on electroplated diamond wire saw slicing single- crystal silicon, Mater. Sci. Semicond. Process. 56 (2016) 106–114. https:// www.sciencedirect.com/science/article/pii/S1369800116302499. U. Pala, S. Sussmaier, F. Kuster, K. Wegener, Experimental investigation of tool wear in electroplated diamond wire sawing of silicon, Procedia CIRP 77 (2018) 371–374. https://www.sciencedirect.com/science/article/pii/S2212827 118311946. A. Kumar, S.N. Melkote, Diamond wire sawing of solar silicon wafers: a sustainable manufacturing alternative to loose abrasive slurry sawing, Procedia Manuf. 21 (2018) 549–566. https://www.sciencedirect.com/science/article/pii/S2351978 918301963. T. Vodenitcharova, O. Borrero-L� opez, M. Hoffman, Mechanics prediction of the fracture pattern on scratching wafers of single crystal silicon, Acta Mater. 60
[28]
[29] [30] [31]
[32] [33] [34] [35]
[36] [37] [38]
9
(2012) 4448–4460. https://www.sciencedirect.com/science/article/pii/S1359645 412002960. M. Ge, H. Zhu, C. Huang, A. Liu, W. Bi, Investigation on critical crack-free cutting depth for single crystal silicon slicing with fixed abrasive wire saw based on the scratching machining experiments, Mater. Sci. Semicond. Process. 74 (2018) 261–266. https://www.sciencedirect.com/science/article/pii/S1369800 117316335. Z.J. Pei, S.R. Billingsley, S. Miura, Grinding induced subsurface cracks in silicon wafers, Int. J. Mach. Tool Manuf. 39 (1999) 1103–1116. https://www.sciencedirec t.com/science/article/pii/S0890695598000790. R. P� erez, P. Gumbsch, Directional anisotropy in the cleavage fracture of silicon, Phys. Rev. Lett. 84 (2000) 5347–5350. https://journals.aps.org/prl/abstract/ 10.1103/PhysRevLett.84.5347. C. Klute, F. Kaule, S. Schoenfelder, Breakage Root Cause Analysis in As-Cut Monocrystalline Silicon Wafers, 29th European Photovoltaic Solar Energy Conference and Exhibition, 2014, pp. 753–756, in: https://www.eupvsec-proceed ings.com/proceedings?paper¼29589. D. Sherman, Aspects of rapid crack propagation in silicon, Fatigue Fract. Eng. Mater. Struct. 30 (2006) 32–40. https://onlinelibrary.wiley.com/doi/full/10. 1111/j.1460-2695.2006.01054.x. D. Sherman, I. Be’ery, Dislocations deflect and perturb dynamically propagating cracks, Phys. Rev. Lett. 93 (2004) 265501. https://journals.aps.org/prl/abstract/ 10.1103/PhysRevLett.93.265501. D. Sherman, Energy considerations in crack deflection phenomenon in single crystal silicon, Int. J. Fract. 140 (2006) 125–140. https://link.springer.com/article /10.1007/s10704-006-0048-9. D. Sherman, I. Be’ery, From crack defection to lattice vibrations-macro to atomistic examination of dynamic cleavage fracture, J. Mech. Phys. Solids 52 (2004) 1743–1761. https://www.sciencedirect.com/science/article/pii/S00225 09604000286?via%3Dihub. D. Sherman, Hackle or textured mirror? Analysis of surface perturbation in single crystal silicon, J. Mater. Sci. 00 (2003) 1–6. https://link.springer.com/article/10.1 023/A:1021809014702. D. Sherman, Fractography of dynamic crack propagation in silicon crystal, Key Eng. Mater. 409 (2009) 55–64. https://www.scientific.net/KEM.409.55. M. Wang, L. Zhao, M. Fourmeau, D. Nelias, Crack plane deflection and shear wave effects in the dynamic fracture of silicon single crystal, J. Mech. Phys. Solids 122 (2019) 472–488. https://www.sciencedirect.com/science/article/pii/S0022509 618305866.
Contents lists available at ScienceDirect
Materials Science in Semiconductor Processing journal homepage: http://www.elsevier.com/locate/mssp
The impact of silicon brick polishing on thin (120 μm) silicon wafer sawing yields and fracture strengths in diamond-wire sawing Halubai Sekhar *, Tetsuo Fukuda **, Katsuto Tanahashi, Hidetaka Takato Renewable Energy Research Center, Fukushima Renewable Energy Institute (FREA), National Institute of Advanced Industrial Science and Technology (AIST), 2-2-9 Machi-ikedai, Koriyama, Fukushima, 963-0298, Japan
A R T I C L E I N F O
A B S T R A C T
Keywords: Silicon bricks Diamond wires Three-line bending Wafer fracture strength Ground brick Mirror-polished brick
The present study recommends sawing thin (120 μm) silicon (Si) wafers using thin (120 μm) diamond wire with higher throughputs and sawing yields (>96%). In a multi-wire saw, an improved type of diamond wire (100 d/ M6-12) is employed to saw ground (g) and mirror-polished (p) Si bricks into thin (120 μm) Si wafers. Im provements in both diamond wire and Si brick surface allow us to saw thin (120 μm) Si wafers with higher fracture strengths and sawing yields of over 96%. The wafers sawn from g and p Si bricks are labeled as g- Si wafers and p- Si wafers. Depending on wire wear position, sawn wafers are labeled as fresh-wire and worn-wire sides. In a three-line bending test, mechanical loads were applied perpendicular to the wire saw marks on the middle of each wafer to measure its fracture strength. Two fundamental differences are observed in the fracture strengths of g- and p- Si wafers. The g- Si wafers fractured at lower strengths compared with the p- Si wafers. Both g- and p- Si wafers from the fresh-wire side fractured at lower strengths compared with worn-wire-side wafers. To address the fracture strength difference, edge chipping and fractographic studies were carried out. The wafer edges were observed at wire entrance and wire exit sides in the Si brick. At the wire exit side, the wafer surface contains a large number of pits followed by longer chipping lengths and widths compared with the wire entrance side. The fractographic studies were performed on fractured samples collected from the middle of the wafer by observing its cross-sections. The wafers fractured at low-strength samples follow mirror mechanisms, and the wafers fractured at intermediate- and higher-strength samples follow any one of mirror–mist, mist, hackle, branching or a mixture of these mechanisms.
1. Introduction In the semiconductor industry, silicon (Si) is an essential material for the applications of integrated circuits and photovoltaic cells [1–8]. First-generation wafer-based crystalline and multi-crystalline Si (c-Si and mc-Si) solar cells possess an overwhelming market share of above 90% because of their excellent device performance and longer lifetimes [2]. To manufacture Si wafers for application in photovoltaics (PVs), the following pre- and post-processing steps are required: grow high-quality Si crystal, crop the crystal into a brick shape, grind, polish, saw wafers, and etch out saw damage [8–10]. Currently, state-of-the-art c-Si wafers, with a thickness of 180–170 μm, are used in the industry to produce solar cells. The Si wafer itself constitutes approximately 52% of the module price [2,4]. Thus, there is ample space to minimize the cost by minimizing the bulk material in the form of thin wafers. It is
recommended to saw a greater number of wafers from a given amount of raw material by lowering the Si wafer thickness and its kerf. Because of the intrinsic brittle nature of Si, sawing thinner wafers leads to higher breakage, nullifying the gain made by lower material consumption (thin wafer), so a special way is needed to overcome the breakage problem [4]. During the period 2018–2029, the international technology road map for photovoltaic (ITRPV) predicts that sawn wafer thickness will decrease from 180 to 130 μm for c-Si, and to 150 μm for mc-Si [2]. In this introduction we primarily discuss various technologies to saw Si bricks into wafers, and the feasibility to adopt each one for mass-scale production. It has been reported that the Si bricks are sawn into wafers in two ways: internal diameter (ID) saw, and multi-wire saw [2,9–11]. In an ID saw, nickel-bonded diamond grits are coated on a thin annular blade that is used to cut the wafers. It cuts only one wafer at a time and therefore consumes more time to process the whole Si brick into wafers.
* Corresponding author. ** Corresponding author. E-mail addresses: [email protected], [email protected] (H. Sekhar), [email protected] (T. Fukuda). https://doi.org/10.1016/j.mssp.2019.104751 Received 9 June 2019; Received in revised form 29 August 2019; Accepted 22 September 2019 1369-8001/© 2019 Published by Elsevier Ltd.
H. Sekhar et al.
Materials Science in Semiconductor Processing 105 (2020) 104751
Fig. 1. (a) SEM image of a developed diamond wire 100 d/M6-12. (b) Ground (g) Si brick. (c) Mirror-polished Si brick.
It is not economically viable for an ID saw to meet industrial needs or perform well in cost competition because of its low productivity and cutting yields [11]. To address these issues in the industry, multi-wire sawing technology has been introduced. In this, wires are wrapped on the guiding roller which run parallel to each other with a constant pitch. It allows the entire Si brick to be processed into wafers at once, which makes it economically feasible to scale up to larger volumes [11]. In the last few decades, the advantages provided by multi-wire sawing tech nology have been inspiring the industry to cut Si bricks into wafers in this way [2]. In multi-wire sawing, hard, abrasive particles are used to abrade the Si brick into the form of wafers. Depending upon the abrasives on the wire, multi-wire sawing is categorized into two types: loose-abrasive (slurry) and fixed-abrasive (diamond) wire. The material abrasion mechanism in loose-abrasive and fixed-abrasive wires is different [12–14]. In slurry wire sawing, the wire moves forward and exerts force on the abrasive particles (SiC particles with irregular shape) allows to roles between the wire and the brick and induct the Si brick. In slurry
cutting, the material abrasion occurs in brittle mode finished by three-body wear, and deforms the Si brick into the form of wafers. In the abrasion, the wire loses its strength through the indentation of sharp abrasive particles on the wire [13–16]. For each new cutting, both the wire and abrasives need to be replaced, which has an impact on pro duction costs. In this cutting, thin Si wafer sawing yields were improved by polishing (by conventional and mirror polishing) Si bricks [16]. Conventional polishing of Si bricks allows the sawing of Si wafers with thicknesses of 120 μm and 100 μm, with sawing yields of 71% and 60%, respectively. Mirror polishing allows the sawing of Si wafers with thicknesses of 120 μm and 100 μm, with sawing yields of 80% and 83.6%, respectively [16]. In this cutting, micro-cracks are randomly distributed on the wafer surface and propagated over several tens of microns inside the bulk material [15,16], which limits progress on thinner wafers by yield loss. In diamond-wire sawing (DWS), the abrasive particles are attached to a steel wire surface by resin bonding or electroplating techniques. In DWS, the wire moves in forward and backward (cyclic) motion and
Fig. 2. (a) Schematic of multi-wire diamond saw. (b) As-sawn Si wafers (120 μm) stuck to a supporting substrate. (c) Schematics of three-line bending tester [17,18]. 2
H. Sekhar et al.
Materials Science in Semiconductor Processing 105 (2020) 104751
scratches the Si surface by indentation, which excites the Si surface layers in different phases (ductile mode) [17–22]. The material chipping (flaking) in ductile mode allows a decrease in subsurface micro-cracks, which encourages progress toward lower wafer thickness with higher yields than before. In this cutting, material abrasion finished by two-body wear, which involves the direct interaction of the diamond abrasives with the Si brick [23]. In physical sawing, the high-speed sliding contacts of diamond abrasives on Si brick generates huge pres sure on both. As a result, there is a high probability that resin-bonded diamond grits easily attract wear and tear compared with electro plated diamond grits [23–25]. To cut Si materials during the period 2018–2029, ITRPV predicts that electroplated diamond wire will dominate with a higher market share (90%) compared with resin-bonded diamond wire [2]. It also reports that the growth in sawing c-Si and mc-Si wafers using diamond wires is going to see it occupy a market share of over 90% by 2022 [2]. In DWS, wire and Si brick feed speeds are relatively high, which allows higher cutting speeds (three times faster), with higher efficiencies, lower processing time, lower power consumption, and less wearing down of the core metal wire [26]. To achieve the objectives of the ITRPV road map for the years 2018–2029, the present study provides an opportunity to progress on thin (120 μm) Si wafer sawing using thin diamond wire, particularly as sawn thin Si wafers have higher fracture strengths with sawing yields above 96%.
Fig. 3. Surface profile of DWS Si wafer surface.
comes from fresh-wire-side wafer breakage. To measure the fracture strength of Si sawn wafers, we employed a simple uniaxial three-line bending test performed using a Shimadzu Autograph AG-X plus tester [17,18]. In our bending test, the loads were applied on the middle of the wafer to generate the maximum peak stress under a loading axis (Fig. 2 (c)) on the wafer surface, and minimum negligible stress on both wafer edges parallel to the loading bar [18,19]. The wafer sat on two supporting line bars. A variable mechanical load was attached to the third line bar. In Fig. 2 (c), the loads are shown as red arrows and are operated from an automated computer-controlled pro gram, and the loads were applied with an incremental speed of 3 mm/min onto the middle of the wafer. By measuring the load at the moment of wafer fracture, we were able to calculate and statistically analyze the wafer fracture strength using the following equation [18, 19]:
2. Experimental conditions With a precise control on the electroplating technique, the diamond particles are attached on the wire with less agglomeration and higher dispersion, as shown in Fig. 1 (a). The wire is known as improved dia mond wire, labeled 100 d/M6-12, where diamond particles (diameter 6–12 μm) are attached to the core steel wire (diameter 100 μm) with the help of metal particles as a coating layer. To address the impact of the Si brick surface condition on its wafer fracture strengths in DWS, the Si bricks are ground and mirror polished, as shown in Fig. 1(b) and (c). The surface roughness of Si bricks is measured using Surftest SJ-310 (Mitu toyo). Thin wafer sawings are performed under commercial multi-wire saw for large-scale production machines, a rough schematic of which is shown in Fig. 2 (a). By employing improved diamond wire, both ground and mirror-polished Si brick saw separately into wafers. Here inafter we refer to the wafers sawn from ground Si brick as g- Si wafers, and to those from mirror-polished Si brick as p- Si wafers. The diamond wire (length ~25 km) is wrapped onto the wire spool and labeled as new wire spool, and it feeds the diamond wire into the wire web. In the wire web, the wire passes from the grooves of equidistant pitch (240 μm) onto the guiding roller, where the wire lengths run parallel to each other as shown in the schematic in Fig. 2 (a). The Si brick is attached with glue onto the support bar. The brick sawing parameters are as follows [17, 18]. The tension on the wire is 19 N. The wire speed is 1000 m/min. The wire moves in forward and backward motion with a cyclic moment of 2 min/c. The mono c-Si brick with a pseudo-square cross-section of 156 � 156 mm2 feeds towards the wire web with a speed of 0.53 mm/min. The used wire is collected from a worn wires pool on the other side. The used wire length per wafer is 2–4 m. As the sawing progresses, the scratching and indenting of the abrasives removes the material in the form of wafers from the workpiece. The mono c-Si bricks are sawn into thin (120 μm) Si wafers stuck to a supporting substrate as shown in Fig. 2 (b). Depending on the wire wear position on the Si brick, the sawn wafers are labeled as either fresh-wire (diamond wire entrance) side or worn-wire (diamond wire exit) side wafers. The wafers are separated manually, cleaned with soapy water, rinsed under distilled water, dried with nitrogen flow, and forwarded to process the next measurement. In the present case, the thin (120 μm) Si wafer sawing yields of ground and mirror-polished Si bricks are above 90% and 96%, respectively. In ground Si brick, surface defects are a cause of wafer breakage during the sawing process, and the sawing yield loss primarily
Fracture strength:σfrac ¼
3FL 2bh2
where F is the load at the point of wafer fracture, L is the distance be tween the two supporting bars (80 mm), b is the width of the sample wafer (156 mm), and h is the thickness of each sample wafer (120 μm). To evaluate strength distributions, a total of 120 wafers were bent up to the point of fracture. The DWS sawn wafer surface contains wire saw marks in the sawing direction (Fig. 3). Depending on the bending direction of the wire saw marks on the wafer surface, bare DWS Si wafers have asymmetry (bidirectional) in their fractural strengths, a lower strength in parallel bending, and a higher strength in perpendicular bending [18,19]. The explanation for the strength difference (asymmetry) is as follows. In parallel bending, the elongated surface cracks and surface pits are considered to be long scratch lines. Under this bending, both terrace and elongated surface cracks and pits directly fall under the loading axis [18]. When bending in this direction, all wafer fractures have approxi mately equal strengths [18]. In bending perpendicular to the wire saw marks, the surface and sub-surface damage (both terrace and pits) are considered as individual defects. In this bending, wafers are exposed to various fracture strengths, depending on their damage (surface, sub-surface and edge damage) states under the loading bar. The maximum (subsurface micro-cracks or edge cracks) damage caused by diamond wire leads the wafer to fracture in perpendicular bending. In the present study, the mechanical loads were applied perpendicular to the wire saw marks on the wafer surface. The wafer edges and cross-sections of fractured samples (shattered pieces from the middle of the wafers) were examined under a scanning electron microscope (SEM) (JCM-6000PLUS NeoScope Benchtop). 3
H. Sekhar et al.
Materials Science in Semiconductor Processing 105 (2020) 104751
distribution of fracture strengths. These fracture strengths are repre sented as X � Y MPa [18], where X is average fracture strength and Y is standard deviation. The fracture strength distributions of as-sawn g- Si wafers and p- Si wafers in perpendicular bending are shown in Fig. 4. The average fracture strengths and standard deviations are noted in Table 2. Two notable differences are observed from Fig. 4 and Table 2. The first dif ference indicated, for both g- Si wafers and p- Si wafers, is that the freshwire-side wafers have lower strength compared with the worn-wire-side wafers. The second difference indicated is that the g- Si wafers have lower strength compared with the p- Si wafers. The explanation for the first difference (lower strength on the freshwire-side compared with worn-wire-side wafers) is as follows. On the fresh-wire-side, the diamond abrasives have sharp tips; material chip ping with sharp tips generates deeper microscopic cracks inside the Si [18]. As sawing is under way, on the fresh-wire side the sharp tips of diamond particles participate in chipping the Si by simultaneous scratching and inducting, and the wire progresses to move inside the Si bricks. As time progresses, the sharp tips become blunt and the wire passes from the fresh to the worn side. The previous experimental results on indentation of Si with sharp tips (conical, Berkovich, and Vickers) leads the initiation of hemispherical plastic-zone and sub-surface cracks (lateral, median cracks) [20,21,28,29]. The lateral cracks seem to be parallel with the Si surface, and their depths are approximately equal to the plastic zone size. The median cracks go deeper into the bulk of the sample and their depths are equal to subsurface damage depth (SSD) [12,21]. The blunt tips, such as flat or spherical indenters, initiate only surface cracks at the ductile-to-brittle transition point. In diamond saw, the fresh-wire-side diamond particle sharp tips penetrate into the sur face and sub-surface layer of the plastic zone, and start to propagate as median cracks in the bulk. At the worn-wire side, the chipping with blunt diamond particles generates shallow surface and subsurface cracks. The damage to wafers cut from the worn-wire side might be less
Table 1 Surface roughness of ground and mirror-polished Si bricks. Si brick polishing type
Ground (g) brick Mirror-polished (p) brick
Arithmetic mean surface roughness Ra (μm) 1
2
3
4
Average
0.485 0.010
0.417 0.014
0.370 0.013
0.401 0.014
0.418 0.013
3. Results and discussion The arithmetic mean surface roughness (Ra) of ground and mirrorpolished Si bricks were measured at four different points in the middle of the bricks, and their average values are shown in Table 1. The average surface roughness (Ra) of ground Si bricks is 0.418 μm and that of mirrorpolished Si bricks is 0.013 μm. The improvements in Si brick surface conditions (mirror polishing) allow us to saw thin (120 μm) Si wafers with sawing yields of over 96%. The surface profile of a bare diamondwire-sawn thin Si wafer is shown in Fig. 3. The wafer surface contains a periodic pattern of wire saw marks in the form of terraces, pits, and surface cracks distributed along the wire-cutting direction [17–22]. In ductile chipping, an amorphous Si layer was manifested locally on the machined wafer surface in the form of terrace. The forward and back ward (cyclic) motion of the diamond wire abrasives was responsible for ploughing the amorphous layer, and the cause for the formation of pits on the machined wafer surface. The fracture strength is defined as the maximum energy needed for the wafer to resist breakage, or the maximum energy needed to separate the two atoms. In Si solar cell module fabrication, the wafer experiences large thermal and mechanical stresses on its surfaces and edges. If these stress fields exceed the wafer strength, a large number of wafers will break during the solar cell production-line process, strongly impacting the production costs and yields in industry. Therefore, it is very important to supply higher-fracture-strength thin Si wafers. It was reported that Si wafer fracture can arise from any of bulk, surface, or edge defects [11]. Crystal growth is the source of bulk de fects, which can be minimized by optimizing growth conditions. Me chanical sawing is the source of surface and edge defects, which can be minimized by using high-quality diamond wires, polishing the Si brick surface with ultra-low roughness, and optimizing wafer-sawing param eters by the trial and error method [16]. Si is an intrinsically brittle material and anisotropic in nature [27]. Depending upon the damage on their surface, subsurface, and edge regions, Si wafers are exposed to a
Table 2 Average fracture strengths and standard deviations of DWS g- Si wafers and p- Si wafers. Wafer type g- Si wafers p- Si wafers
Facture strength (MPa) (X � Y MPa) Fresh-wire-side
Worn-wire-side
195 � 16 312 � 18
235 � 18 336 � 24
Fig. 4. The fracture strength distributions of DWS thin (120 μm) g- Si wafers and p- Si wafers. 4
H. Sekhar et al.
Materials Science in Semiconductor Processing 105 (2020) 104751
(100 μm) Si wafers sawn from mirror-polished bricks (95 MPa) is little bit higher than that of conventional polished bricks (85 MPa) [16]. However, we found that the difference in strength between wafers cut from mirror-polished and ground bricks is substantially larger than re ported. This is because they processed wafers with free abrasive (silicon carbide, SiC) wire, whereas we processed them with fixed diamond abrasives. It is well known that in free abrasive cutting the material abrasion takes place in brittle mode, and cracks penetrate deeply up to several microns into the wafer. These deep micro-cracks dominate the wafer fracture and are responsible for the slight strength gap. However, in our results, we can clearly distinguish a large strength difference between DWS g- Si wafers and p- Si wafers, i.e. the subsurface micro-cracks are shallower. In mechanical cutting, the Si brick is fed towards the wire web, resulting in sharp, brittle chipping at the wire entrance and exit sides of the wafer edges. The sharp, brittle edges are considered to be a prime obstacle to progress in sawing thin Si wafers. To address the impact of wafer edge chipping on the fracture strengths of g-wafers and p-wafers, the edges are observed at three different places, denoted by (1), (2), and (3) in Fig. 5. The edge chipping at the wire entrance and exit in the Si bricks is termed as wire entrance side (1) and wire exit side (2), respectively, on the Si wafer. The edge chipping perpendicular to the direction of wire motion on the Si wafer is denoted by (3). The SEM images of g- Si wafer and p- Si wafer edge chipping profiles are shown in Figs. 6–8. Observing Figs. 6 and Fig. 7, we find two differences between the wire entrance (1) and wire exit (2) edges. The edge chipping heights and widths are higher at the wire exit side (2) (Figs. 6 (b–1) and Figs. 7 (b–1)) compared with those at the wire entrance side (1) (Figs. 6 (a–1) and Figs. 7 (a–1)). The wafer surface is left with high pit density (Figs. 6 (b–2) and Figs. 7 (b–2)) at the wire exit side (2) compared with the wire entrance side (1) (Figs. 6 (a–2) and Figs. 7 (a–2)). In g- Si wafers, the edge chipping heights at the wire entrance and wire exit sides are 12–14
Fig. 5. Diagram of diamond wire at the entrance and exit side in an Si brick, and schematic diagram of wafer edge chipping measurement.
than that to the wafers cut from the fresh-wire side because the worn-wire-side wafers were cut by blunt diamond particles. The wafer breakage strength strongly depends on the damage state in the wafer area under maximal stress. Therefore, the fresh-wire-side wafers have lower fracture strengths compared with the worn-wire-side wafers. The explanation for the second difference is as follows. The g- Si wafers (both fresh-wire side and worn-wire side) are fractured at a lower strength compared with the p- Si wafers. From the surface roughness measurement, the ground Si brick surface (roughness 0.418 μm) suffered higher damage than the mirror-polished Si brick surface (roughness 0.013 μm). In wafer sawing, the g- Si wafer edges carry excess damage from their parent Si brick, which is responsible for their lower fracture strength compared with the p- Si wafers. Normally, in thin wafers, a small difference in damage state (surface, sub-surface, or edge damage) has a strong impact on its wafer fracture strength. It can be seen in Fig. 4 that both g- Si wafers and p- Si wafers fracture at a variety (distribution) of strengths. The previous reports show that the fracture strength of thin
Fig. 6. SEM images of edge-chipping profiles on the fresh-wire-side g- Si wafer (a) at the wire entrance side (1) (a-1 edge cross-sectional view and a-2 edge surface), (b) at the wire exit side (2) (b-1 edge cross-sectional view and b-2 edge surface). 5
H. Sekhar et al.
Materials Science in Semiconductor Processing 105 (2020) 104751
Fig. 7. SEM images of edge-chipping profiles on fresh-wire-side p- Si wafer (a) at the wire entrance side (1) (a-1 edge cross-sectional view and a-2 edge surface), (b) at the wire exit side (2) (b-1 edge cross-sectional view and b-2 edge surface).
Fig. 8. (a) SEM images of edge-chipping profiles perpendicular to the direction of wire motion on the wafer surface (3) for (a) g- Si wafer, (b) p- Si wafer.
μm and 16–18 μm (Fig. 6(a and b)). In p- Si wafers, the edge chipping heights at the wire entrance and wire exit sides are 8–12 μm and 13–15 μm (Fig. 7(a and b)). In g- Si wafers, both sides of edge chipping are higher compared with those in p-wafers. The explanation for the higher chipping and number of pits at the wire exit side is as follows. The Si brick is attached to the supporting bar with glue, as shown in Fig. 9 (a). As sawing progresses, the wire ad vances in the Si brick by cutting material and the wire comes closer towards the brick edge, as shown in Fig. 9 (a), and the wire is ready to transfer from Si to glue. At this point, most of the Si brick is already cut into wafer form, only small parts of Si are left out and it needs to be sawn to grow as a full wafer. At this point, both the wire and the wafer suffer from small fluctuations in the form of vibrations, resulting in punches on each other. The punching causes diamond abrasives to induct the Si and plug the ductile phase (a-Si layer) from the wafer surface in the
Fig. 9. (a) Schematic of diamond wire (DW) at the exit side of an Si brick. (b) Schematic diagram of wafer edge-chipping profile in <1 0 0> crystal orienta tion in thin Si wafers.
6
H. Sekhar et al.
Materials Science in Semiconductor Processing 105 (2020) 104751
Fig. 10. The cross-sectional cleavages of broken samples from the middle of g-wafers at different strengths: (a) 132 MPa, (b) 185 MPa, (c) 218 MPa, (d) 267 MPa.
scratching. This gives the wafer surface a high pit density at the wire exit side compared with the wire entrance side. There is significant scope to increase fracture strengths and sawing yields further by redefining the process parameters (wire speed, brick feed rates, and tension on the wire) at the wire exit side. The edge-chipping profiles of the g- Si wafer and p- Si wafer perpendicular to the direction of wire motion (3) are shown in Fig. 9. In both wafers the chipping heights are approximately 2–5 μm. Under perpendicular bending, the wafer experiences a negli gible stress at position (3) as shown in Fig. 2(c). This may not have a strong impact on its wafer fracture. In thin Si wafers, the edge-chipping profiles and chipping mecha nisms are not well understood. In the present study, we attempted to improve the understanding of edge-chipping profiles and chipping mechanisms by considering crystallographic orientation, as shown in Fig. 9 (b). The elucidation for edge-chipping profiles is as follows. Thin wafer crystal orientations and cleavage planes are considered to be dominant to decide edge-chipping shapes. The Si is a diamond lattice cubic structure followed by three {100}, {110}, and {111} crystalline planes. The angle between the <1 0 0> and <1 1 0> crystal orientations is 45� , and the {111} plane is the lowest energy cleavage plane with the smallest binding force [7]. In previous reports on the application of IC packaging, involving the grinding of thick (100) Si wafers to thin wafers, cracks are preferentially developed in its {111} cleavage planes. Edge chipping typically starts and propagates along the <1 1 0> crystal orientation on the {111} planes, and the edge chipping profile becomes an isosceles right triangle in the <1 0 0> crystal orientation [7]. In thin (100) Si wafer sawing, the Si brick is forced towards the wire web, which allows the cracks to initiate on the lower energy cleavage plane {111}, propagate in <1 1 0> crystal orientation, and chip the Si in brittle mode as shown in Fig. 9 (b) [7]. From Figs. 6 (a–1 and a-2) and Figs. 7 (a–1 and a-2), it is clear that thin Si wafer edges becomes sharp and cracks are
initiated on the low energy cleavage plane {111}, and chips in the <110> crystal direction [7]. As the wire starts to move into the Si brick by scratching and indenting of diamond particles, the ductile chipping becomes real. To understand the wafer fracture mechanism in the three-line bending test, the broken samples under the loading bar were analyzed with a fractographic method of electron microscopy. Normally, the cross-sections of fractured samples hold valuable information on how the damages (cracks) are responsible for opening the material. Because of the anisotropic nature of Si, the {1 1 1} and {1 1 0} crystal planes are considered to have lower toughness. In this sense, crystal low energy cleavage ({1 1 1} and {1 1 0}) planes are the dominant areas to fracture the Si (1 0 0) in the <1 1 0 > crystal direction [27,30,31]. Previous experiments on three-line bending of c-Si (1 0 0) samples with various pre-crack lengths on its surface exhibited fractures of various (low- kinetic-energy (mirror) and high-kinetic-energy (mirror-mist, mist, hackle, and branching)) mechanisms [32–38]. In the three-line bending experiment, under continuous loading, the wafer experienced a compressive stress on its front surface and a tensile stress on its back surface, and the applied stress accumulated as strain energy at the crack. Under loading, the wafer sustained up to a certain load by bending and then, when the load exceeded the wafer strength, cracks started to propagate by releasing strain energy in this direction, and opened the material by fracturing the wafer. To understand the fracture mechanism in g-wafers and p-wafers, the lower and higher fracture strength samples (from the middle of the wafer) had their cross-sections recorded and shown in Fig. 10 and Fig. 11. In Fig. 10 (a), the lower-strength (132 MPa) fractured sample followed the mirror mechanism. In mirror fracture, sample crosssections seem to be atomically smooth or mirror-like, with little or no surface perturbations [32–34]. The cracks propagate in a stable manner, 7
H. Sekhar et al.
Materials Science in Semiconductor Processing 105 (2020) 104751
Fig. 11. The cross-sectional cleavages of broken samples from the middle of p-wafers at different strengths: (a) 312 MPa, (b) 364 MPa.
and the fracture follows the low-kinetic-energy mechanism. In this case the wafer fractured into a few large pieces [19]. The wafers that fractured at intermediate strengths (185, 218, and 267 MPa) are shown in Fig. 10(b) and (c), and (d). The fractured sample cross-sectional surface accommodates fluctuations on its mirror surface. The cracks propagate at an unstable manner that leads to surface perturbation in this direction, and the fracture follows the high-kineticenergy mechanism. In this case, the wafer fracture follows the mirrormist and hackle mechanisms. The wafers that fractured at higher strengths are shown in Fig. 11(a) and (b). In this case, the overgrowing stress on the wafer surface results in bifurcation. In Fig. 11 (b), one can clearly see crack branching (bifurcation) taking place, and cracks follow longer paths and propagate less stably in a tortuous way, from the top surface to the bottom surface and vice versa. Therefore, the samples of wafers that fractured at higher strengths have more complex crosssectional surface morphologies. In this fracture, the wafers are made to fracture into many tiny pieces. From Figs. 10 and 11, we conclude that as the wafer strength increases, the cross-sectional surface perturbations of the fractured samples gradually increases and the cracks follow more complex paths. From fractographic studies we can conclude that the wafers that fracture at lower strengths have deeper damage caused by the mirror-fracture mechanism. The wafers that fracture at higher strength have shallow damages caused by the mirror-mist, hackle, and branching fracture mechanisms.
Appendix A. Supplementary data Supplementary data to this article can be found online at https://doi. org/10.1016/j.mssp.2019.104751. References [1] G.-S. Jeong, W. Bae, D.-K. Jeong, Review of CMOS integrated circuit technologies for high-speed photo-detection, Sensors 17 (2017) 1962. https://www.ncbi.nlm. nih.gov/pmc/articles/PMC5620527/. [2] International Technology Roadmap for Photovoltaics (ITRPV), 9th ed. (2018) and 10th ed, 2019. https://itrpv.vdma.org/. [3] K. Yamamoto, K. Yoshikawa, H. Uzu, D. Adachi, High-efficiency heterojunction crystalline Si solar cells, Jpn. J. Appl. Phys. 57 (1–8) (2018) 08RB20. https://iopsc ience.iop.org/article/10.7567/JJAP.57.08RB20/meta. [4] J. Walters, K. Sunder, O. Anspach, R.P. Brooker, H. Seigneur, Challenges associated with diamond wire sawing when generating reduced thickness mono-crystalline silicon wafers, IEEE Photovolt. Spec. Conf. (2016) 0724–0728. https://ieeexplore. ieee.org/document/7749697. [5] S. Wieghold, A.E. Morishige, L. Meyer, T. Buonassisi, E.M. Sachs, Crack detection in crystalline silicon solar cells using dark-field imaging, Energy Procedia 124 (2017) 526–531. https://www.sciencedirect.com/science/article/pii/S1876610 217341838. [6] T.S. Liang, M. Pravettoni, C. Deline, J.S. Stein, R. Kopecek, J.P. Singh, W. Luo, Y. Wang, A.G. Aberle, Y.S. Khoo, A review of crystalline silicon bifacial photovoltaic performance characterisation and simulation, Energy Environ. Sci. 12 (2019) 116–148. https://pubs.rsc.org/en/content/articlelandi ng/2019/ee/c8ee02184h#!divAbstract. [7] S. Gao, R. Kang, Z. Dong, B. Zhang, Edge chipping of silicon wafers in diamond grinding, Int. J. Mach. Tool Manuf. 64 (2013) 31–37. https://www.sciencedirect. com/science/article/pii/S0890695512001587. [8] M. Li, Y. Dai, W. Ma, B. Yang, Q. Chu, Review of new technology for preparing crystalline silicon solar cell materials by metallurgical method, IOP Conf. Ser. Earth Environ. Sci. 94 (1–11) (2017) 012016. https://iopscience.iop.org/article/ 10.1088/1755-1315/94/1/012016. [9] W.F. Struth, K. Steffens, W. Konig, Wafer slicing by internal diameter sawing, Precis. Eng. 10 (1988) 29–34. https://www.sciencedirect.com/science/article/pii/ 014163598890092X. [10] Z.J. Pei, G.R. Fisher, J. Liu, Grinding of silicon wafers: a review from historical perspectives, Int. J. Mach. Tool Manuf. 48 (2008) 1297–1307. https://www.scienc edirect.com/science/article/pii/S0890695508001089. [11] G. Fisher, M.R. Seacrist, R.W. Standley, Silicon crystal growth and wafer technologies, Proc. IEEE 100 (2012) 1454–1474. https://ieeexplore.ieee.org/do cument/6178756. [12] X. Li, Y. Gao, P. Ge, L. Zhang, W. Bi, The effect of cut depth and distribution for abrasives on wafer surface morphology in diamond wire sawing of PV polycrystalline silicon, Mater. Sci. Semicond. Process. 91 (2019) 316–326. https:// www.sciencedirect.com/science/article/pii/S1369800118312046. [13] A. Bidiville, K. Wasmer, J. Michler, P.M. Nasch, M. Van der Meer, C. Ballif, Mechanisms of wafer sawing and impact on wafer properties, Prog. Photovoltaics 18 (2010) 563–572. https://onlinelibrary.wiley.com/doi/full/10.1002/pip.972. [14] J.D. Gates, Two-body and three-body abrasion: a critical discussion, Wear 214 (1998) 139–146. https://www.sciencedirect.com/science/article/pii/S0043164 897001889. [15] H. Wu, Wire sawing technology: a state-of-the-art review, Precis. Eng. 43 (2016) 1. https://www.sciencedirect.com/science/article/pii/S0141635915001531. [16] S. Choi, B. Jang, J. Kim, H. Song, T. Baek, M. Han, Effects of mirror polishing brick surface on process yield of multi-wire slicing for thin single-crystalline silicon solar cells, Sol. Energy 122 (2015) 1170–1179. https://www.sciencedirect.com/science/ article/pii/S0038092X15005733. [17] H. Sekhar, T. Fukuda, K. Tanahashi, K. Shirasawa, H. Takato, K. Ohkubo, H. Ono, Y. Sampei, T. Kobayashi, The impact of subsurface damage on the fracture strength of diamond-wire-sawn monocrystalline silicon wafers, Jpn. J. Appl. Phys. 57
4. Conclusions The goal of this paper is to bring some insight into the cutting of thin Si wafers using thin diamond wires to fulfill the objectives of the ITRPV 2018–2029 road map. The breakage of thin Si wafers during manufacturing is an important issue and has a strong impact on its production yields and costs. The diamond wire quality and Si brick polishing are the deciding factors in thin (120 μm) Si wafer-slicing yields and fracture strengths. The ground (g) and mirror-polished (p) Si bricks are sawn into thin (120 μm) silicon (Si) wafers. The higher damage on gwafer edges is responsible for their lower sawing yields (>90%) and lower fracture strengths. By polishing an Si brick with ultra-low surface roughness (mirror polish), we achieved higher sawing yields (>96%) and higher fracture strengths in thin Si wafers. There is still room to improve the sawing yields and fracture strengths by controlling both wire and wafer dynamics at the wire exit in between the Si brick and the glue. Depending on the wafer damage (surface, subsurface, and edge) state, wafers are made to fracture via low- or high-energy mechanisms. Acknowledgment The authors thank Noritake Co., Ltd. for supporting the experiment and helping us to receive a large amount of diamond wire for this study.
8
H. Sekhar et al.
[18]
[19]
[20] [21]
[22]
[23]
[24] [25]
[26]
[27]
Materials Science in Semiconductor Processing 105 (2020) 104751
(2018) 08RB08. https://iopscience.iop.org/article/10.7567/JJAP.57.08RB08/met a. H. Sekhar, T. Fukuda, K. Tanahashi, K. Shirasawa, H. Takato, K. Ohkubo, H. Ono, Y. Sampei, T. Kobayashi, The impact of saw mark direction on the fracture strength of thin (120 μm) monocrystalline silicon wafers for photovoltaic cells, Jpn. J. Appl. Phys. 57 (2018) 095501. https://iopscience.iop.org/article/10.7567/JJAP.57.09 5501/meta. H. Sekhar, T. Fukuda, K. Tanahashi, H. Takato, The impact of damage etching on fracture strength of diamond wire sawn monocrystalline silicon wafers for photovoltaics use, Jpn. J. Appl. Phys. 57 (2018) 126501. https://iopscience.iop. org/article/10.7567/JJAP.57.126501/meta. A.M. Kovalchenko, YuV. Milman, On the cracks self-healing mechanism at ductile mode cutting of silicon, Tribol. Int. 80 (2014) 166–171. https://www.sciencedirec t.com/science/article/pii/S0301679X14002618. T. Liu, P. Ge, W. Bi, Y. Gao, Subsurface crack damage in silicon wafers induced by resin bonded diamond wire sawing, Mater. Sci. Semicond. Process. 57 (2017) 147–156. https://www.sciencedirect.com/science/article/pii/S136980011630 4383. J. Yan, T. Asami, H. Harada, T. Kuriyagawa, Fundamental investigation of subsurface damage in single crystalline silicon caused by diamond machining, Precis. Eng. 33 (2009) 378–386. https://www.sciencedirect.com/science/article/ pii/S0141635908001530. Y. Chiba, Y. Tani, T. Enomoto, H. Sato, Development of a high-speed manufacturing method for electroplated diamond wire tools, CIRP Annals 52 (2003) 281–284. https://www.sciencedirect.com/science/article/pii/S000785060 7605848. Y. Gao, P. Ge, T. Liu, Experiment study on electroplated diamond wire saw slicing single- crystal silicon, Mater. Sci. Semicond. Process. 56 (2016) 106–114. https:// www.sciencedirect.com/science/article/pii/S1369800116302499. U. Pala, S. Sussmaier, F. Kuster, K. Wegener, Experimental investigation of tool wear in electroplated diamond wire sawing of silicon, Procedia CIRP 77 (2018) 371–374. https://www.sciencedirect.com/science/article/pii/S2212827 118311946. A. Kumar, S.N. Melkote, Diamond wire sawing of solar silicon wafers: a sustainable manufacturing alternative to loose abrasive slurry sawing, Procedia Manuf. 21 (2018) 549–566. https://www.sciencedirect.com/science/article/pii/S2351978 918301963. T. Vodenitcharova, O. Borrero-L� opez, M. Hoffman, Mechanics prediction of the fracture pattern on scratching wafers of single crystal silicon, Acta Mater. 60
[28]
[29] [30] [31]
[32] [33] [34] [35]
[36] [37] [38]
9
(2012) 4448–4460. https://www.sciencedirect.com/science/article/pii/S1359645 412002960. M. Ge, H. Zhu, C. Huang, A. Liu, W. Bi, Investigation on critical crack-free cutting depth for single crystal silicon slicing with fixed abrasive wire saw based on the scratching machining experiments, Mater. Sci. Semicond. Process. 74 (2018) 261–266. https://www.sciencedirect.com/science/article/pii/S1369800 117316335. Z.J. Pei, S.R. Billingsley, S. Miura, Grinding induced subsurface cracks in silicon wafers, Int. J. Mach. Tool Manuf. 39 (1999) 1103–1116. https://www.sciencedirec t.com/science/article/pii/S0890695598000790. R. P� erez, P. Gumbsch, Directional anisotropy in the cleavage fracture of silicon, Phys. Rev. Lett. 84 (2000) 5347–5350. https://journals.aps.org/prl/abstract/ 10.1103/PhysRevLett.84.5347. C. Klute, F. Kaule, S. Schoenfelder, Breakage Root Cause Analysis in As-Cut Monocrystalline Silicon Wafers, 29th European Photovoltaic Solar Energy Conference and Exhibition, 2014, pp. 753–756, in: https://www.eupvsec-proceed ings.com/proceedings?paper¼29589. D. Sherman, Aspects of rapid crack propagation in silicon, Fatigue Fract. Eng. Mater. Struct. 30 (2006) 32–40. https://onlinelibrary.wiley.com/doi/full/10. 1111/j.1460-2695.2006.01054.x. D. Sherman, I. Be’ery, Dislocations deflect and perturb dynamically propagating cracks, Phys. Rev. Lett. 93 (2004) 265501. https://journals.aps.org/prl/abstract/ 10.1103/PhysRevLett.93.265501. D. Sherman, Energy considerations in crack deflection phenomenon in single crystal silicon, Int. J. Fract. 140 (2006) 125–140. https://link.springer.com/article /10.1007/s10704-006-0048-9. D. Sherman, I. Be’ery, From crack defection to lattice vibrations-macro to atomistic examination of dynamic cleavage fracture, J. Mech. Phys. Solids 52 (2004) 1743–1761. https://www.sciencedirect.com/science/article/pii/S00225 09604000286?via%3Dihub. D. Sherman, Hackle or textured mirror? Analysis of surface perturbation in single crystal silicon, J. Mater. Sci. 00 (2003) 1–6. https://link.springer.com/article/10.1 023/A:1021809014702. D. Sherman, Fractography of dynamic crack propagation in silicon crystal, Key Eng. Mater. 409 (2009) 55–64. https://www.scientific.net/KEM.409.55. M. Wang, L. Zhao, M. Fourmeau, D. Nelias, Crack plane deflection and shear wave effects in the dynamic fracture of silicon single crystal, J. Mech. Phys. Solids 122 (2019) 472–488. https://www.sciencedirect.com/science/article/pii/S0022509 618305866.