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The International Technology Roadmap for Semiconductors—Perspectives and challenges for the next 15 years
Current Opinion in Solid State and Materials Science 6 (2002) 371–377
The International Technology Roadmap for Semiconductors— Perspectives and challenges for the next 15 years q Wolfgang M. Arden* Infineon Technologies AG, St. Martinstrasse 76, 81541 Muenchen, Germany
Abstract The paper will give an overview on the structure and the contents of the International Technology Roadmap for Semiconductors (ITRS), with special emphasis on the ‘ITRS 2001’ edition. The scope of the ITRS covers the next 15 years. The outlook in semiconductor manufacturing expects the continuous application of silicon technology where CMOS based devices will carry the development of the industry at least for one more decade. New device architectures and concepts based on silicon wafer material are being developed to support the development of the IC industry for another one or two decades. The paper will highlight the key issues of future requirements on semiconductor structures and processes for manufacturing technologies on silicon. These will cover material aspects for front end processing, interconnect, lithography, and new devices. 2002 Elsevier Science Ltd. All rights reserved.
1. Introduction The definition of a technology roadmap for the semiconductor industry started as a national effort in the United States in 1992. Six years later this effort became an international activity with the major global regions participating in the definition of the roadmap, which is now called the International Technology Roadmap for Semiconductors (ITRS). The organizations editing the ITRS are the Semiconductor Industry Associations (or corresponding affiliations) of USA, Europe, Japan, Korea, and Taiwan. Besides the semiconductor industry which is the owner of the ITRS, there are also representatives from the equipment and materials supplier industry, research institutes and international research consortia joining in the roadmapping work. In total more than 800 experts are participating in the definition of the roadmap. The ITRS is edited on a regular basis every two years (odd year numbers) with updates of the tables only in the years between (even year numbers). The mission of the ITRS is the definition of the near and long term technology requirements for the semiconductor industry as well as the description of potential technical q This publication was presented as an invited paper in the plenary session of the 2002 spring meeting of the European Materials Research Society (E-MRS) in Strasbourg, June 18th–21st. *Tel.: 149-89-234-41480, fax: 149-89-234-717959. E-mail address: [email protected] (W. M. Arden).
solutions to meet these needs. The technical scope of the ITRS is depicted in Fig. 1. There are twelve International Technical Working Groups (ITWGs) active in the definition of the roadmap. These twelve ITWGs cover focus areas of the semiconductor technology, e.g. Design and Test, Front End Processing, Interconnect, Lithography, Process Integration. So-called cross-cut ITWGs deal with cross-functional issues of the roadmap, these are for example Modeling and Simulation, or Metrology. The overall activity of the ITRS is coordinated by an International Roadmap Committee (IRC).
2. Driving forces of the ITRS and technology node timing There are several driving forces behind the continuing evolution of semiconductor technology (see Fig. 2). The major drivers are the increase in functionality with embedding digital, analog and memory functions or even sensoric elements on a single chip, the continuous decrease in cost per function, the improvement in processing speed and memory capacity, and last but not least the decrease in power consumption per operation. Quantitatively this evolution was characterized by the following historic trends which were first recognized by Gordon Moore (‘Moore’s Law’ [1,2]): The cost per function decreased by 30% per year, the capacity for DRAM memories increased by a factor of four every three years, and the MPU
1359-0286 / 02 / $ – see front matter 2002 Elsevier Science Ltd. All rights reserved. PII: S1359-0286( 02 )00116-X
W. M. Arden / Current Opinion in Solid State and Materials Science 6 (2002) 371–377
372
Nomenclature ASIC CMOS DRAM IRC ITRS ITWG MPU
Application specific integrated circuit Complementary metal oxide semiconductor Dynamic random access memory International Roadmap Committee International Technology Roadmap for Semiconductors International Technical Working Group Micro-processor unit
Fig. 1. Technical scope of the International Technology Roadmap for Semiconductors (ITRS) with International Technical Working Groups (ITWGs) and International Roadmap Committee (IRC).
performance speed rose by a factor of two every two years. This trend however recently slowed down to a 43 increase every four years for memory capacity and to a 23 increase every four to six years for MPU performance, caused by
upcoming limitations in 3-dimensional integration and scaling of memory cell sizes, and by continuous downscaling of the device supply voltages restricting the achievable driving currents of semiconductor devices. In
Fig. 2. Driving forces in the semiconductor technology roadmap (RF5radio frequency, SRAM5static random access memory, NVM5non volatile memory, EEPROM5electrically erasable programmable read-only-memory, FRAM5ferroelectric random access memory, MRAM5magnetic random access memory, MEMS5micro-electronic-mechanical system).
W. M. Arden / Current Opinion in Solid State and Materials Science 6 (2002) 371–377
order to compensate these limitations, the introduction of new technology nodes with decreased feature sizes was accelerated in recent years. Traditionally the minimum features of an integrated circuit (IC) and its devices were scaled down by a factor of 0.7 per technology node every three years since 1975. The critical features to be scaled along these rules are the polysilicon and first metal layer pitches and the gate length of the MOS transistor device. In recent years (since 1995) the scaling speed was accelerated with introduction of new technology nodes every two years. By this acceleration the semiconductor industry could maintain its speed of cost reduction and performance increase. Fig. 3 shows the overall technology characteristics from ‘Table 1’ of the ‘ITRS 2001’ roadmap edition [3] for the next fifteen years depicting the following critical feature sizes: Half-pitch values for DRAM which define the technology nodes, as well as the half-pitch values for MPU and the gate-lengths for the MOS transistors for MPU and ASIC / Low Power devices. The projection for DRAM critical features follows a 3-year cycle with a scaling factor of 0.7 every three years, whereas the feature size scaling for MPUs follows a 2-year cycle until 2004, and then returns to a 3-year cycle along with DRAM. The devices are scaled even more aggressively with reducing the gate
373
lengths for MPUs by a 2-year cycle until 2005, followed by a 3-year cycle thereafter. The device geometries for ASICs are following those for MPUs with a delay of two years, basically for the reason of a better control of device leakage currents and system power consumption.
3. Hierarchy of IC requirements In order to define the technology demands of the IC industry, a hierarchy of requirements is established in the ITRS definition process, as outlined in Fig. 4. This process starts with the definition of integrated circuit requirements like cost, power, speed and density followed by overall device requirements given by the parameters supply voltage, leakage and drive currents, transistor size, threshold voltage control and others. Thereafter device scaling and device design issues are defined as for example gate length, gate dielectric, junction depth, and channel engineering properties. Finally process integration requirements are derived, e.g. thermal budget, overall process flow and material properties. In order to define this sequence of technology needs, a very intensive crossfunctional cooperation between the individual Technical Working Groups has become a common practice.
Fig. 3. Technology node characteristics as outlined in the ‘ITRS 2001’ edition.
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W. M. Arden / Current Opinion in Solid State and Materials Science 6 (2002) 371–377
Fig. 4. Hierarchy of integrated circuit requirements and choices (Vdd 5supply voltage, T ox 5oxide thickness, Lg 5gate length, S / D xj5source / drain junction depth).
4. CMOS device scaling and new device structures The continuous scaling of classical CMOS devices is building up key challenges for the design of the transistor. The down scaling of the supply voltage requires an accelerated shrink of the gate length in order to keep up with the demands for switching speed; the down-scaling of the gate length however results in an increase of the gate resistance with the future requirement to introduce low resistivity metal gates, for example silicon-germanium, especially for high frequency applications. The scaling of the gate oxide thickness leads to an increase of gate-tosubstrate tunneling currents which results in unacceptable leakage currents and requires the introduction of high k dielectrics as e.g. oxinitrides or oxide based compounds of aluminum / hafnium. The third area with device scaling
leading to severe limitations is the source / drain region, where the continuous thickness reduction results in high series resistance and problems in silicidation of the diffusion areas with the demand for innovative solutions as e.g. elevated source / drain. The traditional scaling of classical CMOS devices leads to performance limitations which have to be overcome by introduction of new materials and improvements of the device design. However, planar conventional CMOS devices can not be scaled to dimensions below 50 nm gate lengths without severely sacrificing performance. New socalled ‘non-classical’ device concepts are being developed for MOS devices to remove the barriers of conventional transistor designs for MOSFETs (metal-oxide-silicon fieldeffect-transistors). An overview of some of these new— still CMOS-based—device concepts is shown in Fig. 5 in
Fig. 5. Cross-sections of ‘non-classical’ CMOS devices.
W. M. Arden / Current Opinion in Solid State and Materials Science 6 (2002) 371–377
comparison with standard bulk devices. Some of these advanced device structures will probably be introduced within the next 5 to 10 years. The thin-body (SOI5silicon-on-insulator) MOSFET is characterized by a very thin (smaller than 50 nm) active device layer separated from the silicon substrate by an insulating oxide. Its advantages are improved subthreshold slope and reduced parasitic capacitance, whereas the thickness control of the active silicon layer is a manufacturing challenge. The double-gate MOSFET introduces a second gate between the transistor channel and the substrate, thus improving transistor drive currents and short channel effects, however process integration and manufacturability of this advanced architecture are still key issues to be solved. The vertical MOSFET is also challenged by process complexity and manufacturability, its key advantages are lithography independent gate length control and higher drive currents.
5. Interconnect issues In the near term (next five years) the increasing effect of interconnect parasitic capacitances leads to the need for integrating interconnect dielectrics with low dielectric constants. The corresponding k values will be decreasing from 3.6 (fluorinated silicon oxide) today down to about 2 and below in the year 2007 and beyond. Due to severe material and integration problems the introduction of socalled low k dielectrics has been delayed in the ‘ITRS 2001’ edition as compared to the ‘ITRS 1999’ version. In the longer term the key challenges for interconnects will be the limited conductivity of the present conductor material copper. Material innovation combined with traditional scaling will no longer satisfy the performance require-
375
ments. New solutions beyond the present technology have to be developed and introduced. For example, new innovative concepts in the areas of design, interconnect and packaging are needed to overcome the limited conductivity of the copper interconnect material in longer term. Alternative conductors may have to be introduced, as for example optical or RF conductors.
6. Lithography The imaging and patterning techniques have always been a major challenge in the semiconductor technology. Optical lithography is the work horse of present imaging techniques, and continuous reduction of the imaging wavelength has kept optical lithography alive, but it is now approaching its physical limitations: The patterned feature size today is already about half of the imaging wavelength. Probably the last imaging source to be applied in large scale manufacturing will be a fluor based laser with 157 nm wavelength with a potential resolution down to the 65 nm technology node, a feature size which amounts to 40% of the imaging wavelength. Control of the critical dimensions will be a key challenge for this technology. There are several alternative imaging technologies in development which are to follow the optical lithography. These alternatives, their potential applications to the future technology nodes and their timing as projected in the ‘ITRS 2001’ are depicted in Fig. 6. A major global consensus now has been reached that extreme UV (EUV) with an imaging wavelength of 13 nm is the most favourite potential candidate for the next generation lithography technology. With a 13 nm imaging wavelength which actually corresponds to soft X-rays rather than to ultraviolet light, completely new materials in the area of
Fig. 6. Potential lithography techniques for future technology nodes.
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W. M. Arden / Current Opinion in Solid State and Materials Science 6 (2002) 371–377
imaging optics, mask substrates and absorbers, and resists have to be developed. Their future introduction into volume manufacturing will impose a great challenge.
7. Material requirements The future development of the IC industry puts forward major challenges to the material research scientists. Although silicon substrate materials will remain the dominant material in the IC industry for the next fifteen years, both physical and technological limitations are demanding for the introduction of new materials both in the frontend as well as in the interconnect and backend processing area of semiconductor manufacturing. ASIC and microprocessor applications are pushing the material innovation in the gate stack and interconnect technology, whereas in the memory area the continuous scaling of memory cell sizes drives the introduction of high k dielectric materials for DRAMs and ferroelectric materials for non-volatile memories. In lithography new materials will be required for imaging resists as well as for mask substrates and projection lens elements, as for example CaF 2 for 157 nm projection.
8. Summary of key challenges In order to fulfill the future projections of the ‘ITRS 2001’ roadmap, many challenges and potential roadblocks are to be resolved. Some of the major issues in future semiconductor technologies are summarized in Fig. 7. A key question is whether the overall cost trend and target of 30% reduction in cost per function and year can be achieved in future in view of the increasing expenses for research and development and the rising investment cost
for manufacturing equipment. In the technology area the major challenges are in the field of lithography with the migration from optical to extreme UV systems, in the field of the device due to the introduction of new materials for gate and gate dielectric and the implementation of ‘nonclassical’ CMOS-based device structures, and in the field of interconnect because of the increasing dominance of the parasitic RC delay. The rapid progress in semiconductor technology evolution leads to enormous challenges on the part of integrated circuit design demanding for rapid improvement in design productivity, the integration of multiple functionalities in complex systems-on-chip (SoC) and in their verification and testing.
9. Outlook The International Technology Roadmap for Semiconductors gives a long term projection of key requirements and specifications for the next fifteen years in silicon technology. Based on the projection of historic trends in the semiconductor industry and on the technical assessment of future potential solutions in the field of technology, the ‘ITRS 2001’ edition gives specific projections down to the year of 2016. In Fig. 8 some of the key parameters and characteristics of integrated circuit devices are highlighted for the year of 2016 which might be comprehended as a long term vision for the evolution of the semiconductor technology in the next fifteen years. We can envision dynamic memories with 64 Gigabit storage capacity and minimum feature sizes of 22 nm, microprocessor chips with 6 billion transistors, a maximum operation frequency of 28 Gigahertz and a minimum device gate length of 9 nm, and a system-on-chip with a pad pitch of 20 mm, manufactured on silicon wafers with
Fig. 7. Key challenges for future semiconductor technologies (SOI5silicon on insulator, SoC5system on chip).
W. M. Arden / Current Opinion in Solid State and Materials Science 6 (2002) 371–377
377
extreme UV is the most viable candidate for the next generation imaging system. In order to overcome limitations in overall chip performance as imposed by conventional CMOS scaling, new materials in both the frontend and interconnect processing area will be introduced together with more sophisticated device engineering. In the long term new ‘non-classical’ CMOS-based device structures are to be implemented to fulfill the continuous demand for performance increase and cost decrease in the IC industry. Silicon based technology will remain the mainstream semiconductor technology for at least two more decades.
Fig. 8. Vision of the ‘ITRS 2001’ roadmap for the year of 2016.
450 mm diameter, packaged with a maximum number of 4700 pins and operated at 0.4 volts supply voltage.
10. Conclusion As a global effort the ITRS is developed to address challenges and potential solutions for the semiconductor industry in the next fifteen years. The methodology and the hierarchical approach of the definition of future requirements of the IC industry in the ITRS have been described. Future limitations in device performance and memory cell scaling are driving forces for accelerated feature size scaling. Optical lithography will be pushed to its limits,
Acknowledgements The provision of some of the figures of this article by Toshitaka Fukushima from Fujitsu Corporation, Werner Klingenstein from Infineon Technologies, Paolo Garjini from Intel, and the SIA (Semiconductor Industry Association of USA) who has the copyright of the contents of the ITRS, is highly appreciated.
References [1] Moore G. Electronics Magazine 1965;(35th anniversary edition). [2] Moore G. Developing the integrated circuit,. PC Magazine 1997;(25th March). [3] ITRS Web-Site: http: / / public.itrs.net /
The International Technology Roadmap for Semiconductors— Perspectives and challenges for the next 15 years q Wolfgang M. Arden* Infineon Technologies AG, St. Martinstrasse 76, 81541 Muenchen, Germany
Abstract The paper will give an overview on the structure and the contents of the International Technology Roadmap for Semiconductors (ITRS), with special emphasis on the ‘ITRS 2001’ edition. The scope of the ITRS covers the next 15 years. The outlook in semiconductor manufacturing expects the continuous application of silicon technology where CMOS based devices will carry the development of the industry at least for one more decade. New device architectures and concepts based on silicon wafer material are being developed to support the development of the IC industry for another one or two decades. The paper will highlight the key issues of future requirements on semiconductor structures and processes for manufacturing technologies on silicon. These will cover material aspects for front end processing, interconnect, lithography, and new devices. 2002 Elsevier Science Ltd. All rights reserved.
1. Introduction The definition of a technology roadmap for the semiconductor industry started as a national effort in the United States in 1992. Six years later this effort became an international activity with the major global regions participating in the definition of the roadmap, which is now called the International Technology Roadmap for Semiconductors (ITRS). The organizations editing the ITRS are the Semiconductor Industry Associations (or corresponding affiliations) of USA, Europe, Japan, Korea, and Taiwan. Besides the semiconductor industry which is the owner of the ITRS, there are also representatives from the equipment and materials supplier industry, research institutes and international research consortia joining in the roadmapping work. In total more than 800 experts are participating in the definition of the roadmap. The ITRS is edited on a regular basis every two years (odd year numbers) with updates of the tables only in the years between (even year numbers). The mission of the ITRS is the definition of the near and long term technology requirements for the semiconductor industry as well as the description of potential technical q This publication was presented as an invited paper in the plenary session of the 2002 spring meeting of the European Materials Research Society (E-MRS) in Strasbourg, June 18th–21st. *Tel.: 149-89-234-41480, fax: 149-89-234-717959. E-mail address: [email protected] (W. M. Arden).
solutions to meet these needs. The technical scope of the ITRS is depicted in Fig. 1. There are twelve International Technical Working Groups (ITWGs) active in the definition of the roadmap. These twelve ITWGs cover focus areas of the semiconductor technology, e.g. Design and Test, Front End Processing, Interconnect, Lithography, Process Integration. So-called cross-cut ITWGs deal with cross-functional issues of the roadmap, these are for example Modeling and Simulation, or Metrology. The overall activity of the ITRS is coordinated by an International Roadmap Committee (IRC).
2. Driving forces of the ITRS and technology node timing There are several driving forces behind the continuing evolution of semiconductor technology (see Fig. 2). The major drivers are the increase in functionality with embedding digital, analog and memory functions or even sensoric elements on a single chip, the continuous decrease in cost per function, the improvement in processing speed and memory capacity, and last but not least the decrease in power consumption per operation. Quantitatively this evolution was characterized by the following historic trends which were first recognized by Gordon Moore (‘Moore’s Law’ [1,2]): The cost per function decreased by 30% per year, the capacity for DRAM memories increased by a factor of four every three years, and the MPU
1359-0286 / 02 / $ – see front matter 2002 Elsevier Science Ltd. All rights reserved. PII: S1359-0286( 02 )00116-X
W. M. Arden / Current Opinion in Solid State and Materials Science 6 (2002) 371–377
372
Nomenclature ASIC CMOS DRAM IRC ITRS ITWG MPU
Application specific integrated circuit Complementary metal oxide semiconductor Dynamic random access memory International Roadmap Committee International Technology Roadmap for Semiconductors International Technical Working Group Micro-processor unit
Fig. 1. Technical scope of the International Technology Roadmap for Semiconductors (ITRS) with International Technical Working Groups (ITWGs) and International Roadmap Committee (IRC).
performance speed rose by a factor of two every two years. This trend however recently slowed down to a 43 increase every four years for memory capacity and to a 23 increase every four to six years for MPU performance, caused by
upcoming limitations in 3-dimensional integration and scaling of memory cell sizes, and by continuous downscaling of the device supply voltages restricting the achievable driving currents of semiconductor devices. In
Fig. 2. Driving forces in the semiconductor technology roadmap (RF5radio frequency, SRAM5static random access memory, NVM5non volatile memory, EEPROM5electrically erasable programmable read-only-memory, FRAM5ferroelectric random access memory, MRAM5magnetic random access memory, MEMS5micro-electronic-mechanical system).
W. M. Arden / Current Opinion in Solid State and Materials Science 6 (2002) 371–377
order to compensate these limitations, the introduction of new technology nodes with decreased feature sizes was accelerated in recent years. Traditionally the minimum features of an integrated circuit (IC) and its devices were scaled down by a factor of 0.7 per technology node every three years since 1975. The critical features to be scaled along these rules are the polysilicon and first metal layer pitches and the gate length of the MOS transistor device. In recent years (since 1995) the scaling speed was accelerated with introduction of new technology nodes every two years. By this acceleration the semiconductor industry could maintain its speed of cost reduction and performance increase. Fig. 3 shows the overall technology characteristics from ‘Table 1’ of the ‘ITRS 2001’ roadmap edition [3] for the next fifteen years depicting the following critical feature sizes: Half-pitch values for DRAM which define the technology nodes, as well as the half-pitch values for MPU and the gate-lengths for the MOS transistors for MPU and ASIC / Low Power devices. The projection for DRAM critical features follows a 3-year cycle with a scaling factor of 0.7 every three years, whereas the feature size scaling for MPUs follows a 2-year cycle until 2004, and then returns to a 3-year cycle along with DRAM. The devices are scaled even more aggressively with reducing the gate
373
lengths for MPUs by a 2-year cycle until 2005, followed by a 3-year cycle thereafter. The device geometries for ASICs are following those for MPUs with a delay of two years, basically for the reason of a better control of device leakage currents and system power consumption.
3. Hierarchy of IC requirements In order to define the technology demands of the IC industry, a hierarchy of requirements is established in the ITRS definition process, as outlined in Fig. 4. This process starts with the definition of integrated circuit requirements like cost, power, speed and density followed by overall device requirements given by the parameters supply voltage, leakage and drive currents, transistor size, threshold voltage control and others. Thereafter device scaling and device design issues are defined as for example gate length, gate dielectric, junction depth, and channel engineering properties. Finally process integration requirements are derived, e.g. thermal budget, overall process flow and material properties. In order to define this sequence of technology needs, a very intensive crossfunctional cooperation between the individual Technical Working Groups has become a common practice.
Fig. 3. Technology node characteristics as outlined in the ‘ITRS 2001’ edition.
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W. M. Arden / Current Opinion in Solid State and Materials Science 6 (2002) 371–377
Fig. 4. Hierarchy of integrated circuit requirements and choices (Vdd 5supply voltage, T ox 5oxide thickness, Lg 5gate length, S / D xj5source / drain junction depth).
4. CMOS device scaling and new device structures The continuous scaling of classical CMOS devices is building up key challenges for the design of the transistor. The down scaling of the supply voltage requires an accelerated shrink of the gate length in order to keep up with the demands for switching speed; the down-scaling of the gate length however results in an increase of the gate resistance with the future requirement to introduce low resistivity metal gates, for example silicon-germanium, especially for high frequency applications. The scaling of the gate oxide thickness leads to an increase of gate-tosubstrate tunneling currents which results in unacceptable leakage currents and requires the introduction of high k dielectrics as e.g. oxinitrides or oxide based compounds of aluminum / hafnium. The third area with device scaling
leading to severe limitations is the source / drain region, where the continuous thickness reduction results in high series resistance and problems in silicidation of the diffusion areas with the demand for innovative solutions as e.g. elevated source / drain. The traditional scaling of classical CMOS devices leads to performance limitations which have to be overcome by introduction of new materials and improvements of the device design. However, planar conventional CMOS devices can not be scaled to dimensions below 50 nm gate lengths without severely sacrificing performance. New socalled ‘non-classical’ device concepts are being developed for MOS devices to remove the barriers of conventional transistor designs for MOSFETs (metal-oxide-silicon fieldeffect-transistors). An overview of some of these new— still CMOS-based—device concepts is shown in Fig. 5 in
Fig. 5. Cross-sections of ‘non-classical’ CMOS devices.
W. M. Arden / Current Opinion in Solid State and Materials Science 6 (2002) 371–377
comparison with standard bulk devices. Some of these advanced device structures will probably be introduced within the next 5 to 10 years. The thin-body (SOI5silicon-on-insulator) MOSFET is characterized by a very thin (smaller than 50 nm) active device layer separated from the silicon substrate by an insulating oxide. Its advantages are improved subthreshold slope and reduced parasitic capacitance, whereas the thickness control of the active silicon layer is a manufacturing challenge. The double-gate MOSFET introduces a second gate between the transistor channel and the substrate, thus improving transistor drive currents and short channel effects, however process integration and manufacturability of this advanced architecture are still key issues to be solved. The vertical MOSFET is also challenged by process complexity and manufacturability, its key advantages are lithography independent gate length control and higher drive currents.
5. Interconnect issues In the near term (next five years) the increasing effect of interconnect parasitic capacitances leads to the need for integrating interconnect dielectrics with low dielectric constants. The corresponding k values will be decreasing from 3.6 (fluorinated silicon oxide) today down to about 2 and below in the year 2007 and beyond. Due to severe material and integration problems the introduction of socalled low k dielectrics has been delayed in the ‘ITRS 2001’ edition as compared to the ‘ITRS 1999’ version. In the longer term the key challenges for interconnects will be the limited conductivity of the present conductor material copper. Material innovation combined with traditional scaling will no longer satisfy the performance require-
375
ments. New solutions beyond the present technology have to be developed and introduced. For example, new innovative concepts in the areas of design, interconnect and packaging are needed to overcome the limited conductivity of the copper interconnect material in longer term. Alternative conductors may have to be introduced, as for example optical or RF conductors.
6. Lithography The imaging and patterning techniques have always been a major challenge in the semiconductor technology. Optical lithography is the work horse of present imaging techniques, and continuous reduction of the imaging wavelength has kept optical lithography alive, but it is now approaching its physical limitations: The patterned feature size today is already about half of the imaging wavelength. Probably the last imaging source to be applied in large scale manufacturing will be a fluor based laser with 157 nm wavelength with a potential resolution down to the 65 nm technology node, a feature size which amounts to 40% of the imaging wavelength. Control of the critical dimensions will be a key challenge for this technology. There are several alternative imaging technologies in development which are to follow the optical lithography. These alternatives, their potential applications to the future technology nodes and their timing as projected in the ‘ITRS 2001’ are depicted in Fig. 6. A major global consensus now has been reached that extreme UV (EUV) with an imaging wavelength of 13 nm is the most favourite potential candidate for the next generation lithography technology. With a 13 nm imaging wavelength which actually corresponds to soft X-rays rather than to ultraviolet light, completely new materials in the area of
Fig. 6. Potential lithography techniques for future technology nodes.
376
W. M. Arden / Current Opinion in Solid State and Materials Science 6 (2002) 371–377
imaging optics, mask substrates and absorbers, and resists have to be developed. Their future introduction into volume manufacturing will impose a great challenge.
7. Material requirements The future development of the IC industry puts forward major challenges to the material research scientists. Although silicon substrate materials will remain the dominant material in the IC industry for the next fifteen years, both physical and technological limitations are demanding for the introduction of new materials both in the frontend as well as in the interconnect and backend processing area of semiconductor manufacturing. ASIC and microprocessor applications are pushing the material innovation in the gate stack and interconnect technology, whereas in the memory area the continuous scaling of memory cell sizes drives the introduction of high k dielectric materials for DRAMs and ferroelectric materials for non-volatile memories. In lithography new materials will be required for imaging resists as well as for mask substrates and projection lens elements, as for example CaF 2 for 157 nm projection.
8. Summary of key challenges In order to fulfill the future projections of the ‘ITRS 2001’ roadmap, many challenges and potential roadblocks are to be resolved. Some of the major issues in future semiconductor technologies are summarized in Fig. 7. A key question is whether the overall cost trend and target of 30% reduction in cost per function and year can be achieved in future in view of the increasing expenses for research and development and the rising investment cost
for manufacturing equipment. In the technology area the major challenges are in the field of lithography with the migration from optical to extreme UV systems, in the field of the device due to the introduction of new materials for gate and gate dielectric and the implementation of ‘nonclassical’ CMOS-based device structures, and in the field of interconnect because of the increasing dominance of the parasitic RC delay. The rapid progress in semiconductor technology evolution leads to enormous challenges on the part of integrated circuit design demanding for rapid improvement in design productivity, the integration of multiple functionalities in complex systems-on-chip (SoC) and in their verification and testing.
9. Outlook The International Technology Roadmap for Semiconductors gives a long term projection of key requirements and specifications for the next fifteen years in silicon technology. Based on the projection of historic trends in the semiconductor industry and on the technical assessment of future potential solutions in the field of technology, the ‘ITRS 2001’ edition gives specific projections down to the year of 2016. In Fig. 8 some of the key parameters and characteristics of integrated circuit devices are highlighted for the year of 2016 which might be comprehended as a long term vision for the evolution of the semiconductor technology in the next fifteen years. We can envision dynamic memories with 64 Gigabit storage capacity and minimum feature sizes of 22 nm, microprocessor chips with 6 billion transistors, a maximum operation frequency of 28 Gigahertz and a minimum device gate length of 9 nm, and a system-on-chip with a pad pitch of 20 mm, manufactured on silicon wafers with
Fig. 7. Key challenges for future semiconductor technologies (SOI5silicon on insulator, SoC5system on chip).
W. M. Arden / Current Opinion in Solid State and Materials Science 6 (2002) 371–377
377
extreme UV is the most viable candidate for the next generation imaging system. In order to overcome limitations in overall chip performance as imposed by conventional CMOS scaling, new materials in both the frontend and interconnect processing area will be introduced together with more sophisticated device engineering. In the long term new ‘non-classical’ CMOS-based device structures are to be implemented to fulfill the continuous demand for performance increase and cost decrease in the IC industry. Silicon based technology will remain the mainstream semiconductor technology for at least two more decades.
Fig. 8. Vision of the ‘ITRS 2001’ roadmap for the year of 2016.
450 mm diameter, packaged with a maximum number of 4700 pins and operated at 0.4 volts supply voltage.
10. Conclusion As a global effort the ITRS is developed to address challenges and potential solutions for the semiconductor industry in the next fifteen years. The methodology and the hierarchical approach of the definition of future requirements of the IC industry in the ITRS have been described. Future limitations in device performance and memory cell scaling are driving forces for accelerated feature size scaling. Optical lithography will be pushed to its limits,
Acknowledgements The provision of some of the figures of this article by Toshitaka Fukushima from Fujitsu Corporation, Werner Klingenstein from Infineon Technologies, Paolo Garjini from Intel, and the SIA (Semiconductor Industry Association of USA) who has the copyright of the contents of the ITRS, is highly appreciated.
References [1] Moore G. Electronics Magazine 1965;(35th anniversary edition). [2] Moore G. Developing the integrated circuit,. PC Magazine 1997;(25th March). [3] ITRS Web-Site: http: / / public.itrs.net /