The low-frequency noise behaviour of silicon-on-insulator technologies

World abstracts on microelectronics and reliability istics make the MCM's a powerful integration technology for module development, but the intrinsic construction of the MCM's may cause significant problems when testing has to be performed. Because of this, new cost-effective test methodologies are expected for MCM's that will be built on the MCM substrate. These test structures on the MCM substrate will be integrated if cost-effective solutions are possible. 7. SEMICONDUCTOR INTEGRATED CIRCUITS, DEVICES AND MATERIALS

Periodic boundary conditions for the numerical analysis of semiconductor devices. S. P. LEPKOWSKI. Electron Technology, Warsaw, Poland, 1996, 29(1), 29. In the numerical analysis of semiconductor device equations we have to introduce the artificial boundaries, which do not exit in the real devices. The artificial boundaries, commonly described by the homogeneous Neumann conditions (reflecting boundary conditions) cause accuracy problems, when they intersect the p - n junction. We have analysed the numerical error introduced by the application of the artificial, reflecting boundary conditions in the cases of the intersection with heterojunctions. The unphysical fluctuations in the potential and carrier distributions have been shown in places, where the heterojunctions cross the artificial boundaries. The application of periodic boundary conditions has been proposed to remove the error introduced by the reflecting boundaries. A simple implementation of the periodic boundary conditions to the limited element method has been presented and improvement in accuracy of the solution has been shown.

1289

isolation from each other by screening caused by the gate electrode. Capture and emission in such small structures are subject to Coulomb blocking and enhancement effects of several hundred meV at room temperature. Single interface traps may be used as randomly located atomic probes in the MOS channel.

The low-frequency noise behaviour of silicon-oninsulator technologies. E. SIMOEN and C. CLAEYS. Solid-State Electronics, 1996, 39(7), 949. In this overview, the low-frequency noise behaviour of devices fabricated in silicon-on-insulator technologies is described. The different potential noise sources are analysed and illustrated by experimental results, mainly obtained on MOSFETs. Some SOl-specific noise behaviour is highlighted, as for instance the kink-related excess low-frequency noise overshoot. It is shown, furthermore, that SO1 MOSFETs suffer from so-called random telegraph signals, which can originate from the front- or the back-gate dielectric, or from defects located in the thin Si active layer. The impact of the substrate type (SIMOX, bonded, Z M R , . . . ) is discussed. At the same time, it is shown that the used technology and device structure can have a pronounced effect on the LF noise performance. Finally, the response of SOl MOSFETs on ionizing radiation (Ts, X-rays . . . . ) is studied through the LF noise degradation, in view of radiation-hardened applications.

Depth profile analysis of porous Si film by ERDA using a A E - E detector telescope. D. K. AVASTHI,S. K. HUI, E. T. SUBRAMANYIYAMand B. R. MEHTA. Vacuum, 1996, 47(9), 1061. A complete analytical study, as well as depth profiling of the constituent elements of a porous Si layer have been carried out by elastic recoil detection analysis using 100 MeV Ag ions and a A E - E detector telescope. Quantitative estimates of elements H, C, N, O, F, Mg and Si in a porous Si film have been made. The analysis of data indicates that the lowest detection limit of the technique is 8 × 10-4at% with an inaccuracy of 15%.

Electrical measurement of silicon film and oxide thicknesses in partially depleted SO1 technologies. B. M. TENBROEK, W. REDMAN-WHITE,M. S. L. LEE and M. J. UREN. Solid-State Electronics, 1996, 39(7), 1011. This paper discusses the electrical measurement of silicon film, gate oxide and buried oxide thicknesses in partially depleted SO1 CMOS technologies. For the first time a technique is presented that allows extraction of all three thicknesses, as well as the average silicon film doping concentration, using static threshold voltage measurements only. All measurements and extraction procedures can easily be fully automated, making this method suitable for both accurate parameter extraction and process control. The results obtained with this new technique have been verified by SEM cross-section measurement and a comparison is made with other electrical techniques.

Single-electron trapping in sub-/~m sized MOSFETs. M. SCHULTZ and H. H. MUELLER. Electron Technology, Warsaw, Poland, 1996, 29(1), 5. In sub-#m metal-oxide-semiconductor field-effect transistors (MOSFETs), the trapping and emission of single inversion carriers at the Si-SiO2 interface is visible as a discrete fluctuation of the channel conductance known as a random telegraph signal (RTS). The RTS is the major contribution to the total noise present in the device during operation. Electron traps in sub-/~m MOSFETs are individually observed due to their low total number in the small device area and due to their

Low-temperature impurity breakdown in semiconductors: an approach towards efficient device simulation. R. E. KUNZ, E. SCHOLL, R. NURNBERG and H. GAJEWSKI. Solid-State Electronics, 1996, 39(8), 1155. The spatio-temporal dynamics of threshold switching from a nearly insulating to a high-conducting state in the regime of impurity impact ionization breakdown in semiconductors is studied by means of a simulation scheme that combines the drift-diffusion approach with Monte Carlo simulations of the generation-recombination parameters. One-dimensional simulations yield a three-stage scenario for the breakdown