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The Operation of Microcomputer Control Systems Performing Hardware Emulation
Copyright © IFAC 3, System Approach for Development Rabat, Morocco, 1980
THE OPERATION OF MICROCOMPUTER CONTROL SYSTEMS PERFORMING HARDWARE EMULATION T.
J.
Kobylarz
Department of Electrical Engineering, University of Petroleum and Minerals, Dhahran, Saudi Arabia
Abstract. A frequent complaint by design engineers, regarding microcomputer utilization, is the difficulty they encounter during programmlng. Certainly higher level languages, such as FORTRAN, BASIC, and PL/M have relieved this burden. However, these languages still require an abstract association, and sometimes compl icated interface desi gn, between the microcomputer and the real time peripherals. A preferable approach is a higher level lan~uage which allows the microcomputer to be viewed as an assembly of buildin9 blocks for which a design engineer has strong familiarity; e.g. gates, flip flops, integrators, analog filters, etc. That is, to utilize a crosscompiler, which accepts inputs tantamount to a schematic, and generates a microcomputer object code which will emulate the terminal characteristics of the schematic. The operation of microcomputers which perform such hardware emulation is the subject matter of this paper. Keywords. Microprocessors; programming languages; compilers; digital control; computer hardware. INTRODUCTION
limited to only five hardware elements, all digital, and 17 total instructions. Four of these elements perform combinational logic. The fifth is a J-K flip flop. Because the project is ongoing, the repertoire of elements will probably be larger at the time this paper is being read. The first thrust in element expansion will be digital. These are simpler to emulate and entail less microcomputer overhead memory. A second phase is being considered which exoands to the emulation of continuous elements; e.g. amplifiers, integrators, filters, function generators, etc.
There is no doubt that microcomputers are experiencing a remarkable growth in useage. Their applications appear almost unbounded. Nevertheless, one obstacle has prevented an even more rapid growth. This obstacle is the difficulty in formulating and writing programs. Difficulties arise from two reasons; 1. the programmin9 languages are incompatible with the design procedures generally used for the real time systems to which a microcomputer interfaces, 2. the design engineers have been trained and thereby more naturally reason in the mathematics concerned with the real time systems. The remedy to this problem is to eliminate the need for using an alien language and unorthodox mathematics in programming a microcomputer. This now leads to the research described in this paper. It concerns the operation of a microcomputer which has been programmed by a cross-compiler havinq user input data in a format akin to a schematic of a real time system. Byemulating the input/output terminal properties of the system specified within the schematic, the microcomputer appears as merely additional system hardware. Hith such a facility, a design engineer is permitted to perform all of his work in his more natural domain of treating systems in terms of block diagrams.
The underlying principal of operation is the state variable approach (Kobylarz, 1968 and McCluskey, 1965). The fundamental representation of this approach is shown in Fig. 1. ,ll,lthough a digital system is implied, analog systems are also representable by replacing the delay with integration and replacing the combinational logic with instantaneous function generation. This universality of Fig. 1 is quite important. It suggests that the basis of operation can be maintained, to an approximation, for emulation of continuous elements. Quantization in amplitude and in time are the main reasons for an approximation. The basic operating principle of Fig. 1 and hence, of the program is straightforward. Consequently no description is provided herein. It is however, important to point out that the oresent inputs I are usually from external peripherals and-that the present states Q are stored within internal merrory. Furtller-
The research and desi gn in the "hardware emulation cross-compiler" is actually at its early stages. The system is presently 501
T. J. Kobylarz
502
ITOre, the functions .f. and .9. are instantaneous (combinational) computations, where .f. produces the output vector! for external peripheral sand .£ produces the "next" state vector Q'. As will be seen later, ! and~' are computed by a program loop. This is termed a "computation cycle". .r.. major significance of the computation cycle is that it represents an implicit clock signal for the emulated system; i.e. each computation cycle is tantamount to a clock cycle.
Fig . 1.
Fundamental viewpoint for emulat i on.
The programming language for the crosscompiler is FORTRAN and therefore can be run on ITOst general purpose computers. However, the object coding is in machine language for a National Semiconductor, 16 bit, PACE microprocessor (National Semiconductor, 1977a). The emulation programs have been run on the PACE "Low Cost Development System" (National Semiconductor, 1977b). There is no alternative but to have the cross-compiler designed for a specific microcomputer type. Nevertheless, the basic principles, described in this paper, can be universally applied to all mi crocomputers. Probably the best way to provide significance to the preceding description is by means of a simple example. Therefore, the next section is concerned with an example. This is followed by sections which contain information relating to the operation of the microcomputer. BLOCK DIAGRAM EXAMPLE The switching elements are each specified by their function and their enumerated input and output nodes of a schematic. The general form is: LABEL, i 1, .. ·, i m, q,n' MneuIOOnic labels are used, such as A for an "and" gate, V for an "or" gate, etc. Although an element type may be used a number of times within a schematic, the cross-compiler writes only one subroutine per element type within the microcomputer program. To economize on memory, no such subroutine is written when an element type is not used. The schematic portrayal is not the only input for the cross-compiler. Other recognizable character strings exist having general form of LABEL, arguments (if any). For example, the labels ID, IH (q,D, q,H) can be used to prescribe the locations of peri-
pheral inputs (outputs) to the switching system being emulated. The first argument represents an address, either in decimal (D suffix) or hexadecimal (H suffix). The remaining arguments indicate the nodes to which the input (output) bits correspond. From 1 to 14 inputs (outputs) can be assigned for each address used. The first designated node is associated with bit 1, the second with bit 2, etc. Bit 0 has a special program significance which precludes its use for peri phera 1 input/output. Labels ID, IH (q,D, q, H) may be repeated, each with a unique address, whenever the quantity of inputs (outputs) exceeds 14. It is not possible to directly transfer an input to an output. This can be accomplished indirectly by means of two cascaded inverters (label N). However, a time delay of one computation cycle will transpire from input to output. At least one input and one output must be specified. It is possible to emulate "real time" operation by means of the time delay operator D. The use of this operator will increase the microcomputer computation cycle time by an amount proportional to the argument. The PACE microprocessor, with a 2.667 MHZ crystal controlled clock, results in a proportionality factor of 60 ~-sec. Because non-negative integers of up to four digits can be designated, a single delay of about 0.6 sec. is achievable. Re-use of the D label permits an algebraic increase to longer delays.
The cross-compiler requires tnat the labels PD or PH must appear exactly once in the cross-compiler input data. The argument establishes the first address of the mi crocomputer program. Either a deci ma 1 (PD) or a hexadecimal (PH) number, but not both, can be specified. The PACE Low Cost Development System requires that the address not be less than (40)16' Two more labels must be described for the example. A Z signifies the final input data card (end of the data set) to the crosscompiler. Obviously it is to be placed at the end of the data set. Blanks may succeed the Z label. Blanks (spaces) or commas (,) should follow all labels and arguments. However, they are never to be placed within a label or argument; e.g. I,D is unacceptable, also 10 5 will be construed as 10,5 and not 105. Successive blanks, as at the end of card, merely iteratively prepare the cross-compiler for a new label or argument. The example of an emulated hardware circuit is shown in Fig . 2. The schematic contains an oscillator, designed to have a real time period of 1 sec., and a divide by three counter (one pulse every 3 sec.). Oscillation is achieved by maintaining node 1 at a constant one val ue. It should be
The Operation of Microcomputer Control Systems
Fi g. 2.
50:
Emulati on e xa""le .
indicated that the J-K flip-flop corresponds to one with a "lagging edge" trigger for a computation cycle. That is to say, a state change occurs at the completion of one computation cycle, but just prior to the succeeding computation cycle. An internal (non-peripheral) address is used for the input to node 1. . The corresponding cross-compiler input data set is: PH,40,IH,3FF,,1, ~ H,1000,2,3,5,6,8,9,0,
7990 J,1,1,2,A, 2,3,4,J,4,4,5,V,5,10,3,N,6, 10"
V,5,6,7,A,2,7,8,J,8,8,6,A,8,6,9,Z The first card specifies a microcomputer program starting address of (40)16' The node 1 input is bit 1 of the address (3FF)16' Six outputs are selected at the output address (1000)16' Bit 1 corresponds to node 2 of the schematic, ... , bit 6 is used for node 9. A delay of 7990 time units or 479.4 m-sec. is indicated. This value was determined by first specifying 0,0. A time measurement resulted in a half period of 20.6 m-sec. for the clock; thereby enabling the additional delay determination for a 1 HZ clock cycle. The following two cards designate the input/output nodes for the switching elements shown in Fig. 2. The last symbol (Z) terminates reading cards for the cross -compil er input da ta. Of course, control cards precede and succeed input data. The microcomputer program required 246 words of memory, of which 161 are overhead. The extravagance of memory and output hardware for this circuit emulation suggests that it can only be cost effective in more elaborate systems.
states (Q). The program reads these values, either directly or indirectly, when they are necessary for logic computations. Also within the emulation stack are subroutine addresses corresponding to logic elements. As pertinent computations are performed, the microcomputer program will write the evaluations within the emulation stack . The pertinent computations are the present outputs 1, the next states 9.', and va1 ues of schematic nodes which branch to more than one element input point. For example, node 8 of Fig. 2 branches to three input points and its value is written within the stack. Contrarily, node 10 will not have its value written within the emulation stack. Recomputation of nodes having multiple branching is eliminated by such a "write" instruction . After all computations of 1 and Q' have been completed, the states and the inputs are updated. Combinational logic computations are now repeated for new evaluations of 1 and 9.'. The first word of the emulation stack contains a pointer, akin to a computer program counter. The second word contains a value one higher than the stack length. Remaining words correspond to instructions necessary for performing the previously described computations. These latter words are examined in sequence and, by means of relative addressing, the computer can ascertain the conclusion of the evaluations (end of stack) . Two major categories of words exist: 1. read/write and 2. subroutine function . The general bit patterns of these words are shown in Fig. 3. The sign bit (15) distinguishes between the categories. The read/write words are further subdivided into four types ; two for read and two for write. Table i identifies the code used 15 14 ... 11
10
. . .
3 2 I
EMULATION STACK The portion of the microcomputer program which is tailored to a specific switching circuit schematic is the emulation stack. The basic purpose of the emulation stack is to perform the computations suggested by Fig. 1. This stack contains the values of the present inputs (1) and the present
READ/ WRITE 1514
FUNCTION
Fig. 3.
EIIRJlat10n stack b1t patterns.
0
T. J. Kobylarz
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to distinguish the four types. For direct read words, the V bit contains eithe r a present input or a present state val ue. Should V be for a present input, the source TABLE 1 Read/Write Identification Code Bit Identification
o
W
1
0 0 1 1
o o 1
Read V directly. Read V indirectly. Write non-state value into V. Write state value into V.
of this value i s indirectly addresse d by AO and is located in bit B. That is, an input va l ue i s origina l ly secured from ((AO))S' If B=O, then V corresponds to a present state. Its source is a write word, contained in the stack, at the location ((Ao))O' The value in ((AO))O would have been computed in a preceding cycle. Updating V for each computation cycle is a time consuming task. Therefore only one word is reserved for each input or state value. However, such values may be used several times during the combinational logic computations. Indirect reads are employed whenever a value V must be reused. The indirect read secures V from the emulation stack location (B,AO)O' The pertinent computations are stored in V of the write instructions. If such a write instruction corresponds to a computation for a node having branches to more than one switching element, then an indirect read utilizes V at least once. Write instructions for outputs include an indirect address and a bit location ((AO))B for temporary storage of V. The entire word (vector) at ((Ao)) is applied to the output peripheral address when the emulation stack computations have been completed. If a flip-flop state is selected for an output, the microcomputer program will provi de the present (not next) sta te. However, the value of V in a write instruction corresponds to the next state. This signifies that V should be written into the temporary storage ((AO))B just prior, rather than subsequent, to the combinational logic computations. In order to make this distinction, 0=1 for a state va 1 ue in V. The other category of words, in the emulation stack, contain addresses for the emulated element type subroutines. Each unique element type, within the schematic, will *Parantheses are used to indicate the "contents of" in an iterative manner.
have one such subroutine. The values upon which such subroutines operate are stored in two of four accumulator registers. Registers Al and A2 are concatinated (A 2 ,A 1) to form a pushdown stack with (A1)0 at the top and (A 2 )15 at the bottom. The emulation stack operates in (reverse) Polish notation (Knuth, 1969). Hence, equivalent p~r~n theses nesting can be 32 deep. Modlflcations for indirect read and write have been added to improve efficiency of operation. Values read are pushed onto the data stack and values written are pulled off of the data stack. The subroutine functions wi 11 pull off as many arguments as is needed for a computation and push the result onto the data stack. Non-commutative and non-associative operations naturally have the data stack arguments arranged in the requi red order. Outputs of elements within switching networks will frequently branch (fan) out to several other element input points. A mqjor feature of the emulation stack is that it preserves such branching and thereby reduces the amount of intermediate computations. This is accomplished by the indirect reading of prior write instructions. Such an addition to reverse Polish notation is quite simple to implement and it is believed that the procedure can be inferred from an example. Consider the computations of the output node 9 in Fig. 2. The symbo1~ R, R', W, W' will correspond to respectlVe instructions in Table 1. Addresses, where appropriate will be designated by node enumerations. Subroutine function calls are designated as A (for "and"), V (for "or"), and N (for negation). Observe now that nodes, 2, 5, and 6 are present states of the flip-flops and must be initially read directly into the data stack. Assuming all states have been updated, then the partial emulation stack will contain: . .. A,W8,R'5,R'6,N,V,W3,R'8,R'6,A,W9, .. In the preceding, the first symbol A identifies the point at which node 8 is computed. The next instruction pulls this value from the data stack and stores it in the V bit of the emulation stack W8 instruction. Following this are instructions to indirectly read node 5 and node 6 values into the data stack. After inverting the node 6 value, an "or" computation is made to evaluate node 3. This value is then pulled from the data stack for either future computations or for the peripheral output. Rather than recompute the node 8 value for node 9, the value is now indirectly read into the data stack from the W8 address written in R' 8. Subsequently, the value of node 9 is computed via the A subroutine and written in the emulation stack by means of W9.
The Operation of Microcomputer Control Systems
After executing the final instruction of the emulation stack, the microcomputer provides outputs to peripherals designated in the write instructions. The read instructions are later updated from peripheral inputs and the next state variables. The program now iterates the emulation stack computations. MICROCOMPUTER PROGRAM OPERATION An overview of the microcomputer program operation is presented in this section. The program operates in six basic steps: l. Initialize next states, 2. First updatea. Transfer present states to temporary output storage, b. Transfer input values to emulation stack, c. Transfer next states to present states within emulation stack, 3. Operate emulation stack, 4. Second update- Transfer non-state computations to temporary output storage, 5. Apply outputs at peripheral addresses from temporary storage, 6. Enact computation delay, if selected by user. Return to step 2.
In step 1, the microcomputer program searches the emulation stack for all "write" instructions. When found, a "0" is placed in the V bit. This step therefore initializes all computations which are to be written within the emulation stack. As will be shortly seen, only the ne xt state in it i a 1i za t i on will ha ve a ro 1e in computations . The second step is mainly used to prepare the emulation stack for its computations . In addition, it transfers the previously computed next state (present state) values to the temporary output storage. The transfer of these state values is necessary at this point, since only write instruction values can be placed into the temporary storage and next states cannot be defined outputs. Because of the initialization step, all such values will be "0" in the first pass through the program. The peripheral input values a re inserted into the di rect read "V" bits by means of the associated addresses and bit locations . The states are updated similarly, except tha t the trans fer is from write s ta te instructions to direct read instructions, within the stack, and the bit locations are "0".
After performing the computations defined bll the emulation stack (step 3.), a second update takes place. The purpose of this is to complete the temporary output storage. Prior to step 4. , the temporary output storage contains only those present state values which have been designated as outputs
505
by a user. Step 4. inserts the newly computed values into this storage. When the output temporary storage has been completely updated, the values are subsequently transferred to the output peripherals selected by the user (step 5.). One peripheral at a time is addressed. This means that the new output values occur simultaneously only if they are at the same address. For mUltiple addresses, the time delay between new outputs for succeeding addresses is approximately 0. 16 m-sec. The user should therefore ma ximi ze the number of outputs per address (14) should this delay be appreciable. The output synchronization option can substantially alter the time delay between output addresses. The program will, in this case, not provide a new output until a peripheral has read the old output (bit 15) at the address in question. The program enacts such a wait for each address individually . The final step, prior to an iteration to step 2. , is the enactment of the computation delay. This routine merely cycles through a loop of known time duration for an amount of repetitions specified by the user. The indirect addressing entails the need of stored constants to be used as address pointers. The cross-compiler determines these constants as it composes the microcomputer program. Because of complexity in operation, only the indirect addressing for outputs to peripherals will be described. Assume that the addresses designated within the write instructions of the emulator stack a re A01 ' A02 ' etc. Those ins tructi ons havin g non-zero bit locations (B ¥ 0) imply that the V bit value must be provided to a peripheral. One can consider that the AOj addresses identify rows of an array, as shown in Table 2. The nomenclature "array" is used, since the bits of a word are regarded as columns. Each (A Oj )=AT+2j-1 (j = 1,2, ... ), in the temporary address array. The con ten ts 0 f the tempora ry address array correspond to rows (addresses) of a consecutively arranged tempora ry output array . The con ten ts of the temporary output array alternate with output peripheral address A~j and output ~ '., having 14 meaningful data bits. vectors -J The output updating routine will place V, from the emulation stack into the bit position ((AOj)B of the temporary output i'. rray. An output peri phera 1 recei ves new outputs when a ~ '. vector is transferred to -J the peripheral output array. Because the temporary output array is consecutively arranged in the memory, the latter transfer is accomplished by a loop. It is only necessary to identify the first address AT
506
T. J. Kobylarz
TABLE 2 Indirect Addressing Technique Temporary Temporary Address Array Output Array Address Contents Address Contents AD1
AT + 1
AD
AT + 3
2
AT
tl
AT + 2
A
+
Knuth, D.E., (1969). The Art Of Computer Programming, Vol. 1. Addison-Wesley Publishing Co., Reading, Mass., pp. 336.
A
AT + 1
AT
REFERENCES
3
P~
Peri phera 1 Output Array Address Contents
Kobylarz, T.J., (1968). Nonlinear network computer analysis. G.J. Herskowitz (Ed.), Computer-Aided Integrated Circuit Design, McGraw-Hill Book Co., N.Y. Chap. 6, pp. 197-240. Kobylarz, T.J., (1980). A higher level language to simplify programming of microcomputer control systems. Proceedings of the IEEE Conference on Applications of Mini and Microcomputers, March, pp. 33-39. McCl uskey, E. J., Jr., (1965). Introducti on To The Theory of Switching Circuits. McGraw-Hill Book Co., N.Y. National Semiconductor Corp., (1977a). PACE Microprocessor System Design Manual. Order no. IPC-16A/928, 2900 Semiconductor Drive, Santa Clara, Calif., March.
and the final address AT + N, where N is an odd integer. The program performs (N+1)/2 transfers of (AT+j) into (A T+j-1), j=l,3, ••• , N.
CONCLUSION It is believed that microcomputer hardware emulation is a potentially valueable tool for digital control system designers. Principally because it permits the incorporation of standard design procedures. Furthermore, it allows circuit elements to be regarded as having ideal properties. Therefore, the disconcerting problems arising from propagation delay, hazards, races, fan-out, cross-talk, etc. need not be cons i dered. The most severe limitation is computation time. It is quite apparent that applicability is restricted to slow response systems. System cost suggests that only complex systems should be emulated. However, both slow speed and large cost are governing factors for the utilization of microcomputers in most real time control systems.
National Semiconductor Corp., (1977b). Users Manual, PACE Microprocessor Low Cost Development System. Order no. IPC-16P/301Y, 2900 Semi-conductor Drive, Santa Clara, Calif., June.
THE OPERATION OF MICROCOMPUTER CONTROL SYSTEMS PERFORMING HARDWARE EMULATION T.
J.
Kobylarz
Department of Electrical Engineering, University of Petroleum and Minerals, Dhahran, Saudi Arabia
Abstract. A frequent complaint by design engineers, regarding microcomputer utilization, is the difficulty they encounter during programmlng. Certainly higher level languages, such as FORTRAN, BASIC, and PL/M have relieved this burden. However, these languages still require an abstract association, and sometimes compl icated interface desi gn, between the microcomputer and the real time peripherals. A preferable approach is a higher level lan~uage which allows the microcomputer to be viewed as an assembly of buildin9 blocks for which a design engineer has strong familiarity; e.g. gates, flip flops, integrators, analog filters, etc. That is, to utilize a crosscompiler, which accepts inputs tantamount to a schematic, and generates a microcomputer object code which will emulate the terminal characteristics of the schematic. The operation of microcomputers which perform such hardware emulation is the subject matter of this paper. Keywords. Microprocessors; programming languages; compilers; digital control; computer hardware. INTRODUCTION
limited to only five hardware elements, all digital, and 17 total instructions. Four of these elements perform combinational logic. The fifth is a J-K flip flop. Because the project is ongoing, the repertoire of elements will probably be larger at the time this paper is being read. The first thrust in element expansion will be digital. These are simpler to emulate and entail less microcomputer overhead memory. A second phase is being considered which exoands to the emulation of continuous elements; e.g. amplifiers, integrators, filters, function generators, etc.
There is no doubt that microcomputers are experiencing a remarkable growth in useage. Their applications appear almost unbounded. Nevertheless, one obstacle has prevented an even more rapid growth. This obstacle is the difficulty in formulating and writing programs. Difficulties arise from two reasons; 1. the programmin9 languages are incompatible with the design procedures generally used for the real time systems to which a microcomputer interfaces, 2. the design engineers have been trained and thereby more naturally reason in the mathematics concerned with the real time systems. The remedy to this problem is to eliminate the need for using an alien language and unorthodox mathematics in programming a microcomputer. This now leads to the research described in this paper. It concerns the operation of a microcomputer which has been programmed by a cross-compiler havinq user input data in a format akin to a schematic of a real time system. Byemulating the input/output terminal properties of the system specified within the schematic, the microcomputer appears as merely additional system hardware. Hith such a facility, a design engineer is permitted to perform all of his work in his more natural domain of treating systems in terms of block diagrams.
The underlying principal of operation is the state variable approach (Kobylarz, 1968 and McCluskey, 1965). The fundamental representation of this approach is shown in Fig. 1. ,ll,lthough a digital system is implied, analog systems are also representable by replacing the delay with integration and replacing the combinational logic with instantaneous function generation. This universality of Fig. 1 is quite important. It suggests that the basis of operation can be maintained, to an approximation, for emulation of continuous elements. Quantization in amplitude and in time are the main reasons for an approximation. The basic operating principle of Fig. 1 and hence, of the program is straightforward. Consequently no description is provided herein. It is however, important to point out that the oresent inputs I are usually from external peripherals and-that the present states Q are stored within internal merrory. Furtller-
The research and desi gn in the "hardware emulation cross-compiler" is actually at its early stages. The system is presently 501
T. J. Kobylarz
502
ITOre, the functions .f. and .9. are instantaneous (combinational) computations, where .f. produces the output vector! for external peripheral sand .£ produces the "next" state vector Q'. As will be seen later, ! and~' are computed by a program loop. This is termed a "computation cycle". .r.. major significance of the computation cycle is that it represents an implicit clock signal for the emulated system; i.e. each computation cycle is tantamount to a clock cycle.
Fig . 1.
Fundamental viewpoint for emulat i on.
The programming language for the crosscompiler is FORTRAN and therefore can be run on ITOst general purpose computers. However, the object coding is in machine language for a National Semiconductor, 16 bit, PACE microprocessor (National Semiconductor, 1977a). The emulation programs have been run on the PACE "Low Cost Development System" (National Semiconductor, 1977b). There is no alternative but to have the cross-compiler designed for a specific microcomputer type. Nevertheless, the basic principles, described in this paper, can be universally applied to all mi crocomputers. Probably the best way to provide significance to the preceding description is by means of a simple example. Therefore, the next section is concerned with an example. This is followed by sections which contain information relating to the operation of the microcomputer. BLOCK DIAGRAM EXAMPLE The switching elements are each specified by their function and their enumerated input and output nodes of a schematic. The general form is: LABEL, i 1, .. ·, i m, q,n' MneuIOOnic labels are used, such as A for an "and" gate, V for an "or" gate, etc. Although an element type may be used a number of times within a schematic, the cross-compiler writes only one subroutine per element type within the microcomputer program. To economize on memory, no such subroutine is written when an element type is not used. The schematic portrayal is not the only input for the cross-compiler. Other recognizable character strings exist having general form of LABEL, arguments (if any). For example, the labels ID, IH (q,D, q,H) can be used to prescribe the locations of peri-
pheral inputs (outputs) to the switching system being emulated. The first argument represents an address, either in decimal (D suffix) or hexadecimal (H suffix). The remaining arguments indicate the nodes to which the input (output) bits correspond. From 1 to 14 inputs (outputs) can be assigned for each address used. The first designated node is associated with bit 1, the second with bit 2, etc. Bit 0 has a special program significance which precludes its use for peri phera 1 input/output. Labels ID, IH (q,D, q, H) may be repeated, each with a unique address, whenever the quantity of inputs (outputs) exceeds 14. It is not possible to directly transfer an input to an output. This can be accomplished indirectly by means of two cascaded inverters (label N). However, a time delay of one computation cycle will transpire from input to output. At least one input and one output must be specified. It is possible to emulate "real time" operation by means of the time delay operator D. The use of this operator will increase the microcomputer computation cycle time by an amount proportional to the argument. The PACE microprocessor, with a 2.667 MHZ crystal controlled clock, results in a proportionality factor of 60 ~-sec. Because non-negative integers of up to four digits can be designated, a single delay of about 0.6 sec. is achievable. Re-use of the D label permits an algebraic increase to longer delays.
The cross-compiler requires tnat the labels PD or PH must appear exactly once in the cross-compiler input data. The argument establishes the first address of the mi crocomputer program. Either a deci ma 1 (PD) or a hexadecimal (PH) number, but not both, can be specified. The PACE Low Cost Development System requires that the address not be less than (40)16' Two more labels must be described for the example. A Z signifies the final input data card (end of the data set) to the crosscompiler. Obviously it is to be placed at the end of the data set. Blanks may succeed the Z label. Blanks (spaces) or commas (,) should follow all labels and arguments. However, they are never to be placed within a label or argument; e.g. I,D is unacceptable, also 10 5 will be construed as 10,5 and not 105. Successive blanks, as at the end of card, merely iteratively prepare the cross-compiler for a new label or argument. The example of an emulated hardware circuit is shown in Fig . 2. The schematic contains an oscillator, designed to have a real time period of 1 sec., and a divide by three counter (one pulse every 3 sec.). Oscillation is achieved by maintaining node 1 at a constant one val ue. It should be
The Operation of Microcomputer Control Systems
Fi g. 2.
50:
Emulati on e xa""le .
indicated that the J-K flip-flop corresponds to one with a "lagging edge" trigger for a computation cycle. That is to say, a state change occurs at the completion of one computation cycle, but just prior to the succeeding computation cycle. An internal (non-peripheral) address is used for the input to node 1. . The corresponding cross-compiler input data set is: PH,40,IH,3FF,,1, ~ H,1000,2,3,5,6,8,9,0,
7990 J,1,1,2,A, 2,3,4,J,4,4,5,V,5,10,3,N,6, 10"
V,5,6,7,A,2,7,8,J,8,8,6,A,8,6,9,Z The first card specifies a microcomputer program starting address of (40)16' The node 1 input is bit 1 of the address (3FF)16' Six outputs are selected at the output address (1000)16' Bit 1 corresponds to node 2 of the schematic, ... , bit 6 is used for node 9. A delay of 7990 time units or 479.4 m-sec. is indicated. This value was determined by first specifying 0,0. A time measurement resulted in a half period of 20.6 m-sec. for the clock; thereby enabling the additional delay determination for a 1 HZ clock cycle. The following two cards designate the input/output nodes for the switching elements shown in Fig. 2. The last symbol (Z) terminates reading cards for the cross -compil er input da ta. Of course, control cards precede and succeed input data. The microcomputer program required 246 words of memory, of which 161 are overhead. The extravagance of memory and output hardware for this circuit emulation suggests that it can only be cost effective in more elaborate systems.
states (Q). The program reads these values, either directly or indirectly, when they are necessary for logic computations. Also within the emulation stack are subroutine addresses corresponding to logic elements. As pertinent computations are performed, the microcomputer program will write the evaluations within the emulation stack . The pertinent computations are the present outputs 1, the next states 9.', and va1 ues of schematic nodes which branch to more than one element input point. For example, node 8 of Fig. 2 branches to three input points and its value is written within the stack. Contrarily, node 10 will not have its value written within the emulation stack. Recomputation of nodes having multiple branching is eliminated by such a "write" instruction . After all computations of 1 and Q' have been completed, the states and the inputs are updated. Combinational logic computations are now repeated for new evaluations of 1 and 9.'. The first word of the emulation stack contains a pointer, akin to a computer program counter. The second word contains a value one higher than the stack length. Remaining words correspond to instructions necessary for performing the previously described computations. These latter words are examined in sequence and, by means of relative addressing, the computer can ascertain the conclusion of the evaluations (end of stack) . Two major categories of words exist: 1. read/write and 2. subroutine function . The general bit patterns of these words are shown in Fig. 3. The sign bit (15) distinguishes between the categories. The read/write words are further subdivided into four types ; two for read and two for write. Table i identifies the code used 15 14 ... 11
10
. . .
3 2 I
EMULATION STACK The portion of the microcomputer program which is tailored to a specific switching circuit schematic is the emulation stack. The basic purpose of the emulation stack is to perform the computations suggested by Fig. 1. This stack contains the values of the present inputs (1) and the present
READ/ WRITE 1514
FUNCTION
Fig. 3.
EIIRJlat10n stack b1t patterns.
0
T. J. Kobylarz
504
to distinguish the four types. For direct read words, the V bit contains eithe r a present input or a present state val ue. Should V be for a present input, the source TABLE 1 Read/Write Identification Code Bit Identification
o
W
1
0 0 1 1
o o 1
Read V directly. Read V indirectly. Write non-state value into V. Write state value into V.
of this value i s indirectly addresse d by AO and is located in bit B. That is, an input va l ue i s origina l ly secured from ((AO))S' If B=O, then V corresponds to a present state. Its source is a write word, contained in the stack, at the location ((Ao))O' The value in ((AO))O would have been computed in a preceding cycle. Updating V for each computation cycle is a time consuming task. Therefore only one word is reserved for each input or state value. However, such values may be used several times during the combinational logic computations. Indirect reads are employed whenever a value V must be reused. The indirect read secures V from the emulation stack location (B,AO)O' The pertinent computations are stored in V of the write instructions. If such a write instruction corresponds to a computation for a node having branches to more than one switching element, then an indirect read utilizes V at least once. Write instructions for outputs include an indirect address and a bit location ((AO))B for temporary storage of V. The entire word (vector) at ((Ao)) is applied to the output peripheral address when the emulation stack computations have been completed. If a flip-flop state is selected for an output, the microcomputer program will provi de the present (not next) sta te. However, the value of V in a write instruction corresponds to the next state. This signifies that V should be written into the temporary storage ((AO))B just prior, rather than subsequent, to the combinational logic computations. In order to make this distinction, 0=1 for a state va 1 ue in V. The other category of words, in the emulation stack, contain addresses for the emulated element type subroutines. Each unique element type, within the schematic, will *Parantheses are used to indicate the "contents of" in an iterative manner.
have one such subroutine. The values upon which such subroutines operate are stored in two of four accumulator registers. Registers Al and A2 are concatinated (A 2 ,A 1) to form a pushdown stack with (A1)0 at the top and (A 2 )15 at the bottom. The emulation stack operates in (reverse) Polish notation (Knuth, 1969). Hence, equivalent p~r~n theses nesting can be 32 deep. Modlflcations for indirect read and write have been added to improve efficiency of operation. Values read are pushed onto the data stack and values written are pulled off of the data stack. The subroutine functions wi 11 pull off as many arguments as is needed for a computation and push the result onto the data stack. Non-commutative and non-associative operations naturally have the data stack arguments arranged in the requi red order. Outputs of elements within switching networks will frequently branch (fan) out to several other element input points. A mqjor feature of the emulation stack is that it preserves such branching and thereby reduces the amount of intermediate computations. This is accomplished by the indirect reading of prior write instructions. Such an addition to reverse Polish notation is quite simple to implement and it is believed that the procedure can be inferred from an example. Consider the computations of the output node 9 in Fig. 2. The symbo1~ R, R', W, W' will correspond to respectlVe instructions in Table 1. Addresses, where appropriate will be designated by node enumerations. Subroutine function calls are designated as A (for "and"), V (for "or"), and N (for negation). Observe now that nodes, 2, 5, and 6 are present states of the flip-flops and must be initially read directly into the data stack. Assuming all states have been updated, then the partial emulation stack will contain: . .. A,W8,R'5,R'6,N,V,W3,R'8,R'6,A,W9, .. In the preceding, the first symbol A identifies the point at which node 8 is computed. The next instruction pulls this value from the data stack and stores it in the V bit of the emulation stack W8 instruction. Following this are instructions to indirectly read node 5 and node 6 values into the data stack. After inverting the node 6 value, an "or" computation is made to evaluate node 3. This value is then pulled from the data stack for either future computations or for the peripheral output. Rather than recompute the node 8 value for node 9, the value is now indirectly read into the data stack from the W8 address written in R' 8. Subsequently, the value of node 9 is computed via the A subroutine and written in the emulation stack by means of W9.
The Operation of Microcomputer Control Systems
After executing the final instruction of the emulation stack, the microcomputer provides outputs to peripherals designated in the write instructions. The read instructions are later updated from peripheral inputs and the next state variables. The program now iterates the emulation stack computations. MICROCOMPUTER PROGRAM OPERATION An overview of the microcomputer program operation is presented in this section. The program operates in six basic steps: l. Initialize next states, 2. First updatea. Transfer present states to temporary output storage, b. Transfer input values to emulation stack, c. Transfer next states to present states within emulation stack, 3. Operate emulation stack, 4. Second update- Transfer non-state computations to temporary output storage, 5. Apply outputs at peripheral addresses from temporary storage, 6. Enact computation delay, if selected by user. Return to step 2.
In step 1, the microcomputer program searches the emulation stack for all "write" instructions. When found, a "0" is placed in the V bit. This step therefore initializes all computations which are to be written within the emulation stack. As will be shortly seen, only the ne xt state in it i a 1i za t i on will ha ve a ro 1e in computations . The second step is mainly used to prepare the emulation stack for its computations . In addition, it transfers the previously computed next state (present state) values to the temporary output storage. The transfer of these state values is necessary at this point, since only write instruction values can be placed into the temporary storage and next states cannot be defined outputs. Because of the initialization step, all such values will be "0" in the first pass through the program. The peripheral input values a re inserted into the di rect read "V" bits by means of the associated addresses and bit locations . The states are updated similarly, except tha t the trans fer is from write s ta te instructions to direct read instructions, within the stack, and the bit locations are "0".
After performing the computations defined bll the emulation stack (step 3.), a second update takes place. The purpose of this is to complete the temporary output storage. Prior to step 4. , the temporary output storage contains only those present state values which have been designated as outputs
505
by a user. Step 4. inserts the newly computed values into this storage. When the output temporary storage has been completely updated, the values are subsequently transferred to the output peripherals selected by the user (step 5.). One peripheral at a time is addressed. This means that the new output values occur simultaneously only if they are at the same address. For mUltiple addresses, the time delay between new outputs for succeeding addresses is approximately 0. 16 m-sec. The user should therefore ma ximi ze the number of outputs per address (14) should this delay be appreciable. The output synchronization option can substantially alter the time delay between output addresses. The program will, in this case, not provide a new output until a peripheral has read the old output (bit 15) at the address in question. The program enacts such a wait for each address individually . The final step, prior to an iteration to step 2. , is the enactment of the computation delay. This routine merely cycles through a loop of known time duration for an amount of repetitions specified by the user. The indirect addressing entails the need of stored constants to be used as address pointers. The cross-compiler determines these constants as it composes the microcomputer program. Because of complexity in operation, only the indirect addressing for outputs to peripherals will be described. Assume that the addresses designated within the write instructions of the emulator stack a re A01 ' A02 ' etc. Those ins tructi ons havin g non-zero bit locations (B ¥ 0) imply that the V bit value must be provided to a peripheral. One can consider that the AOj addresses identify rows of an array, as shown in Table 2. The nomenclature "array" is used, since the bits of a word are regarded as columns. Each (A Oj )=AT+2j-1 (j = 1,2, ... ), in the temporary address array. The con ten ts 0 f the tempora ry address array correspond to rows (addresses) of a consecutively arranged tempora ry output array . The con ten ts of the temporary output array alternate with output peripheral address A~j and output ~ '., having 14 meaningful data bits. vectors -J The output updating routine will place V, from the emulation stack into the bit position ((AOj)B of the temporary output i'. rray. An output peri phera 1 recei ves new outputs when a ~ '. vector is transferred to -J the peripheral output array. Because the temporary output array is consecutively arranged in the memory, the latter transfer is accomplished by a loop. It is only necessary to identify the first address AT
506
T. J. Kobylarz
TABLE 2 Indirect Addressing Technique Temporary Temporary Address Array Output Array Address Contents Address Contents AD1
AT + 1
AD
AT + 3
2
AT
tl
AT + 2
A
+
Knuth, D.E., (1969). The Art Of Computer Programming, Vol. 1. Addison-Wesley Publishing Co., Reading, Mass., pp. 336.
A
AT + 1
AT
REFERENCES
3
P~
Peri phera 1 Output Array Address Contents
Kobylarz, T.J., (1968). Nonlinear network computer analysis. G.J. Herskowitz (Ed.), Computer-Aided Integrated Circuit Design, McGraw-Hill Book Co., N.Y. Chap. 6, pp. 197-240. Kobylarz, T.J., (1980). A higher level language to simplify programming of microcomputer control systems. Proceedings of the IEEE Conference on Applications of Mini and Microcomputers, March, pp. 33-39. McCl uskey, E. J., Jr., (1965). Introducti on To The Theory of Switching Circuits. McGraw-Hill Book Co., N.Y. National Semiconductor Corp., (1977a). PACE Microprocessor System Design Manual. Order no. IPC-16A/928, 2900 Semiconductor Drive, Santa Clara, Calif., March.
and the final address AT + N, where N is an odd integer. The program performs (N+1)/2 transfers of (AT+j) into (A T+j-1), j=l,3, ••• , N.
CONCLUSION It is believed that microcomputer hardware emulation is a potentially valueable tool for digital control system designers. Principally because it permits the incorporation of standard design procedures. Furthermore, it allows circuit elements to be regarded as having ideal properties. Therefore, the disconcerting problems arising from propagation delay, hazards, races, fan-out, cross-talk, etc. need not be cons i dered. The most severe limitation is computation time. It is quite apparent that applicability is restricted to slow response systems. System cost suggests that only complex systems should be emulated. However, both slow speed and large cost are governing factors for the utilization of microcomputers in most real time control systems.
National Semiconductor Corp., (1977b). Users Manual, PACE Microprocessor Low Cost Development System. Order no. IPC-16P/301Y, 2900 Semi-conductor Drive, Santa Clara, Calif., June.