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The performance of plastic-encapsulated CMOS microcircuits in a humid environment
World Abstracts on Microclectronics and Reliability A ULA is mere than dlkon. J. A. V ~ z ~ , N . R. CROCKER and J. P. SINGLETON.Fifth Solid State Circuits Conference-ESSCIRC 79, lEE Publn. 178, 51. For many years now the computer industry has been building systems with a large number of printed circuit boards which may contain many hundreds of gates. These boards have been well supported by Design Automation in the areas of coding, electrical loading rules, automatic tracking, logic simulation and automatic test pattern generation. Since LSI offers the advantages of cost, performance and reliability, how should the LSI he structured to take full advantage of Design Automation ? The LSI parts must also have a short development time and hence low development cost, be error free and have a fast turnround from the logic diagram to the samples. It is the purpose of this paper to show that these objectives for LSI can be achieved by using the Uncommitted Logic Array, ULA approach to LSI design. Advances in wafer process control. KLAUS SCHUEGRAF.SolidSt. Technol. 87 (February 1980). A number of new silicon wafer processing techniques have become standard procedures during the past decade, but the coming VLSI and VHSIC will he even more demanding. Hot wall wafer processing systems have been the mainstays of the semiconductor industry. With new developments in temperature and gas flow control and in automated process control, these systems will he able to accommodate dopant deposition and diffusion, oxidation, VCVD and annealing at the high throughput rates and with the energy and costeffectiveness that will be required inthe next few years. Thermal Studies of a plastic dual-in-line package. CURTis MITCHELL and HOWARD M. BV.RG. IEEE Trans. Components, Hybrids Mfg Technol. Chmt-2, (4) 500 (December 1979). The major factors affecting heat flow in a 16 pin plastic dual-in-line package (DIP) are investigated using thermal resistance measurements of packages with various materials and design permutations. Factors explored include the molding compound material, leadframe material and design, die size, wire size, and die bond material. Of these, the leadframe material and molding compound most dramatically impact O:A while the leadframe design plays a secondary role. Other factors are of minor importance. The user's external cooling conditions are very important to properly utilizing a package's thermal capabilities. By optimizing material selection in a standard 16 pin plastic DIP while using natural convection cooling,, its thermal performance can be potentially increased by a factor of three. A factor of seven improvement is possible when using both optimum cooling conditions and superior packaging materials. Experimental investigation of mounting thermal resistance of flatpacks on circuit boards. THOMAS F. MOVlUS, IVAN R. JONES and JAMES M. KALLIS. IEEE Trans. Components, Hybrids Mfg Technol. Chmt-2, (4) 512 (December 1979). Thermal tests were performed on radar digital module circuit boards to measure the thermal effect of various size gaps between the circuit board and the flatpack integrated circuit (IC) case and also the thermal resistance of the circuit board. These IC's are cooled by conduction through the circuit board to an air-cooled heat exchanger. The thermal effect of the gap filled with air, and also filled with an adhesive, was measured. The temperature differences between pairs of locations on the flatpack IC case, particularly between the top and the bottom center, also were meaSured. These tests are described; the test results are presented, discussed, and compared with analytical predictions; and conclusions are given. The key conclusions are that the filler is quite effective in lowering the IC junction temperatures and, in fact, has a larger thermal effect than the gap size. For example, filling a 5-rail (1.27 x 10-*m) gap
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reduces the junction t e m p e r a t e by 12°C, whereas reducing the gap from 5mils (1.27 x I 0 - 4 m ) to 0 reduces it by only 3°C. The combined thermal resistance of the gap and the circuit board is a linear function of the gap. The performance of plutic-oncalmlated CMOS ndemciseuim in a humid emironmam. PbUL W. Pe~rmtSON. IEEE Trans. Components, Hybrids Mfg Technol. Chmt-2, (4) 422 (December 1979). The major portion of this investigation is devoted to accelerated testing of plastic CMOS microcircuits under conditions of high humidity. The test results revealed a high failure rate in sharp contrast to the results of a similar investigation performed on plastic TTL IC's. The program also investigates the effects of coating devices with a common PC card conformal coating and the effects of operation at various bias levels. A comparison is made between the results of short term pressure cooker testing and long term moisture bias life testing. The results of testing over 1300 devices, representing the product of five (5) manufacturers are discussed. Findings of the investigation reveal a higher failure rate for plastic CMOS than plastic TTL. Conformal coating proved to be an insignificant moisture deterrent. The results of 15PSIG, 127°, 48-h testing were observed to correlate with 85°C, 85 % relative humidity (RH), 1,000-h results. Also observed was the improved performance o f CMOS B series devices in moisture compared to the A series. Removal of moisture from the ambient significantly improved the failure rate indicating that moisture was the prime failure cause.
Gold/chrominm metalUzationsfor electronic devices. PAUL H. HOLLOWAY. Solid-St. Technol. 109 (February 1980), The thin films of gold which are applied so extensively in electronic devices are normally deposited over thin films of other metals in two, three or even four component metallization systems. The problems arising in such systems are vividly illustrated in this article on the gold/chromium metalllzation system developed in large measure at the Sandia Laboratories in Albuquerque, New Mexico.
Computer aided design of LSI: an 12L case study. C. P. LINCOLN and R. J. CRISPIN. Fifth Solid State Circuits
Conference--ESSCIRC 79, IEE Publn. 178, 64. This paper describes how a full custom LSI circuit can be designed, laid out and released to fabrication with substantially reduced manual checking by using the STL computer design aids to be described. These comprise a linked suite of programs performing logic simulation, layout rule checking, functional checking and electrical analysis of layouts. To illustrate them, the case history has been chosen of a recent I2L design which comprises some 3,000 gates of random logic performing multiplexing and code conversion at 4 MHz. The functional definition of this circuit was 10 A4 pages of TTL gates and MSI logic. The initial gate count allowing 6 for a D flip-flop, 7 for an adder, 6 for a multiplexer and 2 for exclusive or, come to 2,200. A 500-pieosecoud system design capability. S. HOLL(~K.
Fifh Solid State Circuits Conference--ESSCIRC 79, lEE Publn. 178, 79. A family of ultra-high speed devices has been designed to maximise the performance of digital systems. The family is based on MSI parts developed on the high performance Plessey Process III(V); these circuits offer local gate delays of 500 picoseconds and flip-flop clock rates of over 500 MHz, and enable overall "system" gate delays of less than one nanosecond to be achieved. The performance of a scaled version of one of these circuits has improved these gate delays by a further 150 picoseconds; this improvement has been achieved by the reduction of minimum geometries to three microns. By the introduction of fundamental improvements to the basic transistor structure, and by optimisation of geometries, it will be possible to reduce the local gate delay to 200 picoseconds and the system gate delay to 500 picoseconds.
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reduces the junction t e m p e r a t e by 12°C, whereas reducing the gap from 5mils (1.27 x I 0 - 4 m ) to 0 reduces it by only 3°C. The combined thermal resistance of the gap and the circuit board is a linear function of the gap. The performance of plutic-oncalmlated CMOS ndemciseuim in a humid emironmam. PbUL W. Pe~rmtSON. IEEE Trans. Components, Hybrids Mfg Technol. Chmt-2, (4) 422 (December 1979). The major portion of this investigation is devoted to accelerated testing of plastic CMOS microcircuits under conditions of high humidity. The test results revealed a high failure rate in sharp contrast to the results of a similar investigation performed on plastic TTL IC's. The program also investigates the effects of coating devices with a common PC card conformal coating and the effects of operation at various bias levels. A comparison is made between the results of short term pressure cooker testing and long term moisture bias life testing. The results of testing over 1300 devices, representing the product of five (5) manufacturers are discussed. Findings of the investigation reveal a higher failure rate for plastic CMOS than plastic TTL. Conformal coating proved to be an insignificant moisture deterrent. The results of 15PSIG, 127°, 48-h testing were observed to correlate with 85°C, 85 % relative humidity (RH), 1,000-h results. Also observed was the improved performance o f CMOS B series devices in moisture compared to the A series. Removal of moisture from the ambient significantly improved the failure rate indicating that moisture was the prime failure cause.
Gold/chrominm metalUzationsfor electronic devices. PAUL H. HOLLOWAY. Solid-St. Technol. 109 (February 1980), The thin films of gold which are applied so extensively in electronic devices are normally deposited over thin films of other metals in two, three or even four component metallization systems. The problems arising in such systems are vividly illustrated in this article on the gold/chromium metalllzation system developed in large measure at the Sandia Laboratories in Albuquerque, New Mexico.
Computer aided design of LSI: an 12L case study. C. P. LINCOLN and R. J. CRISPIN. Fifth Solid State Circuits
Conference--ESSCIRC 79, IEE Publn. 178, 64. This paper describes how a full custom LSI circuit can be designed, laid out and released to fabrication with substantially reduced manual checking by using the STL computer design aids to be described. These comprise a linked suite of programs performing logic simulation, layout rule checking, functional checking and electrical analysis of layouts. To illustrate them, the case history has been chosen of a recent I2L design which comprises some 3,000 gates of random logic performing multiplexing and code conversion at 4 MHz. The functional definition of this circuit was 10 A4 pages of TTL gates and MSI logic. The initial gate count allowing 6 for a D flip-flop, 7 for an adder, 6 for a multiplexer and 2 for exclusive or, come to 2,200. A 500-pieosecoud system design capability. S. HOLL(~K.
Fifh Solid State Circuits Conference--ESSCIRC 79, lEE Publn. 178, 79. A family of ultra-high speed devices has been designed to maximise the performance of digital systems. The family is based on MSI parts developed on the high performance Plessey Process III(V); these circuits offer local gate delays of 500 picoseconds and flip-flop clock rates of over 500 MHz, and enable overall "system" gate delays of less than one nanosecond to be achieved. The performance of a scaled version of one of these circuits has improved these gate delays by a further 150 picoseconds; this improvement has been achieved by the reduction of minimum geometries to three microns. By the introduction of fundamental improvements to the basic transistor structure, and by optimisation of geometries, it will be possible to reduce the local gate delay to 200 picoseconds and the system gate delay to 500 picoseconds.