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The present state, future and possibilities or application of the principles of magnetic bubble memories
World Abstracts on Microelectronics and Reliability
Some graphical methods for maintenance planning. Bo. BERMAN.Proc. IEEE Reliab. Maintainab. Syrup. Philadelphia, 18-20 Jan. 1977. p. 467. The failure of a unit in operation may in many situations be costly and even dangerous. If we have reason to believe that older units are more prone to fail than younger ones it may be advantageous to replace a used unit by a new one at some age. In some situations we have information not only about the age of a unit under evaluation but also about its state. If we have reason to believe that the proneness to fail depends on the state of the unit, then it seems reasonable to use this in planning preventive maintenance. We presume that a cost is associated with each replacement and that an additional cost is incurred at each failure in service. The problem is to find a good control strategy
355
that ,balances the cost of replacements with the cost of failures and results in a minimum total long-run average cost per unit time. In most situations we know rather little about the failure model and therefore we have to use observational data as much as possible. We suggest the use of a new simple graphical method to obtain a reasonable nonparametric age replacement policy. The method is based on observational data using the Total Time on Test plot. The Total Time on Test plot was recently introduced by Barlow and Campo (1975). It is also indicated that the suggested method may be generalized in some situations where we have information about the state of the unit under evaluation to give a basis for the planning of maintenance "on condition".
4. MICROELECTRONICS--GENERAL The present state, future and possibilities of application of the principles of magnetic bubble memories. R. STRAUBEL. Nachrichtentechnik Elektronik 27, 400 (1977). An explanation of the basic principle of magnetic bubble memories is followed by a description of the present technical state and technical memory parameters to be expected up to 1980, which may be taken into account by the user. Potential fields of application of these new memories are mentioned, and an outlook is given on more recent principles of memories still in an experimental stage.
The CCDs future takes on a bright hue. LARRYARMSTRONG. Electronics p. 65 (10 November 1977). 65-k devices, now available as samples from semiconductor houses, will initially replace fixed-head and floppy disk storage. IEDM heralds breakthroughs in LSI fabrication, power discretes. LAWRENCE LATMAN and LUCINDA MATTERA. Electronics p. 109 (8 December 1977). To "the semiconductor specialists gathering at this week's International Electron Devices Meeting in Washington, D. C., the main focus of
interest is finer microcircuit pattern geometry, with smaller, more powerful discrete devices running a close second. If device pattern techniques have always been prominent on IEDM agendas, this year the subject has new urgency, as designers push device technology to new levels of performance and packing density. In power devices, also, there are four major breakthroughs.
Selected bibliography on integrated injection logic (I2L)/ merged transistor logic (MTL) technology. J. L. STONE and J. C. PLUNKETT.Solid St. Electron Devices 1, (6) 179 (November 1977). The rapid advances that have been made over the last five years in the development of I2L/MTL technology and the introduction of numerous new applications for this technology have been paced by an expanding list of technical publications. The accelerating rate at which new material appears has necessitated the collection of the following bibliography. The length has been kept to manageable proportions and it is hoped that it will be updated at regular intervals. While every effort has been made to make the list as complete as possible, inevitably important articles may have been overlooked.
5. MICROELECTRONICS DESIGN A N D CONSTRUCTION Analysis of the merged charge memory (MCM) cell. H.S. LEE. IBM JI Resl Dev. 21, (5) 402 (Sept. 1977). This paper describes a new MOS dynamic RAM (Random-Access Memory) cell which utilizes a merged surface charge transistor structure. The merged charge memory (MCM) cell uses a polysilicon electrode as both a bit sense line and common plate for a column of storage capacitors. The MCM structure is self-aligned, contactless and free of closely spaced p - n junctions. Its spatial density approaches the conceptual limit of the intersection formed by two orthogonal lines or 4W 2 where W is the minimum geometry feature. The cell area utilization efficiency is improved because of this simplicity. Preliminary experimental results and ASTAPsimulations based on the charge control equivalent circuit for a dynamic potential well are described. Implications for chip design constraints are discussed, and the advantages and limitations of MCM are highlighted where appropriate. V-groove MOS (VMOS) enhancement load logic. FRANK E. HOLMES. Solid-St. Electron. 20, p. 775 (1977). The characteristics of V-groove metal-oxide-semiconductor (VMOS) enhancement load logic circuits are investigated. Two new load structures are proposed and their characteristics studied. Measurements are presented for experimental VMOS logic arrays. VMOS logic is shown to be capable of producing high 1Sacking density circuits with standard
photolithographic tolerances and no degradation of electrical characteristics.
Functional modelling of floating substrate MOS structures. M. I. ELMASRYand A. G. ELDIN. Int. J. Electron. 43, (5) 433 (1977). The floating substrate of MOS structures (e.g. MOS/SOS) produces two kinks (current steps) in the d.c. drain current-drain voltage characteristic. In this paper the locus of each kink is determined. The value of the current step is calculated and the effect of the different parameters on the locus and the amount of the current step is discussed for the two kinks. The locus of the two kinks are compared with experimental measurements for silicon-onsapphire MOS devices. Good agreement has been observed. The analysis has been applied to determine the effect of the current kinks on both the transfer characteristics and the transient response of CMOS/SOS inverter circuits. Modifications of a MOS model for CAD is presented to simulate the MOS/SOS structure, taking into account the effect of both current kinks.
Integrated injection logic using non-optimized processes. M. CROOKE, T. C. VERSTER, A. G. K. LUTSCH, R. F. GREYVENSTEIN and J. D. STULTtNG. Microelectronics 8, (3) 23 (1977). It is shown that even a simple bipolar process is quite capable of producing very-low-power "standard"
Some graphical methods for maintenance planning. Bo. BERMAN.Proc. IEEE Reliab. Maintainab. Syrup. Philadelphia, 18-20 Jan. 1977. p. 467. The failure of a unit in operation may in many situations be costly and even dangerous. If we have reason to believe that older units are more prone to fail than younger ones it may be advantageous to replace a used unit by a new one at some age. In some situations we have information not only about the age of a unit under evaluation but also about its state. If we have reason to believe that the proneness to fail depends on the state of the unit, then it seems reasonable to use this in planning preventive maintenance. We presume that a cost is associated with each replacement and that an additional cost is incurred at each failure in service. The problem is to find a good control strategy
355
that ,balances the cost of replacements with the cost of failures and results in a minimum total long-run average cost per unit time. In most situations we know rather little about the failure model and therefore we have to use observational data as much as possible. We suggest the use of a new simple graphical method to obtain a reasonable nonparametric age replacement policy. The method is based on observational data using the Total Time on Test plot. The Total Time on Test plot was recently introduced by Barlow and Campo (1975). It is also indicated that the suggested method may be generalized in some situations where we have information about the state of the unit under evaluation to give a basis for the planning of maintenance "on condition".
4. MICROELECTRONICS--GENERAL The present state, future and possibilities of application of the principles of magnetic bubble memories. R. STRAUBEL. Nachrichtentechnik Elektronik 27, 400 (1977). An explanation of the basic principle of magnetic bubble memories is followed by a description of the present technical state and technical memory parameters to be expected up to 1980, which may be taken into account by the user. Potential fields of application of these new memories are mentioned, and an outlook is given on more recent principles of memories still in an experimental stage.
The CCDs future takes on a bright hue. LARRYARMSTRONG. Electronics p. 65 (10 November 1977). 65-k devices, now available as samples from semiconductor houses, will initially replace fixed-head and floppy disk storage. IEDM heralds breakthroughs in LSI fabrication, power discretes. LAWRENCE LATMAN and LUCINDA MATTERA. Electronics p. 109 (8 December 1977). To "the semiconductor specialists gathering at this week's International Electron Devices Meeting in Washington, D. C., the main focus of
interest is finer microcircuit pattern geometry, with smaller, more powerful discrete devices running a close second. If device pattern techniques have always been prominent on IEDM agendas, this year the subject has new urgency, as designers push device technology to new levels of performance and packing density. In power devices, also, there are four major breakthroughs.
Selected bibliography on integrated injection logic (I2L)/ merged transistor logic (MTL) technology. J. L. STONE and J. C. PLUNKETT.Solid St. Electron Devices 1, (6) 179 (November 1977). The rapid advances that have been made over the last five years in the development of I2L/MTL technology and the introduction of numerous new applications for this technology have been paced by an expanding list of technical publications. The accelerating rate at which new material appears has necessitated the collection of the following bibliography. The length has been kept to manageable proportions and it is hoped that it will be updated at regular intervals. While every effort has been made to make the list as complete as possible, inevitably important articles may have been overlooked.
5. MICROELECTRONICS DESIGN A N D CONSTRUCTION Analysis of the merged charge memory (MCM) cell. H.S. LEE. IBM JI Resl Dev. 21, (5) 402 (Sept. 1977). This paper describes a new MOS dynamic RAM (Random-Access Memory) cell which utilizes a merged surface charge transistor structure. The merged charge memory (MCM) cell uses a polysilicon electrode as both a bit sense line and common plate for a column of storage capacitors. The MCM structure is self-aligned, contactless and free of closely spaced p - n junctions. Its spatial density approaches the conceptual limit of the intersection formed by two orthogonal lines or 4W 2 where W is the minimum geometry feature. The cell area utilization efficiency is improved because of this simplicity. Preliminary experimental results and ASTAPsimulations based on the charge control equivalent circuit for a dynamic potential well are described. Implications for chip design constraints are discussed, and the advantages and limitations of MCM are highlighted where appropriate. V-groove MOS (VMOS) enhancement load logic. FRANK E. HOLMES. Solid-St. Electron. 20, p. 775 (1977). The characteristics of V-groove metal-oxide-semiconductor (VMOS) enhancement load logic circuits are investigated. Two new load structures are proposed and their characteristics studied. Measurements are presented for experimental VMOS logic arrays. VMOS logic is shown to be capable of producing high 1Sacking density circuits with standard
photolithographic tolerances and no degradation of electrical characteristics.
Functional modelling of floating substrate MOS structures. M. I. ELMASRYand A. G. ELDIN. Int. J. Electron. 43, (5) 433 (1977). The floating substrate of MOS structures (e.g. MOS/SOS) produces two kinks (current steps) in the d.c. drain current-drain voltage characteristic. In this paper the locus of each kink is determined. The value of the current step is calculated and the effect of the different parameters on the locus and the amount of the current step is discussed for the two kinks. The locus of the two kinks are compared with experimental measurements for silicon-onsapphire MOS devices. Good agreement has been observed. The analysis has been applied to determine the effect of the current kinks on both the transfer characteristics and the transient response of CMOS/SOS inverter circuits. Modifications of a MOS model for CAD is presented to simulate the MOS/SOS structure, taking into account the effect of both current kinks.
Integrated injection logic using non-optimized processes. M. CROOKE, T. C. VERSTER, A. G. K. LUTSCH, R. F. GREYVENSTEIN and J. D. STULTtNG. Microelectronics 8, (3) 23 (1977). It is shown that even a simple bipolar process is quite capable of producing very-low-power "standard"