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The silicon foundry interface
586
World Abstracts on Microelectronics and Reliability
Efficiency of censored reliability studies. R J. BROOKS.IEEE Trans. Reliab. R-32 (5), 504 (1983). The s-expected gain in information provided by an experiment is used to help assess the loss of s-information through censoring in reliability studies. Large sample, relative s-efliciencies of censored studies compared to complete studies are calculated assuming the lifetime distribution is Weibull. For example, when q, the
proportion (if type II censoring) or s-expected proportion (if type I censoring) of complete lifetimes to be censored, is up to about 20 %, a censored study requires roughly 200q % extra observations for the same s-expected gain in s-information as a complete study. The results allow an ordering of studies with different sample sizes and stopping points with respect to their s-expected gains in s-information.
4. M I C R O E L E C T R O N I C S - - G E N E R A L Increased capacity, automation, materials' purity highlight Semicon East. Semiconductor Int. 154 ( August 1984). Supplying the demand for high quality integrated circuits is the challenge to be addressed as the semiconductor industry assembles on the East Coast. Military's VHSIC chips quickstep into final phase. WESLEYR. IVERSEN. Electron. Week 17 (3 September 1984). Contracts should be awarded this month for second-phase submicrometer chips as first-phase chips are readied to report for duty in hardware. Gallium arsenide: a practical alternative to silicon. PETER H. SINGER. Semiconductor Int. 80 (October 1984). The advantages of higher speed and improved performance make GaAs an attractive alternative to silicon for some applications. Wafer scale integration: an appraisal. RON ISCOFF. Semiconductor Int. 62 (September 1984). Wafer scale integration appears to be a technology ahead of its time. Academic interest in WSI is keen, but commercial development is limited. Transition to one micron technology: part 3. PIETER BURGGRAAE. Semiconductor Int. 98 (July 1984). Cooperation between materials suppliers and users, particularly for new test methodologies and more detailed material specifications, is essential for one micron technology. Transition to one micron technology: part 5. Semiconductor Int. 88 (September 1984). Solving testability problems will require new combinations of device and testability designs. GaAs crystal growth trends. PIETER BURGGRAAF. Semiconductor Int. 58 (October 1984). Still low on the "learning 5. M I C R O E L E C T R O N I C S - - D E S I G N The effect of porosity on mechanical, electrical and thermal characteristics of conductive die-attach adhesives. RICHARD H. ESTES. Solid St. Technol. 191 (August 1984). The results of a twelve month research study are reported and indicate that die attach adhesives containing volatile materials are mechanically inferior, prone to outgassing, and exhibit impaired electrical/thermal performance compared to that of the 100% solid, silver filled, electrically conductive epoxies that are presently on the market. The studies included outgassing, lap shear/die shear strengths, thermal resistance measurements in powered devices, electrical resistivities (volume and surface) and current density. Sputtered Tl-doped AL SI for enhanced interconnect reliability. F. FISCHER and F. NEPPL. Proc. IEEE Reliab. Phys. Conj. 190 (1984). It is shown that an A1-Si-Ti alloy containing 0.1-0.2 wt. % Ti used as an IC-interconnect material reaches the electromigration strength of A1-Si-Cu and simultaneously avoids the disadvantages of AI-Si-Cu like enhanced corrosion susceptibility or dry etching problems. The stabilizing effect of Ti is demonstrated by life testing and
curve," significant advances are being made in GaAs crystal growth. Trends in computer aided design systems. Semiconductor Int. 144 (August 1984). Survey results indicate a high interest in new design software and the ability to network workstations. Electronics assembly robots: U.S. vs Japan. Solid St. Technol. 119 (July 1984). Electronic assembly robots are installed inline in Japan while this penetration has barely started in the U.S. The Japanese robots are simple and cheap to operate. The rationale for their introduction has been to substitute one robot to one manual assembler. The preferred Japanese configuration is the SCARA, and the major application is for odd-form dedicated assembly. The U.S. vendors are developing flexible robots with computerized vision, high-level languages, and multiconfiguration end-effectors. Three tables are presented: U.S. and Japanese robot manufacturer capabilities, high level language and vision capabilities of U.S. robot vendors, and current and future electronic assembly robot specifications. CAD systems: mapping out tomorrow's ICs. Semiconductor lnt. 96 (August 1984). Automated design systems allow IC designers to develop more advanced devices with increased productivity. Transition to one micron technology: part 4. PIETER BURGGRAAF. Semiconductor Int. 110 (August 1984). Some future trends in the packaging of high density ICs are seen in today's efforts to improve packaging performance. The silicon foundry interface. TERRENCE A. JOHNSON. Semiconductor Int. 109 (October 1984). Silicon foundries provide an option to the high cost of starting a new production line. Additionally, they offer the customer new design resources and technologies. AND CONSTRUCTION additionally by monitoring changes of residual resistivity and heat transfer to the substrate during temperature current stress. Automated wafer processing using robots. MITCHELL WEISS. Solid St. Technol. 163 (July 1984). The design of a system which uses robots for automated wet processing of semiconductor wafers is discussed. Topics covered include: layout, operation, controls, etc. The implementation of a robotics program for automating front end processing is examined. Constraint solver for generalized IC layout. PETER W. COOK. I B M J. Res. Dev. 28 (5), 581 (1984). This paper presents a constraint solver suitable for use in a general symbolic IC layout system. The essential features of the constraint solver, which is intended to place few restrictions on the source of the constraints to be solved, are that it accommodate mixed equality and inequality constraints, that it allow selective "maximization" of variables, that it proceed with any number of variables given user-defined values, and that it fail to produce a solution only when no solution exists. These
World Abstracts on Microelectronics and Reliability
Efficiency of censored reliability studies. R J. BROOKS.IEEE Trans. Reliab. R-32 (5), 504 (1983). The s-expected gain in information provided by an experiment is used to help assess the loss of s-information through censoring in reliability studies. Large sample, relative s-efliciencies of censored studies compared to complete studies are calculated assuming the lifetime distribution is Weibull. For example, when q, the
proportion (if type II censoring) or s-expected proportion (if type I censoring) of complete lifetimes to be censored, is up to about 20 %, a censored study requires roughly 200q % extra observations for the same s-expected gain in s-information as a complete study. The results allow an ordering of studies with different sample sizes and stopping points with respect to their s-expected gains in s-information.
4. M I C R O E L E C T R O N I C S - - G E N E R A L Increased capacity, automation, materials' purity highlight Semicon East. Semiconductor Int. 154 ( August 1984). Supplying the demand for high quality integrated circuits is the challenge to be addressed as the semiconductor industry assembles on the East Coast. Military's VHSIC chips quickstep into final phase. WESLEYR. IVERSEN. Electron. Week 17 (3 September 1984). Contracts should be awarded this month for second-phase submicrometer chips as first-phase chips are readied to report for duty in hardware. Gallium arsenide: a practical alternative to silicon. PETER H. SINGER. Semiconductor Int. 80 (October 1984). The advantages of higher speed and improved performance make GaAs an attractive alternative to silicon for some applications. Wafer scale integration: an appraisal. RON ISCOFF. Semiconductor Int. 62 (September 1984). Wafer scale integration appears to be a technology ahead of its time. Academic interest in WSI is keen, but commercial development is limited. Transition to one micron technology: part 3. PIETER BURGGRAAE. Semiconductor Int. 98 (July 1984). Cooperation between materials suppliers and users, particularly for new test methodologies and more detailed material specifications, is essential for one micron technology. Transition to one micron technology: part 5. Semiconductor Int. 88 (September 1984). Solving testability problems will require new combinations of device and testability designs. GaAs crystal growth trends. PIETER BURGGRAAF. Semiconductor Int. 58 (October 1984). Still low on the "learning 5. M I C R O E L E C T R O N I C S - - D E S I G N The effect of porosity on mechanical, electrical and thermal characteristics of conductive die-attach adhesives. RICHARD H. ESTES. Solid St. Technol. 191 (August 1984). The results of a twelve month research study are reported and indicate that die attach adhesives containing volatile materials are mechanically inferior, prone to outgassing, and exhibit impaired electrical/thermal performance compared to that of the 100% solid, silver filled, electrically conductive epoxies that are presently on the market. The studies included outgassing, lap shear/die shear strengths, thermal resistance measurements in powered devices, electrical resistivities (volume and surface) and current density. Sputtered Tl-doped AL SI for enhanced interconnect reliability. F. FISCHER and F. NEPPL. Proc. IEEE Reliab. Phys. Conj. 190 (1984). It is shown that an A1-Si-Ti alloy containing 0.1-0.2 wt. % Ti used as an IC-interconnect material reaches the electromigration strength of A1-Si-Cu and simultaneously avoids the disadvantages of AI-Si-Cu like enhanced corrosion susceptibility or dry etching problems. The stabilizing effect of Ti is demonstrated by life testing and
curve," significant advances are being made in GaAs crystal growth. Trends in computer aided design systems. Semiconductor Int. 144 (August 1984). Survey results indicate a high interest in new design software and the ability to network workstations. Electronics assembly robots: U.S. vs Japan. Solid St. Technol. 119 (July 1984). Electronic assembly robots are installed inline in Japan while this penetration has barely started in the U.S. The Japanese robots are simple and cheap to operate. The rationale for their introduction has been to substitute one robot to one manual assembler. The preferred Japanese configuration is the SCARA, and the major application is for odd-form dedicated assembly. The U.S. vendors are developing flexible robots with computerized vision, high-level languages, and multiconfiguration end-effectors. Three tables are presented: U.S. and Japanese robot manufacturer capabilities, high level language and vision capabilities of U.S. robot vendors, and current and future electronic assembly robot specifications. CAD systems: mapping out tomorrow's ICs. Semiconductor lnt. 96 (August 1984). Automated design systems allow IC designers to develop more advanced devices with increased productivity. Transition to one micron technology: part 4. PIETER BURGGRAAF. Semiconductor Int. 110 (August 1984). Some future trends in the packaging of high density ICs are seen in today's efforts to improve packaging performance. The silicon foundry interface. TERRENCE A. JOHNSON. Semiconductor Int. 109 (October 1984). Silicon foundries provide an option to the high cost of starting a new production line. Additionally, they offer the customer new design resources and technologies. AND CONSTRUCTION additionally by monitoring changes of residual resistivity and heat transfer to the substrate during temperature current stress. Automated wafer processing using robots. MITCHELL WEISS. Solid St. Technol. 163 (July 1984). The design of a system which uses robots for automated wet processing of semiconductor wafers is discussed. Topics covered include: layout, operation, controls, etc. The implementation of a robotics program for automating front end processing is examined. Constraint solver for generalized IC layout. PETER W. COOK. I B M J. Res. Dev. 28 (5), 581 (1984). This paper presents a constraint solver suitable for use in a general symbolic IC layout system. The essential features of the constraint solver, which is intended to place few restrictions on the source of the constraints to be solved, are that it accommodate mixed equality and inequality constraints, that it allow selective "maximization" of variables, that it proceed with any number of variables given user-defined values, and that it fail to produce a solution only when no solution exists. These