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The switch of the worst case on NBTI and hot-carrier reliability for 0.13 μm pMOSFETs
Applied Surface Science 254 (2008) 6186–6189
Contents lists available at ScienceDirect
Applied Surface Science journal homepage: www.elsevier.com/locate/apsusc
The switch of the worst case on NBTI and hot-carrier reliability for 0.13 mm pMOSFETs Chia-Hao Tu a,*, Shuang-Yuan Chen a,**, Meng-Hong Lin a, Mu-Chun Wang a,b, Ssu-Han Wu c, Sam chou c, Joe Ko c, Heng-Sheng Huang a a b c
Institute of Mechatronic Engineering, National Taipei University of Technology, 1, Sec. 3, Chung-Hsiao E. Rd., Taipei 10608, Taiwan Department and Institute of Electronic Engineering, Minghsin University of Science and Technology, 1, Hsin-Hsin Road, Hsin-Feng, Hsin-Chu 304, Taiwan Special Technology Division, United Microelectronics Corporation, 3, Li-Hsin Road 2, Science-Based Industrial Park, Hsin-Chu city 300, Taiwan
A R T I C L E I N F O
A B S T R A C T
Article history:
This investigation describes experiments on two sizes of p-channel metal-oxide-semiconductor fieldeffect-transistors (pMOSFETs), to study the negative bias temperature instability (NBTI) and hot-carrier (HC) induced degradation. This work demonstrates that the worst condition for pMOSFETs under HC tests occurs in CHC (channel HC, stressed at Vg = Vd) mode at high temperature. This study also shows that the worst degradation of pMOSFETs should occur in NBTI. This inference is based on a comparison of results for forward saturation current (Ids,f) and reverse saturation current (Ids,r) obtained in NBTI and HC tests. ß 2008 Published by Elsevier B.V.
Available online 16 March 2008 PACS: 85.30.z 73.20.r 73.40.c 85.40.e 73.40.QV Keywords: NBTI CHC The worst case pMOSFETs Forward saturation current (Ids,f) Reverse saturation current (Ids,r)
1. Introduction MOSFET technology continues to be scaled down to the deepsubmicron and nano-meter generations, and the shrinking of device channel length and gate oxide thickness is causing more reliability problems. Various stress modes have been contrived to investigate these reliability issues. They include DAHC (drain avalanche hot-carrier, Vg stressed at maximal substrate current), CHC (channel HC, stressed at Vg = Vd), and NBTI (negative bias temperature instability and Vg biased at stress voltage (Vstress), but Vd = Vs = Vsub = ground). Another important factor to be considered is temperature effect. Current and future generations of CMOS integrated circuits inevitably operate and will operate at high temperature. State-ofthe-art microprocessors have an average power of density over 100 W/cm2 and the junction temperatures often exceed 100 8C [1–
* Corresponding author. Tel.: +886 2 2771 2171x2031; fax: +886 2 2771 7318. ** Corresponding author. Tel.: +886 2 2771 2171x2011; fax: +886 2 2771 7318. E-mail addresses: [email protected] (C.-H. Tu), [email protected] (S.-Y. Chen). 0169-4332/$ – see front matter ß 2008 Published by Elsevier B.V. doi:10.1016/j.apsusc.2008.02.181
3]. The hot-carrier (HC) effect is a critical reliability problem [4]. Early studies indicated that pMOSFETs showed the worst degradation at DAHC and low temperature [5,6]. However, a recent investigation reported that the worst case involves switching from DAHC to CHC and from low to high temperature [7]. In recent years, NBTI-induced pMOSFET degradation has become more serious, as feature dimensions have continued to shrink. Therefore, understanding the severity of these reliability issues is important [8–11]. This study examines the degradation of pMOSFETs in different stress modes at various stress voltages and temperatures. The results show that the worst case of pMOSFET reliability tests should be switched from CHC to NBTI. 2. Experiments Test devices were fabricated using the 0.13 mm dual-gate oxide process of UMC. The pMOSFETs used in these experiments have an effective gate length Leff = 120 nm with a gate oxide thickness of 32 A˚ (I/O devices) or Leff = 90 nm with a gate oxide thickness of 20 A˚ (core devices) – all with width W = 10 mm. DAHC, CHC, and NBTI stress modes were applied to I/O and core devices. The
C.-H. Tu et al. / Applied Surface Science 254 (2008) 6186–6189
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Table 1 Stress conditions Gate length Oxide thickness
90 nm (core device) 20 A˚
Stress voltage (V)
Vg@Isub,max (DAHC) Vg (NBTI) Vg = Vd (CHC)
0.95 2.0 2.0
Temperature (8C) Time (s)
120 nm (I/O device) 32 A˚
1.05 2.2 2.2
1.1 2.4 2.4
1.225 3.2 3.2
1.3 3.4 3.4
1.375 3.6 3.6
25, 75, 125 to 3000 (HC), 10000 (NBTI)
Table 2 Measurement conditions
Id,lin Id,sat
90 nm (core device)
120 nm (I/O device)
Vg (V)
Vd (V)
Vg (V)
Vd (V)
1.2 1.2
0.05 1.2
1.8 1.8
0.05 1.8
threshold voltages were measured using the constant current method. Tables 1 and 2 summarize the stress and measurement conditions. 3. Results and discussion Figs. 1 and 2 plot the degradation curves for Vt,lin shifts and Id degradation ratio in three stress modes for I/O devices. CHC degrades the most and the critical condition moves from room temperature to 75 8C. The order of degradation is CHC > DAHC > NBTI. For core devices, Figs. 3 and 4 show that the degradation order is CHC > NBTI > DAHC. Therefore, NBTI becomes more serious degradation because of the scaling-down of devices. However, the most notable fact is that the high-temperature case is the most critical. Models form other studies ([7], Eq. (1)) and ([12], Eq. (2)) were used to express the Vt,lin shifts of CHC and NBTI, respectively, as follows.
DV t;lin ¼ Atn eðb=V d þg =kTÞ
(1)
DV t;lin ¼ Atn eðaV g þðg =kTÞÞ
(2)
Fig. 1. Vt,lin shifts of I/O devices versus stress time at 25 8C.
Fig. 2. Id degradation of I/O devices after 3000 s of HC stress and after 10000 s of NBTI stress versus temperature.
where DVt,lin is the threshold voltage shift; Vg and Vd are the bias voltages; A is the fitting constant; a is the acceleration factor; b and g are critical potential and energy related to degradation probability; k is Boltzmann’s constant; T is stress temperature; t is stress time, and n is the exponent of time power law. The foregoing parameters are extracted from the above test results and presented in Table 3. Based on Eqs. (1) and (2), Figs. 5 and 6 show the predicted Vt,lin shifts of core devices in NBTI and HC stress modes. Notably, the NBTIinduced Vt,lin shift is about 0.8 mV at Vcc = 1.2 V and T = 25 8C.
Fig. 3. Vt,lin shifts of core devices versus stress time at various temperatures.
C.-H. Tu et al. / Applied Surface Science 254 (2008) 6186–6189
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Fig. 4. Id degradation of core devices after 3000 s of HC stress and after 10,000 s of NBTI stress versus temperature.
Fig. 6. Vt,lin shifts of core devices on log scale versus 1/jVdj in DAHC and CHC stress modes at various temperatures.
Table 3 Comparison of critical parameters Stress mode
DAHC
CHC
NBTI
n
I/O core
0.42 0.38
0.32 0.26
0.25 0.25
Core
a (V1) b (V) g (eV)
None 31.47 0.0815
None 14.35 0.057
1.672 None 0.135
However, the predicted Vt,lin shifts of the same devices are only 0.4 mV and 0.03 mV, respectively, for CHC and DAHC stress modes under the same stress conditions, except that Vd = 0 V for NBTI stress. If the criterion for device failure is defined as the Vt,lin shift of 10 mV, then according to Eqs. (1) and (2), the lifetime of the core devices can be calculated, as plotted in Figs. 7 and 8. Now, a comparison of the predicted values at 1.2 V of normal operating voltage, that the expected lifetimes are in the order DAHC > CHC > 10 years > NBTI. Hence, NBTI is presumed to
Fig. 7. Lifetime of core devices versus jVgj in NBTI stress mode.
Fig. 5. Vt,lin shifts of core devices on log scale versus jVgj in NBTI stress mode at various temperatures.
exhibit the worst degradation for pMOSFETs of the 0.13 technology and smaller. Comparing the n values of the I/O and core devices in three stress modes indicates that n decreased. This result implies that HC induced interface states (DNit) not only near the drain region but also all over the interface area. Fig. 9 plots calculated Vt,lin shifts of NBTI and CHC stress modes versus stress voltages. Clearly, temperature substantially influences NBTI but only weakly affects CHC. Furthermore, the curves of the Vt,lin shifts in the two stress modes intersect with each other, separating the figure into regions I and II. In region I, NBTI is the worst case; in region II, CHC is the worst case. The switch from region II to I involves the switch of the dominant mechanism from lateral electrical field to the temperature effect and vertical field. To elucidate the degradation mechanism, Fig. 10 reveals that the degradations of the forward saturation current (Ids,f) and the
C.-H. Tu et al. / Applied Surface Science 254 (2008) 6186–6189
Fig. 8. Lifetime of core devices versus 1/jVdj in DAHC and CHC stress modes.
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Fig. 10. Reverse saturation current (Ids,r) and forward saturation current (Ids,f) versus stress time in three stress modes.
4. Conclusions The worst case of pMOSFET reliability is observed to switch from CHC to NBTI at the operating voltage. The probable switching mechanism is that NBTI creates the interface states along the whole Si–insulator interface. Moreover, it is strongly dependent on the temperature rises and vertical field. CHC only damages the interface near the drain side and depends strongly on the lateral field. With device shrinkage, the influence of the temperature effect and vertical field becomes stronger than that of the lateral field. Therefore, NBTI effect should become the worst case of all the advanced generations. Acknowledgment The authors would like to thank the National Science Council of the Republic of China, Taiwan, for supporting this research under Contract NSC 96-2221-E-027-113. Fig. 9. Vt,lin shifts of core devices versus stress voltage. The cross points of two corresponding curves separate the figure into two regions.
References
reverse saturation current (Ids,r) in three stress modes. Early studies demonstrated that the HC-induced degradations of Ids,r were more severe than those of Ids,f [13]. The difference between the degradation of Ids,f and that of Ids,r gradually increases. Therefore, the curves do not degrade in parallel. However, the degradation curves between Ids,f and Ids,r show a parallel tendency in CHC mode. This phenomenon presumably indicates that the stress-induced device damage region expanded to cover all of the interface area. The behavior of the HC-induced pMOSFET degradation is similar to the NBTI effect. Hence, the CHC mode is worse than DAHC because of the combination of HC and NBTI effects. This fact can also be inferred from the time exponent n in Table 3. Since n value is involved with hydrogen diffusion in the gate dielectrics [14], a larger n, such as in the DAHC case in Table 3 indicates damage closer to the drain edge. In contrast, the smaller n in the NBTI case implies that the damage region is along the whole interface. Therefore, CHC is the case between DAHC and NBTI, but closer to NBTI.
[1] P. Aminzadeh, M. Alavi, D. Scharfetter, VLSI (1998). [2] E. Li, E. Rosenbaum, L.F. Register, J. Tao, P. Fang, IRPS (2000). [3] K. Xiu, M. Ketchen, Thermal modeling of a small extreme power density, IEEE 2004 Eletronic Components and Technology Conference [4] R. Woltjer, G.M. Paulzen, H.G. Pomp, H. Lifka, P.H. Woerlee, IEEE Trans. ED (1995) 109. [5] M. Song, K.P. MacWilliams, J.C.S. Woo, IEEE Trans. ED 44 (1997) 268. [6] N. Koike, K. Tatsuuma, IEEE Trans. ED Mater. Reliab. 4 (2004) 457. [7] S.Y. Chen, C.H. Tu, J.C. Lin, P.W. Kao, W.C. Lin, Z.W. Jhou, et al., IIRW Final Report (2006) 163. [8] Neeraj K. Jha, P. Sahajananda Reddy, Dinesh K. Sharma, and V. Ramgopal Rao, NBTI degradation and its impact for analog circuit reliability, IEEE TRANSACTIONS ON ELECTRON DEVICES 52 (2005) 2609. [9] J.H. Stathis, S. Zafar, Microelectron. Reliab. 46 (2006) 270. [10] Bipul C. Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad A. Alam, and Kaushik Roy, Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 26 (2007) 743 [11] D. Varghese, G. Gupta, L.M. Lakkimsetti, D. Saha, K. Ahmed, F. Nouri, S. Mahapatra, IEEE Trans. ED 54 (2007) 1672. [12] S. Chakravarthi, A.T. Krishnan, V. Reddy, C.F. Machala, S. Krishnan, A comprehensive framework for predictive modeling of negative bias temperature instability, IEEE 42th Annual International Reliability Physics Symposium, Phoenix, 2004. [13] T. Hori, Gate Dielectrics and MOS ULSIs, Springer, Berlin, 1997, 123. [14] H. Kufluoglu, M.A. Alam, IEDM (2004) 531.
Contents lists available at ScienceDirect
Applied Surface Science journal homepage: www.elsevier.com/locate/apsusc
The switch of the worst case on NBTI and hot-carrier reliability for 0.13 mm pMOSFETs Chia-Hao Tu a,*, Shuang-Yuan Chen a,**, Meng-Hong Lin a, Mu-Chun Wang a,b, Ssu-Han Wu c, Sam chou c, Joe Ko c, Heng-Sheng Huang a a b c
Institute of Mechatronic Engineering, National Taipei University of Technology, 1, Sec. 3, Chung-Hsiao E. Rd., Taipei 10608, Taiwan Department and Institute of Electronic Engineering, Minghsin University of Science and Technology, 1, Hsin-Hsin Road, Hsin-Feng, Hsin-Chu 304, Taiwan Special Technology Division, United Microelectronics Corporation, 3, Li-Hsin Road 2, Science-Based Industrial Park, Hsin-Chu city 300, Taiwan
A R T I C L E I N F O
A B S T R A C T
Article history:
This investigation describes experiments on two sizes of p-channel metal-oxide-semiconductor fieldeffect-transistors (pMOSFETs), to study the negative bias temperature instability (NBTI) and hot-carrier (HC) induced degradation. This work demonstrates that the worst condition for pMOSFETs under HC tests occurs in CHC (channel HC, stressed at Vg = Vd) mode at high temperature. This study also shows that the worst degradation of pMOSFETs should occur in NBTI. This inference is based on a comparison of results for forward saturation current (Ids,f) and reverse saturation current (Ids,r) obtained in NBTI and HC tests. ß 2008 Published by Elsevier B.V.
Available online 16 March 2008 PACS: 85.30.z 73.20.r 73.40.c 85.40.e 73.40.QV Keywords: NBTI CHC The worst case pMOSFETs Forward saturation current (Ids,f) Reverse saturation current (Ids,r)
1. Introduction MOSFET technology continues to be scaled down to the deepsubmicron and nano-meter generations, and the shrinking of device channel length and gate oxide thickness is causing more reliability problems. Various stress modes have been contrived to investigate these reliability issues. They include DAHC (drain avalanche hot-carrier, Vg stressed at maximal substrate current), CHC (channel HC, stressed at Vg = Vd), and NBTI (negative bias temperature instability and Vg biased at stress voltage (Vstress), but Vd = Vs = Vsub = ground). Another important factor to be considered is temperature effect. Current and future generations of CMOS integrated circuits inevitably operate and will operate at high temperature. State-ofthe-art microprocessors have an average power of density over 100 W/cm2 and the junction temperatures often exceed 100 8C [1–
* Corresponding author. Tel.: +886 2 2771 2171x2031; fax: +886 2 2771 7318. ** Corresponding author. Tel.: +886 2 2771 2171x2011; fax: +886 2 2771 7318. E-mail addresses: [email protected] (C.-H. Tu), [email protected] (S.-Y. Chen). 0169-4332/$ – see front matter ß 2008 Published by Elsevier B.V. doi:10.1016/j.apsusc.2008.02.181
3]. The hot-carrier (HC) effect is a critical reliability problem [4]. Early studies indicated that pMOSFETs showed the worst degradation at DAHC and low temperature [5,6]. However, a recent investigation reported that the worst case involves switching from DAHC to CHC and from low to high temperature [7]. In recent years, NBTI-induced pMOSFET degradation has become more serious, as feature dimensions have continued to shrink. Therefore, understanding the severity of these reliability issues is important [8–11]. This study examines the degradation of pMOSFETs in different stress modes at various stress voltages and temperatures. The results show that the worst case of pMOSFET reliability tests should be switched from CHC to NBTI. 2. Experiments Test devices were fabricated using the 0.13 mm dual-gate oxide process of UMC. The pMOSFETs used in these experiments have an effective gate length Leff = 120 nm with a gate oxide thickness of 32 A˚ (I/O devices) or Leff = 90 nm with a gate oxide thickness of 20 A˚ (core devices) – all with width W = 10 mm. DAHC, CHC, and NBTI stress modes were applied to I/O and core devices. The
C.-H. Tu et al. / Applied Surface Science 254 (2008) 6186–6189
6187
Table 1 Stress conditions Gate length Oxide thickness
90 nm (core device) 20 A˚
Stress voltage (V)
Vg@Isub,max (DAHC) Vg (NBTI) Vg = Vd (CHC)
0.95 2.0 2.0
Temperature (8C) Time (s)
120 nm (I/O device) 32 A˚
1.05 2.2 2.2
1.1 2.4 2.4
1.225 3.2 3.2
1.3 3.4 3.4
1.375 3.6 3.6
25, 75, 125 to 3000 (HC), 10000 (NBTI)
Table 2 Measurement conditions
Id,lin Id,sat
90 nm (core device)
120 nm (I/O device)
Vg (V)
Vd (V)
Vg (V)
Vd (V)
1.2 1.2
0.05 1.2
1.8 1.8
0.05 1.8
threshold voltages were measured using the constant current method. Tables 1 and 2 summarize the stress and measurement conditions. 3. Results and discussion Figs. 1 and 2 plot the degradation curves for Vt,lin shifts and Id degradation ratio in three stress modes for I/O devices. CHC degrades the most and the critical condition moves from room temperature to 75 8C. The order of degradation is CHC > DAHC > NBTI. For core devices, Figs. 3 and 4 show that the degradation order is CHC > NBTI > DAHC. Therefore, NBTI becomes more serious degradation because of the scaling-down of devices. However, the most notable fact is that the high-temperature case is the most critical. Models form other studies ([7], Eq. (1)) and ([12], Eq. (2)) were used to express the Vt,lin shifts of CHC and NBTI, respectively, as follows.
DV t;lin ¼ Atn eðb=V d þg =kTÞ
(1)
DV t;lin ¼ Atn eðaV g þðg =kTÞÞ
(2)
Fig. 1. Vt,lin shifts of I/O devices versus stress time at 25 8C.
Fig. 2. Id degradation of I/O devices after 3000 s of HC stress and after 10000 s of NBTI stress versus temperature.
where DVt,lin is the threshold voltage shift; Vg and Vd are the bias voltages; A is the fitting constant; a is the acceleration factor; b and g are critical potential and energy related to degradation probability; k is Boltzmann’s constant; T is stress temperature; t is stress time, and n is the exponent of time power law. The foregoing parameters are extracted from the above test results and presented in Table 3. Based on Eqs. (1) and (2), Figs. 5 and 6 show the predicted Vt,lin shifts of core devices in NBTI and HC stress modes. Notably, the NBTIinduced Vt,lin shift is about 0.8 mV at Vcc = 1.2 V and T = 25 8C.
Fig. 3. Vt,lin shifts of core devices versus stress time at various temperatures.
C.-H. Tu et al. / Applied Surface Science 254 (2008) 6186–6189
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Fig. 4. Id degradation of core devices after 3000 s of HC stress and after 10,000 s of NBTI stress versus temperature.
Fig. 6. Vt,lin shifts of core devices on log scale versus 1/jVdj in DAHC and CHC stress modes at various temperatures.
Table 3 Comparison of critical parameters Stress mode
DAHC
CHC
NBTI
n
I/O core
0.42 0.38
0.32 0.26
0.25 0.25
Core
a (V1) b (V) g (eV)
None 31.47 0.0815
None 14.35 0.057
1.672 None 0.135
However, the predicted Vt,lin shifts of the same devices are only 0.4 mV and 0.03 mV, respectively, for CHC and DAHC stress modes under the same stress conditions, except that Vd = 0 V for NBTI stress. If the criterion for device failure is defined as the Vt,lin shift of 10 mV, then according to Eqs. (1) and (2), the lifetime of the core devices can be calculated, as plotted in Figs. 7 and 8. Now, a comparison of the predicted values at 1.2 V of normal operating voltage, that the expected lifetimes are in the order DAHC > CHC > 10 years > NBTI. Hence, NBTI is presumed to
Fig. 7. Lifetime of core devices versus jVgj in NBTI stress mode.
Fig. 5. Vt,lin shifts of core devices on log scale versus jVgj in NBTI stress mode at various temperatures.
exhibit the worst degradation for pMOSFETs of the 0.13 technology and smaller. Comparing the n values of the I/O and core devices in three stress modes indicates that n decreased. This result implies that HC induced interface states (DNit) not only near the drain region but also all over the interface area. Fig. 9 plots calculated Vt,lin shifts of NBTI and CHC stress modes versus stress voltages. Clearly, temperature substantially influences NBTI but only weakly affects CHC. Furthermore, the curves of the Vt,lin shifts in the two stress modes intersect with each other, separating the figure into regions I and II. In region I, NBTI is the worst case; in region II, CHC is the worst case. The switch from region II to I involves the switch of the dominant mechanism from lateral electrical field to the temperature effect and vertical field. To elucidate the degradation mechanism, Fig. 10 reveals that the degradations of the forward saturation current (Ids,f) and the
C.-H. Tu et al. / Applied Surface Science 254 (2008) 6186–6189
Fig. 8. Lifetime of core devices versus 1/jVdj in DAHC and CHC stress modes.
6189
Fig. 10. Reverse saturation current (Ids,r) and forward saturation current (Ids,f) versus stress time in three stress modes.
4. Conclusions The worst case of pMOSFET reliability is observed to switch from CHC to NBTI at the operating voltage. The probable switching mechanism is that NBTI creates the interface states along the whole Si–insulator interface. Moreover, it is strongly dependent on the temperature rises and vertical field. CHC only damages the interface near the drain side and depends strongly on the lateral field. With device shrinkage, the influence of the temperature effect and vertical field becomes stronger than that of the lateral field. Therefore, NBTI effect should become the worst case of all the advanced generations. Acknowledgment The authors would like to thank the National Science Council of the Republic of China, Taiwan, for supporting this research under Contract NSC 96-2221-E-027-113. Fig. 9. Vt,lin shifts of core devices versus stress voltage. The cross points of two corresponding curves separate the figure into two regions.
References
reverse saturation current (Ids,r) in three stress modes. Early studies demonstrated that the HC-induced degradations of Ids,r were more severe than those of Ids,f [13]. The difference between the degradation of Ids,f and that of Ids,r gradually increases. Therefore, the curves do not degrade in parallel. However, the degradation curves between Ids,f and Ids,r show a parallel tendency in CHC mode. This phenomenon presumably indicates that the stress-induced device damage region expanded to cover all of the interface area. The behavior of the HC-induced pMOSFET degradation is similar to the NBTI effect. Hence, the CHC mode is worse than DAHC because of the combination of HC and NBTI effects. This fact can also be inferred from the time exponent n in Table 3. Since n value is involved with hydrogen diffusion in the gate dielectrics [14], a larger n, such as in the DAHC case in Table 3 indicates damage closer to the drain edge. In contrast, the smaller n in the NBTI case implies that the damage region is along the whole interface. Therefore, CHC is the case between DAHC and NBTI, but closer to NBTI.
[1] P. Aminzadeh, M. Alavi, D. Scharfetter, VLSI (1998). [2] E. Li, E. Rosenbaum, L.F. Register, J. Tao, P. Fang, IRPS (2000). [3] K. Xiu, M. Ketchen, Thermal modeling of a small extreme power density, IEEE 2004 Eletronic Components and Technology Conference [4] R. Woltjer, G.M. Paulzen, H.G. Pomp, H. Lifka, P.H. Woerlee, IEEE Trans. ED (1995) 109. [5] M. Song, K.P. MacWilliams, J.C.S. Woo, IEEE Trans. ED 44 (1997) 268. [6] N. Koike, K. Tatsuuma, IEEE Trans. ED Mater. Reliab. 4 (2004) 457. [7] S.Y. Chen, C.H. Tu, J.C. Lin, P.W. Kao, W.C. Lin, Z.W. Jhou, et al., IIRW Final Report (2006) 163. [8] Neeraj K. Jha, P. Sahajananda Reddy, Dinesh K. Sharma, and V. Ramgopal Rao, NBTI degradation and its impact for analog circuit reliability, IEEE TRANSACTIONS ON ELECTRON DEVICES 52 (2005) 2609. [9] J.H. Stathis, S. Zafar, Microelectron. Reliab. 46 (2006) 270. [10] Bipul C. Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad A. Alam, and Kaushik Roy, Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 26 (2007) 743 [11] D. Varghese, G. Gupta, L.M. Lakkimsetti, D. Saha, K. Ahmed, F. Nouri, S. Mahapatra, IEEE Trans. ED 54 (2007) 1672. [12] S. Chakravarthi, A.T. Krishnan, V. Reddy, C.F. Machala, S. Krishnan, A comprehensive framework for predictive modeling of negative bias temperature instability, IEEE 42th Annual International Reliability Physics Symposium, Phoenix, 2004. [13] T. Hori, Gate Dielectrics and MOS ULSIs, Springer, Berlin, 1997, 123. [14] H. Kufluoglu, M.A. Alam, IEDM (2004) 531.