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The temperature-dependence of threshold voltage of N-MOSFETs with nonuniform substrate doping
PII:
Solid-State Electronics Vol. 42, No. 10, pp. 1799±1805, 1998 # 1998 Elsevier Science Ltd. All rights reserved Printed in Great Britain 0038-1101/98/$ - see front matter S0038-1101(98)00155-5
THE TEMPERATURE-DEPENDENCE OF THRESHOLD VOLTAGE OF N-MOSFETs WITH NONUNIFORM SUBSTRATE DOPING H. H. CHEN, S. H. TSENG and J. GONG Department of Electrical Engineering, National Tsing Hua University, Kuang-Fu Road, Hsinchu, Taiwan 300, R.O.C (Received 19 August 1997; in revised form 12 December 1997) AbstractÐIn this work, the temperature eect on threshold voltage of a MOSFET with nonuniformly doped substrate is discussed. The concept of threshold surface potential is adopted so as to take the freeze out eect into consideration and to calculate the threshold voltage as a function of temperature. A new method of extracting the threshold voltage from experimental data, based on the de®nition of threshold surface potential, is also proposed. The extracted values ®t well with the calculated threshold voltages in the temperature range of 80 to 300 K. # 1998 Elsevier Science Ltd. All rights reserved
1. NOMENCLATURE Cox Dit E(x) EA EC EF Eg Ei EV k L NA(x) NB NC Ng Ng0 ni NV p(x) q Qdep Qf Qi Qi,drain Qi,source Qit Qm T VFB Vni VT xdm DVFB Es m m0 fms
The gate oxide capacitance per unit area. The oxide interface state density. The substrate build-in ®eld at a distance x from gate oxide interface. The substrate acceptor-level. The energy at the bottom of the conduction band. The substrate Fermi-level. The bandgap of substrate. The intrinsic Fermi-level. The energy at the top of the valence band. The Boltzmann constant. The substrate thickness. The substrate doping concentration at a distance x from gate oxide interface. The substrate doping concentration at substrate contact. The eective density of states in the conduction band. The polysilicon gate doping concentration. The polysilicon gate ionized doping concentration. The intrinsic carrier concentration. The eective density of states in the valence band. The ionized substrate doping concentration at a distance of x. The elementary charge. The charge per unit area in substrate depletion region. The oxide ®xed charge per unit area. The charge per unit area in substrate inversion layer. The charge per unit area in substrate inversion layer at drain side. The charge per unit area in substrate inversion layer at source side. The oxide interface trapped charge per unit area. The oxide mobile charge per unit area. The absolute temperature. The ¯at-band voltage. The voltage drop in polysilicon gate at the onset of strong inversion. The threshold voltage of MOSFET. The substrate depletion edge. The ¯at-band voltage shift due to Qf, Qit and Qm. The silicon dielectric constant. The electron mobility. The low ®eld electron mobility. The gate material and substrate work function dierence.
fp fs fs0 fs,drain fs,source ft
The potential dierence between the substrate Fermi level EF and the intrinsic Fermi level Ei. The substrate surface potential. The substrate surface potential at the onset of strong inversion include freeze out eect. The substrate surface potential at the drain side. The substrate surface potential at the source side. The thermal voltage.
2. INTRODUCTION
The threshold voltage VT is one of the important parameters of MOSFET's. There is much research carried out on this topic, most of which discusses the short channel eects of the device[1±5] and nonuniform substrate eects[5±9]. The temperature dependent device physics and characteristics have been discussed in the literature[10±16]. There are many bene®ts for MOSFET operating in low temperatures, such as the improvement of subthreshold swing, increase of carrier mobility, higher saturation velocity and operation speed, decreased leakage current, improved latch-up immunity, reduction of short channel eects and improved electro-migration and heat dissipation. Usually, at room temperature the onset of strong inversion is de®ned as when the surface potential equals 2fp. However at low temperatures, the value of surface potential at the onset of strong inversion must be modi®ed because of the freeze out eect in the substrate and the still fully ionized depletion region right beneath the SiO2 interface. The temperature dependence of threshold voltage on nonuniformly doped substrate is analyzed in this work and the theoretic results are compared with experimental data. 1799
1800
J. Gong et al. 3. THEORY
3.1. Non-uniform doping substrate eect of VT In modern MOS process, the technology of ion implantation is used to obtain a desired threshold voltage and to improve device performance. A nonuniformly doped substrate is then obtained. The threshold voltage of such a device is[8], assuming complete impurity ionization, VT fms DVFB 2fp
Qdep Qi Cox
kT NA L Es ln E x dm Vni q NA x dm Cox
1
where for an N+ polysilicon gate, fms=(EFÿEC)/q is the potential dierence between the substrate Fermi level and the N+ polysilicon Fermi level, DVFB fp
Qf Qm Qit , Cox Cox Cox
kT NA x dm ln , q ni
Qdep
x dm 0
qNA x dx,
kT d E x dm , ln NA x q dx xx dm
2 3
4
5
and Vni
Qdep Qit Qf Qm qNd Qdep Qit Qf Qm ÿ E x dm 2Es
6
is the polygate voltage drop at the onset of strong inversion. 3.2. Temperature dependence of VT When temperature eect is taken into consideration, then Equation (1) is modi®ed to VT fms DVFB fs0
Fig. 1. Band diagram of MOSFET at VT bias considering temperature eect.
Qdep Qi fs0 Cox
kT p L Es E x dm Vni 7 ln Cox q p x dm
Where p(x) is substrate hole density with freeze out eect being considered. The band diagram of a MOSFET considering temperature eect is shown in Fig. 1. Here the temperature dependence of VT can be divided into ®ve parts as discussed in Sections 3.2.1, 3.2.2, 3.2.3, 3.2.4 and 3.2.5. 3.2.1. Temperature dependence of fs0. The threshold surface potential de®ned in Ref.[6] is when
dQi dQdep : dfs fsTH dfs fsTH
8
For uniform doping and a completely ionized substrate case fsTH=2fp, as usually considered in papers. At low temperatures the impurities right beneath the SiO2 interface are still completely ionized due to the existed electric ®eld, however, the substrate carrier concentration is decreased due to the freeze-out eect. Therefore, the threshold surface potential becomes kT NA kT p0 x dm fs0 fp0c fp0 ln ln q q ni ni 9 where fp0c is the voltage dierence between Fermi level and intrinsic Fermi level for complete ionization condition and fp0 is the potential dierence with the freeze out eect. Here the p0(xdm) is the majority carrier concentration at x = xdm and it varies with temperature. For the nonuniform doping case NA in Equation (9) should be substituted with x NAe(xdm) = ( 0 dm NA(x) dx)/xdm. In order to calculate the temperature dependence of fs0, the temperature dependence of p0(xdm) and ni must be known. From Ref.[13] p0 x dm
NA x dm , 1 4 exp EA ÿ EF =kT
10
let Ei=0 as reference point, EF ÿkT ln p0 =ni : From Equations (10) and (11) we have
11
Temperature dependence of threshold voltage of N-MOSFETs
p0 x dm
ÿ1
p 1 4NA x dm 4 exp EA =kT =ni 2 4 exp EA =kT =ni 12
Here the acceptor energy level EA EV 0:045 eV,
13
where 0.045 eV is the ionization energy for boron and EV ÿ kT ln NV =ni ÿ ÿ
Eg kT NV ln ÿ 2 2 NC
Eg 0:4952kT, 2
p ni NC NV eÿEg =kT 1:7065 1019
T 300
3=2
Figure 2 shows the variation of fp0 as a function of temperature with dierent values of NA(xdm). It is clear that fp0 is increased as temperature decreases. The upper line with circle points is the valence band edge with Ei=0 as the reference. For dierent NA(xdm), the value of fp0ÿEV is decreased with temperature. 3.2.2. Temperature dependence of fms. When considering the freeze-out eect, the gate-substrate work-function dierence is fms
14
eÿEg =2kT :
15
Eg T EC ÿ EV Eg 0 ÿ aT 2 = T b,
16
From Ref.[13],
ÿ4
Eg(0) = 1.17, a = 4.73 10 , b = 636, from Equations (12)±(14) and (16) we can solve for p0(xdm) for a certain NA(xdm) at dierent temperatures. From q x dm fs xNA x dx 17 Es 0 and Equation (12), we can use the iteration method to obtain fs, p0 and xdm for a certain known doping pro®le.
1801
EF NB ÿ EF poly kT ÿ ln Ng0 p0 L=n2i q q 18
It is clear that fms will decrease with temperature. 3.2.3. Temperature dependence of DVFB. From Equation (2), DVFB varies with Qf, Qm and Qit. Qm and Qf do not vary with temperature, only Qit increases as temperature decreases which is due to the increased fp. The quantity of Qit also depends on Dit(E). 3.2.4. Temperature dependence of Qdep and Qi. As the temperature decreases both fs and xdm increase which also cause Qdep to increase. To improve the precision of the formula, we add the term of minority carrier charges Qi into VT, q Qi fs Q2dep 2Es kTNA x dm e bfs ÿbfs0 ÿ Qdep : 19 Usually Qdep>>Qi, then Qi can be approximated as Qi fs
Es kTNA x dm bfs ÿbfs0 e Qdep
Fig. 2. fp0 vs temperature for dierent values of NA(xdm).
20
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J. Gong et al.
Fig. 3. The doping pro®le and depletion edge at various temperatures (circle points) of the testing device.
When fs=fs0, Qi is proportional to T for a ®xed NA(xdm). 3.2.5. Temperature dependence of Vni and E(xdm). The electric ®eld at the depletion region edge is E x dm
kT d ln p0 x dm q dx
21
From Equation (6), because Qdep and Qit increase as the temperature decreases, so Vni increases with lowering temperature. For our samples Vni is about 0.0005 and 0.0007 V at the temperatures of 300 and 80 K, respectively. It is clear from the above equation that E(xdm) decreases with temperature, the ®rst term kT/q is proportional to T and the second term d[ln p(xdm)]/dx also decreases with temperature because of the freeze out eect. 4. EXPERIMENTAL RESULTS AND DISCUSSION
The substrate impurity doping pro®le of the testing n-channel MOSFETs is obtained from a TMA SUPREM IV process simulator, shown in Fig. 3. The impurity concentration close to the SiO2 interface is much lower than the peak concentration, this is due to the segregation eect. The circle points are the depletion region edge xdm obtained from Equations (12) and (17), for dierent temperatures from 300 to 80 K. Since the threshold voltage as de®ned in Equation (8) cannot be obtained directly from an experimental reading, therefore, a systematic method is derived in the following to obtain a threshold voltage which corresponds to the de®-
nition of Equation (8). To avoid the lateral electric ®eld eect on mobility, the linear Id±Vg curve were measured at a drain voltage of VD=0.05 V and at temperatures from 80 to 300 K. The threshold voltage was determined by the following method: calculate the low ®eld mobility of the testing device from the following equation: gmmax m0 , 22 Cox WVD =L where gmmax is obtained from the measured Id±Vg curves at dierent temperatures. Under the circumstance of gmRgmmax the gate voltage is small enough such that the eect of vertical electric ®eld on m0 is negligible. Using this mobility and the Qi calculated from Equation (20), we obtain a corresponding Id from the following equation[17]: ( ) W fs,drain Id m ÿQi dfs ft m Qi,drain ÿ Qi,source , L fs,source 23 Read the Vg corresponding to this Id from measured Id±Vg curves, and this Vg is de®ned as the value of VT. Table 1 gives the calculated m0, Qi and Id at dierent temperatures. The measured Id±Vg curves and VT for dierent temperatures are indicated in Fig. 4. Figure 5 shows the temperature dependence of VT. The experimental results are extracted with the procedures described above. The theoretical results are calculated from Equation (7). For comparison,
Temperature dependence of threshold voltage of N-MOSFETs
1803
Table 1. Calculated m0, Qi and Id T (K) 80 2
m0 (cm /V s) Qi (10ÿ9 C) Id (mA)
2252 0.558 0.1608
120 1692 0.848 0.2724
160 1232 1.149 0.3488
200 919 1.464 0.3972
240 716 1.796 0.4329
Fig. 4. Id vs Vg for dierent temperatures. VT is indicated in each curve.
Fig. 5. Threshold voltage as a function of temperature obtained from dierent methods.
300 517 2.332 0.4644
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J. Gong et al.
Fig. 6. Comparison of dierent approaches for DVT.
the VT extracted with the method proposed in Ref.[14], with the conventional maximum gm method (VT=Vgjgmmax ÿ1/gmmaxIdjgmmax ) and the VT calculated for uniform doping of NA=6 1016 and 7 1016 cmÿ3 are also plotted. The experimental results of VT and the calculated VT ®t very well in the temperature range 80 to 300 K. Among the terms discussed in Section 3, the voltage drop in the poly-silicon gate (the Vni term) is the least signi®cant one which can always be neglected. The eect of electric ®eld on the depletion edge [E(xdm)] is more pronounced at room temperature than at low temperatures, because at low temperatures the carrier concentration is reduced due to the freeze out eect, therefore, the electric ®eld is also reduced. The in¯uence of inversion layer charge Qi on the threshold voltage is larger than that of the electric ®eld's but it is often neglected in the literatures. Here the contribution of DQi to DVT (compared to 300 K) is about 5%. A constant interface state density of Dit=1 1010 cmÿ2 is used in this work, however, a larger interface state density will shift the threshold voltage to larger value. The most important three terms that aect the temperature dependence of VT are fms, fs and Qdep. The term fms decreases as the temperature decreases, fs and Qdep increase as the temperature decreases. The total eect of all the above terms causes the threshold voltage to increase as the temperature decreases. For a quick reference, Dfs alone can be used to approximate DVT (about 95% of its value) for poly-gate transistors. Dierent simpli®ed
approaches for the threshold voltage dierence, as compared to that of 300 K are plotted in Fig. 6. 5. CONCLUSION
In this work, we discussed the temperature eect on threshold voltage of a MOSFET with nonuniform substrate. The surface potential at the onset of strong inversion at room temperature is 2fp and at low temperature when considering the freeze out eect it must be modi®ed as fp0c+fp0. The value of the threshold voltage obtained from this de®nition is not the same as normally obtained from the gmmax point extrapolated from the linear Id vs Vg curve. The eect of the inversion layers charge, Qi, in the threshold voltage is more pronounced than that of the electric ®elds and the voltage drop in polysilicon gate's, but it is less discussed in the literature. A method of extracting the threshold voltage from experimental data, based on the de®nition of threshold surface potential, is proposed. These extracted values agree well with theoretical values. REFERENCES
1. Lee, H. S., Solid-State Electron., 1973, 25, 1407±1417. 2. Toyabe, T. and Asia, S., IEEE J. Solid-State Circuit, 1979, 14, 375±383. 3. Liu, Z. H., Hu, C., Huang, J. H., Chan, T. Y., Jeng, M. C., Ko, P. K. and Cheng, Y. C., IEEE Trans. Electron Devices, 1993, 40, 86±93. 4. Fjeldly, T. A. and Shur, M., IEEE Trans. Electron Devices, 1993, 40, 1±137.145. 5. Maa, J. J. and Wu, C. Y., IEEE Trans. Electron Devices, 1995, 42, 1487±1494.
Temperature dependence of threshold voltage of N-MOSFETs 6. Booth, R. V., White, M. H., Wong, H. S. and Krutsick, T. J., IEEE Trans. Electron Devices, 1987, 34, 2501±2508. 7. Kendall, J. D. and Boothroyd, A. R., IEEE Electron Device Lett., 1986, 7, 401±403. 8. Marshak, A. H., Solid-State Electron., 1983, 26, 361± 364. 9. Brews, J. R., IEEE Trans. Electron Devices, 1979, 26, 1696±1710. 10. Kuzmicz, W., Solid-State Electron., 1986, 29, 1223± 1227. 11. Hafez, I. M., Ghibaudo, G., Balestra, F. and Haond, M., Solid-State Electron., 1995, 38, 419±424.
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12. Min, K. S. and Lee, K., IEEE Trans. Electron Devices, 1995, 42, 1956±1961. 13. Sze, S. M., Physics of Semiconductor Devices. John Wiley and Sons, 1981. 14. Emrani, A., Balestra, F. and Ghibaudo, G., IEEE Trans. Electron Devices, 1993, 40, 564±569. 15. Dorkel, J. M. and Leturcq, P. H., Solid-State Electron., 1981, 24, 821±825. 16. Klaassen, D. B. M., Solid-State Electron., 1992, 35, 961±967. 17. Tsividis, Y. P., Operation and Modeling of the MOS Transitor. McGraw-Hill, 1987.
Solid-State Electronics Vol. 42, No. 10, pp. 1799±1805, 1998 # 1998 Elsevier Science Ltd. All rights reserved Printed in Great Britain 0038-1101/98/$ - see front matter S0038-1101(98)00155-5
THE TEMPERATURE-DEPENDENCE OF THRESHOLD VOLTAGE OF N-MOSFETs WITH NONUNIFORM SUBSTRATE DOPING H. H. CHEN, S. H. TSENG and J. GONG Department of Electrical Engineering, National Tsing Hua University, Kuang-Fu Road, Hsinchu, Taiwan 300, R.O.C (Received 19 August 1997; in revised form 12 December 1997) AbstractÐIn this work, the temperature eect on threshold voltage of a MOSFET with nonuniformly doped substrate is discussed. The concept of threshold surface potential is adopted so as to take the freeze out eect into consideration and to calculate the threshold voltage as a function of temperature. A new method of extracting the threshold voltage from experimental data, based on the de®nition of threshold surface potential, is also proposed. The extracted values ®t well with the calculated threshold voltages in the temperature range of 80 to 300 K. # 1998 Elsevier Science Ltd. All rights reserved
1. NOMENCLATURE Cox Dit E(x) EA EC EF Eg Ei EV k L NA(x) NB NC Ng Ng0 ni NV p(x) q Qdep Qf Qi Qi,drain Qi,source Qit Qm T VFB Vni VT xdm DVFB Es m m0 fms
The gate oxide capacitance per unit area. The oxide interface state density. The substrate build-in ®eld at a distance x from gate oxide interface. The substrate acceptor-level. The energy at the bottom of the conduction band. The substrate Fermi-level. The bandgap of substrate. The intrinsic Fermi-level. The energy at the top of the valence band. The Boltzmann constant. The substrate thickness. The substrate doping concentration at a distance x from gate oxide interface. The substrate doping concentration at substrate contact. The eective density of states in the conduction band. The polysilicon gate doping concentration. The polysilicon gate ionized doping concentration. The intrinsic carrier concentration. The eective density of states in the valence band. The ionized substrate doping concentration at a distance of x. The elementary charge. The charge per unit area in substrate depletion region. The oxide ®xed charge per unit area. The charge per unit area in substrate inversion layer. The charge per unit area in substrate inversion layer at drain side. The charge per unit area in substrate inversion layer at source side. The oxide interface trapped charge per unit area. The oxide mobile charge per unit area. The absolute temperature. The ¯at-band voltage. The voltage drop in polysilicon gate at the onset of strong inversion. The threshold voltage of MOSFET. The substrate depletion edge. The ¯at-band voltage shift due to Qf, Qit and Qm. The silicon dielectric constant. The electron mobility. The low ®eld electron mobility. The gate material and substrate work function dierence.
fp fs fs0 fs,drain fs,source ft
The potential dierence between the substrate Fermi level EF and the intrinsic Fermi level Ei. The substrate surface potential. The substrate surface potential at the onset of strong inversion include freeze out eect. The substrate surface potential at the drain side. The substrate surface potential at the source side. The thermal voltage.
2. INTRODUCTION
The threshold voltage VT is one of the important parameters of MOSFET's. There is much research carried out on this topic, most of which discusses the short channel eects of the device[1±5] and nonuniform substrate eects[5±9]. The temperature dependent device physics and characteristics have been discussed in the literature[10±16]. There are many bene®ts for MOSFET operating in low temperatures, such as the improvement of subthreshold swing, increase of carrier mobility, higher saturation velocity and operation speed, decreased leakage current, improved latch-up immunity, reduction of short channel eects and improved electro-migration and heat dissipation. Usually, at room temperature the onset of strong inversion is de®ned as when the surface potential equals 2fp. However at low temperatures, the value of surface potential at the onset of strong inversion must be modi®ed because of the freeze out eect in the substrate and the still fully ionized depletion region right beneath the SiO2 interface. The temperature dependence of threshold voltage on nonuniformly doped substrate is analyzed in this work and the theoretic results are compared with experimental data. 1799
1800
J. Gong et al. 3. THEORY
3.1. Non-uniform doping substrate eect of VT In modern MOS process, the technology of ion implantation is used to obtain a desired threshold voltage and to improve device performance. A nonuniformly doped substrate is then obtained. The threshold voltage of such a device is[8], assuming complete impurity ionization, VT fms DVFB 2fp
Qdep Qi Cox
kT NA L Es ln E x dm Vni q NA x dm Cox
1
where for an N+ polysilicon gate, fms=(EFÿEC)/q is the potential dierence between the substrate Fermi level and the N+ polysilicon Fermi level, DVFB fp
Qf Qm Qit , Cox Cox Cox
kT NA x dm ln , q ni
Qdep
x dm 0
qNA x dx,
kT d E x dm , ln NA x q dx xx dm
2 3
4
5
and Vni
Qdep Qit Qf Qm qNd Qdep Qit Qf Qm ÿ E x dm 2Es
6
is the polygate voltage drop at the onset of strong inversion. 3.2. Temperature dependence of VT When temperature eect is taken into consideration, then Equation (1) is modi®ed to VT fms DVFB fs0
Fig. 1. Band diagram of MOSFET at VT bias considering temperature eect.
Qdep Qi fs0 Cox
kT p L Es E x dm Vni 7 ln Cox q p x dm
Where p(x) is substrate hole density with freeze out eect being considered. The band diagram of a MOSFET considering temperature eect is shown in Fig. 1. Here the temperature dependence of VT can be divided into ®ve parts as discussed in Sections 3.2.1, 3.2.2, 3.2.3, 3.2.4 and 3.2.5. 3.2.1. Temperature dependence of fs0. The threshold surface potential de®ned in Ref.[6] is when
dQi dQdep : dfs fsTH dfs fsTH
8
For uniform doping and a completely ionized substrate case fsTH=2fp, as usually considered in papers. At low temperatures the impurities right beneath the SiO2 interface are still completely ionized due to the existed electric ®eld, however, the substrate carrier concentration is decreased due to the freeze-out eect. Therefore, the threshold surface potential becomes kT NA kT p0 x dm fs0 fp0c fp0 ln ln q q ni ni 9 where fp0c is the voltage dierence between Fermi level and intrinsic Fermi level for complete ionization condition and fp0 is the potential dierence with the freeze out eect. Here the p0(xdm) is the majority carrier concentration at x = xdm and it varies with temperature. For the nonuniform doping case NA in Equation (9) should be substituted with x NAe(xdm) = ( 0 dm NA(x) dx)/xdm. In order to calculate the temperature dependence of fs0, the temperature dependence of p0(xdm) and ni must be known. From Ref.[13] p0 x dm
NA x dm , 1 4 exp EA ÿ EF =kT
10
let Ei=0 as reference point, EF ÿkT ln p0 =ni : From Equations (10) and (11) we have
11
Temperature dependence of threshold voltage of N-MOSFETs
p0 x dm
ÿ1
p 1 4NA x dm 4 exp EA =kT =ni 2 4 exp EA =kT =ni 12
Here the acceptor energy level EA EV 0:045 eV,
13
where 0.045 eV is the ionization energy for boron and EV ÿ kT ln NV =ni ÿ ÿ
Eg kT NV ln ÿ 2 2 NC
Eg 0:4952kT, 2
p ni NC NV eÿEg =kT 1:7065 1019
T 300
3=2
Figure 2 shows the variation of fp0 as a function of temperature with dierent values of NA(xdm). It is clear that fp0 is increased as temperature decreases. The upper line with circle points is the valence band edge with Ei=0 as the reference. For dierent NA(xdm), the value of fp0ÿEV is decreased with temperature. 3.2.2. Temperature dependence of fms. When considering the freeze-out eect, the gate-substrate work-function dierence is fms
14
eÿEg =2kT :
15
Eg T EC ÿ EV Eg 0 ÿ aT 2 = T b,
16
From Ref.[13],
ÿ4
Eg(0) = 1.17, a = 4.73 10 , b = 636, from Equations (12)±(14) and (16) we can solve for p0(xdm) for a certain NA(xdm) at dierent temperatures. From q x dm fs xNA x dx 17 Es 0 and Equation (12), we can use the iteration method to obtain fs, p0 and xdm for a certain known doping pro®le.
1801
EF NB ÿ EF poly kT ÿ ln Ng0 p0 L=n2i q q 18
It is clear that fms will decrease with temperature. 3.2.3. Temperature dependence of DVFB. From Equation (2), DVFB varies with Qf, Qm and Qit. Qm and Qf do not vary with temperature, only Qit increases as temperature decreases which is due to the increased fp. The quantity of Qit also depends on Dit(E). 3.2.4. Temperature dependence of Qdep and Qi. As the temperature decreases both fs and xdm increase which also cause Qdep to increase. To improve the precision of the formula, we add the term of minority carrier charges Qi into VT, q Qi fs Q2dep 2Es kTNA x dm e bfs ÿbfs0 ÿ Qdep : 19 Usually Qdep>>Qi, then Qi can be approximated as Qi fs
Es kTNA x dm bfs ÿbfs0 e Qdep
Fig. 2. fp0 vs temperature for dierent values of NA(xdm).
20
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J. Gong et al.
Fig. 3. The doping pro®le and depletion edge at various temperatures (circle points) of the testing device.
When fs=fs0, Qi is proportional to T for a ®xed NA(xdm). 3.2.5. Temperature dependence of Vni and E(xdm). The electric ®eld at the depletion region edge is E x dm
kT d ln p0 x dm q dx
21
From Equation (6), because Qdep and Qit increase as the temperature decreases, so Vni increases with lowering temperature. For our samples Vni is about 0.0005 and 0.0007 V at the temperatures of 300 and 80 K, respectively. It is clear from the above equation that E(xdm) decreases with temperature, the ®rst term kT/q is proportional to T and the second term d[ln p(xdm)]/dx also decreases with temperature because of the freeze out eect. 4. EXPERIMENTAL RESULTS AND DISCUSSION
The substrate impurity doping pro®le of the testing n-channel MOSFETs is obtained from a TMA SUPREM IV process simulator, shown in Fig. 3. The impurity concentration close to the SiO2 interface is much lower than the peak concentration, this is due to the segregation eect. The circle points are the depletion region edge xdm obtained from Equations (12) and (17), for dierent temperatures from 300 to 80 K. Since the threshold voltage as de®ned in Equation (8) cannot be obtained directly from an experimental reading, therefore, a systematic method is derived in the following to obtain a threshold voltage which corresponds to the de®-
nition of Equation (8). To avoid the lateral electric ®eld eect on mobility, the linear Id±Vg curve were measured at a drain voltage of VD=0.05 V and at temperatures from 80 to 300 K. The threshold voltage was determined by the following method: calculate the low ®eld mobility of the testing device from the following equation: gmmax m0 , 22 Cox WVD =L where gmmax is obtained from the measured Id±Vg curves at dierent temperatures. Under the circumstance of gmRgmmax the gate voltage is small enough such that the eect of vertical electric ®eld on m0 is negligible. Using this mobility and the Qi calculated from Equation (20), we obtain a corresponding Id from the following equation[17]: ( ) W fs,drain Id m ÿQi dfs ft m Qi,drain ÿ Qi,source , L fs,source 23 Read the Vg corresponding to this Id from measured Id±Vg curves, and this Vg is de®ned as the value of VT. Table 1 gives the calculated m0, Qi and Id at dierent temperatures. The measured Id±Vg curves and VT for dierent temperatures are indicated in Fig. 4. Figure 5 shows the temperature dependence of VT. The experimental results are extracted with the procedures described above. The theoretical results are calculated from Equation (7). For comparison,
Temperature dependence of threshold voltage of N-MOSFETs
1803
Table 1. Calculated m0, Qi and Id T (K) 80 2
m0 (cm /V s) Qi (10ÿ9 C) Id (mA)
2252 0.558 0.1608
120 1692 0.848 0.2724
160 1232 1.149 0.3488
200 919 1.464 0.3972
240 716 1.796 0.4329
Fig. 4. Id vs Vg for dierent temperatures. VT is indicated in each curve.
Fig. 5. Threshold voltage as a function of temperature obtained from dierent methods.
300 517 2.332 0.4644
1804
J. Gong et al.
Fig. 6. Comparison of dierent approaches for DVT.
the VT extracted with the method proposed in Ref.[14], with the conventional maximum gm method (VT=Vgjgmmax ÿ1/gmmaxIdjgmmax ) and the VT calculated for uniform doping of NA=6 1016 and 7 1016 cmÿ3 are also plotted. The experimental results of VT and the calculated VT ®t very well in the temperature range 80 to 300 K. Among the terms discussed in Section 3, the voltage drop in the poly-silicon gate (the Vni term) is the least signi®cant one which can always be neglected. The eect of electric ®eld on the depletion edge [E(xdm)] is more pronounced at room temperature than at low temperatures, because at low temperatures the carrier concentration is reduced due to the freeze out eect, therefore, the electric ®eld is also reduced. The in¯uence of inversion layer charge Qi on the threshold voltage is larger than that of the electric ®eld's but it is often neglected in the literatures. Here the contribution of DQi to DVT (compared to 300 K) is about 5%. A constant interface state density of Dit=1 1010 cmÿ2 is used in this work, however, a larger interface state density will shift the threshold voltage to larger value. The most important three terms that aect the temperature dependence of VT are fms, fs and Qdep. The term fms decreases as the temperature decreases, fs and Qdep increase as the temperature decreases. The total eect of all the above terms causes the threshold voltage to increase as the temperature decreases. For a quick reference, Dfs alone can be used to approximate DVT (about 95% of its value) for poly-gate transistors. Dierent simpli®ed
approaches for the threshold voltage dierence, as compared to that of 300 K are plotted in Fig. 6. 5. CONCLUSION
In this work, we discussed the temperature eect on threshold voltage of a MOSFET with nonuniform substrate. The surface potential at the onset of strong inversion at room temperature is 2fp and at low temperature when considering the freeze out eect it must be modi®ed as fp0c+fp0. The value of the threshold voltage obtained from this de®nition is not the same as normally obtained from the gmmax point extrapolated from the linear Id vs Vg curve. The eect of the inversion layers charge, Qi, in the threshold voltage is more pronounced than that of the electric ®elds and the voltage drop in polysilicon gate's, but it is less discussed in the literature. A method of extracting the threshold voltage from experimental data, based on the de®nition of threshold surface potential, is proposed. These extracted values agree well with theoretical values. REFERENCES
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