The use of charge pumping currents to measure surface state densities in MOS transistors

Solid-Skate Ekctmnes.

1976. Vol

19. pp. 241-247.

Pergamon Press.

Pnnted in Great Britam

THE USE OF CHARGE PUMPING CURRENTS TO MEASURE SURFACE STATE DENSITIES IN MOS TRANSISTORS ALEXANDERB. M. ELLIOT Post OfficeResearch Department, Martlesham Heath, Ipswich, England (Received 30 April 1975; in revised form 12August 1975) Absbati-A method is described for determining the surface-state density at the oxide interface in the channel of an MOS transistor from the charge pumping current flowing to the substrate when gate pulses are applied. From this . simple measurement the surface state density can be determined as a function of gate voltage and if a quasi-static C-V characteristic is also measured for the gate of the transistor then the voltage distribution can be converted into an energy distribution. Representative results obtained on a set of commercial transistors show a large increase in the surface-state density near the middle of the band-gap after negative-bias thermal-stressing. 1.

INTltODUCTiON

Shifts in transistor threshold voltage are a significant cause of failure in MOS integrated circuits[ 1.23 and measurements of these shifts, which can be conveniently accelerated by elevated ambient temperatures[3] are an essential part of the procedure for establishing the reliability of an MOS process. The threshold voltage measurements are normally made using what are effectively steady-state conditions and the shifts in the threshold voltage include contributions caused by both the fixed charge in the oxide and also the surface-states at the silicon-silicon dioxide interface. However the transistor in an operational circuit may be operating at speeds faster than the response time of some of the surface states and therefore have an effective high frequency threshold voltage which is significantly different from the steady state value. Hence there is a requirement for a surface state measurement which is sufficiently simple to be included as a routine measurement during thermally accelerated ageing. Because the method must be applicable to commercially available components it must be capable of using a transistor with a small gate area as a test vehicle and the existing techniques which use capacitor structures[4-6] are not suitable. A method based on the charge pumping phenomena in transistors reported by Brugler and Jespers[7] has been developed which in its simplest form determines an overall figure for the surface state density and in a more complex form determines the energy distribution. The usefulness of the technique is illustrated by measuring the change in surface-state distribution which occurs after negative-bias temperature ageing of some test transistors and these particular test transistors have a sufficiently large gate area for the results to be confirmed by comparing them with an independent determination of the surface-state distribution obtained from a comparison of “quasistatic”[4] and high frequency C-V plots. 2. THE CHARGE

PUMPING PHENOMENON

conductivity type in the channel of an MOS transistor can stimulate a net flow of majority carriers from the source and drain to the substrate. In the following description of the charge pumping phenomenon in a p-channel transistor the pulse is referred to as being “on” when it is at its more negative level and as being “off” when it is at its more positive level. Also the terms “above” and “below” a given level are taken to mean “more negative than ” and “less negative than” respectively. When the p-channel transistor in Fig. 1 is switched on by the application of a sufficiently large negative pulse to the gate of the device, the surface is inverted and holes flow into the channel region from the source and drain. Some of the holes are captured by surface states and the rest are present as mobile carriers in the channel. If, when the pulse is turned off, the gate returns to ground potential (i.e. the same potential as the substrate) then the mobile charge drifts back to the source and drain regions under the influence of the reverse bias voltage, V,, but some charge remains in the surface states. During the period when the pulse is off the positively charged surface states are neutralised by recombination with electrons from the n-type substrate thereby giving rise to a net flow of positive charge to the substrate. A repetitive application of the negative gate pulse thus results in a unidirectional “pumped” current of majority carriers from the source and drain to the substrate which is in the opposite direction to the minority carrier leakage current. The magnitude of this “pumped” current due to surface states is given by the equation ICP

=

ffbq~ss

where f = frequency of the gate pulse (Hz) AG = area of the transistor channel (cm*) q = electronic charge (C) Nss = density of surface states with energy levels which sweep through the Fermi level when the pulse is applied (cm-‘).

It has been shown by Brugler and Jespers[‘ll that repetitive gate pulses of magnitude sufficient to invert the

The above equation assumes that all the mobile charge 241

A. B.

242

M.

ELLIOT

L

“R

Fig. I. Basic charge pumping circuit.

drifts back to the source and drain when the pulse is turned off, which is generally a good approximation for the conventional MOS transistor with its channel length of the order of 10/1m provided also that the gate pulse fall-time is greater than 10 ns. However, if some fraction, a, of the mobile charge does not drift back to the source and drain then a “geometric component’* [A must be added to the charge pumping equation to give (2) where Co = oxide capacitance per unit area (F cm-‘), V, = gate voltage (V) V, = threshold voltage (V). The variation of charge pumping current with pulse amplitude and reverse bias voltage V, (applied between the source and drain and the substrate) observed on a typical commercial transistor is shown in Fig. 2. These characteristics can be explained by reference to eqn (2). When the pulse amplitude is much greater than the threshold voltage the surface potential is “pinned” at twice the Fermi potential[ll 2&, and hence the charge pumping current due to surface states saturates in the pulse frufu.ncy

= ZOkHr

pulse

= 5ps

width

manner shown by the V, = -5 V and V, = -9 V plots. However the charge pumping current in the V, = 0 plot does continue to increase slowly with increasing pulse amplitude because the built-in potential across the source and drain junctions is not sufficient to entirely eliminate the “geometric component”. The reduction in the value of the saturated charge pumping current as the reverse-bias voltage increases is believed to be due to a channel shortening effect resulting from an expansion of the depletion regions surrounding the source and drain. Consequently the total density of surface states with energy levels which sweep through the Fermi level when a gate pulse is applied can be calculated from a single measurement of the charge pumping current made with a small reverse-bias voltage applied between the source and drain strapped and the substrate; (a value of - 1V is usually adequate to eliminate the “geometric component” without excessively increasing the channel shortening). Although the charge pumping current is a measure of the total density of surface states between the limits of excursion of the surface potential when the amplitude of the gate pulse is above the threshold voltage this is no longer the case when the pulse amplitude falls below the threshold voltage because the potential barriers between the source and drain and the substrate prevent the holes

I CP charge pumping current AWJS

pulse

amplitude

volts

Fig. 2. Charge pumping current as a function of the gate pulse amplitude with source and drain to substrate reverse-bias voltage as a parameter.

Charge pumping in MOS transistors

from flowing into the channel to fill the empty surface states. Therefore the variation in charge pumping current with gate pulse amplitude cannot be used to determine the energy distribution of the surface states as claimed by Brugler and Jespers[7]. An alternative approach which does enable the surface state distribution to be examined across most of the forbidden band-gap is to measure the charge pumping current as a function of the pulse base level, while keeping the pulse amplitude constant. Characteristics of this type are given for three values of substrate bias in Fig. 3. The V, = 0 characteristic, for which equilibrium theory[9] is valid, can be explained by reference to the energy band diagrams in Fig. 4, which are drawn for a direction normal to the n-type substrate. In these diagrams it is assumed that only donor states are present at the surface, but the situation is not significantly different if acceptor states also exist. The energy band diagrams are not intended to be accurate, they simply indicate the form of the band bending near the surface in order to facilitate the phenomenological description of the processes which give rise to the V, = 0 characteristic in Fig. 3. Consider first the position “A” in Fig. 3 and 4 where the gate pulse goes from -3 to -18 V. The surface potential is “pinned” close to the 2& level at both values of the gate voltage and therefore there is little change in the occupancy of the surface states. Consequently the surface state contribution to the charge pumping current is small but there may be a “geometric component” because the mobile charge density is varying by a large amount and a small contribution of this type does in fact appear to be present in the case of the V, = 0 characteristic in Fig. 3. At position “B”, where the pulse base level is -lV some of the surface donor states which have been filled with holes during the -16V pulse are below the Fermi level when the pulse is off and therefore the trapped holes wiU recombine with electrons from the n-type substrate giving rise to a significant charge pumping current. At position “C” the excursion of the surface potential is greater and therefore the charge pumping current is larger. As the base level goes positive the surface state contribution to the charge pumping pulse frequency pulse amplitude

243 positive donor states

/

,neutral

donor states, \

-18V

6

___---3 -1v

c

- 18V

Eu ---

__

OV

D

xl

L[

-----___

Eg -1 v

14V

Fig. 4. Energy band diagrams in the device channel normal to the surface.

current increases very slowly because ‘the surface potential changes slowly in the accumulation region. However when the pulse base level becomes more positive than 12V the gate voltage is below the threshold voltage even when the pulse is on and the surface states can no longer be filled by holes from the source and the drain. This leads to a rapid decrease in the charge pumping current to the level shown at position “II”; a decrease which mirrors the increase in the rising edge in Fig. 2 because it results from the same mechanism. The application of a reverse-bias voltage between the substrate and the source and drain does not significantly change the rising edge of the characteristic because the surface potential in the majority of the channel is not affected but, since the threshold voltage is measured with respect to the source, the falling edge is shifted by an amount equal to the sum of the voltage between the

s 20kHz 0 -15 V

pulse width

I

5ps

ICP cherQe

PumphI clment Amps

pulsa base level

volts

Fig. 3. Charge pumping current as a function of the gate pulse base level with source and drain reverse-bias voltage as a parameter.

to substrate

244

A. B. M. ELLIOT

source and the substrate and the increase in the threshold voltage. The rising edge clearly contains information on the energy distribution of surface states and the method used to determine this distribution is explained in the next section. The above method was experimentally convenient but other methods based on different gate waveforms are also possible. A fixed negative base level much greater than VT, say -lOV, together with a positive pulse of variable amplitude could be used. The important condition that must be satisfied is that at some point in the cycle the surface must be heavily inverted to allow the surface states to be filled. 3. ANALYSIS OF TEE ENERGY DISTRIBUTION OF

SURFACE STATES

If the rising edge of the charge pumping characteristic in Fig. 3 is to be analysed using eqn (2) then the effective area of the transistor channel, AG, must be determined. The width of the channel can be measured optically but the effective length of the channel is much more difhcult to measure and it can only be obtained indirectly by determining the reverse-bias voltage necessary to make a depletion region extend from the source to the drain and then substituting this voltage together with a value for the substrate doping density obtained from the dependence of threshold voltage on substrate bias[lO] into the depletion layer equation[ 111.

where & e, V, and &

= depletion length (cm) = dielectric constant for silicon (F cm-*) = substrate reverse-bias voltage (V) = junction built-in potential (eV).

This measurement can be made either by: (1) increasing the reverse bias voltage on both the source and the drain with respect to the substrate and using a gate capacitance measurement to determine when the two depletion regions meet or by

(2) applying an increasing negative voltage to the drain with respect to the source and using the drain current to indicate when the depletion region surrounding the drain “punches through” to the source. Since it is difficult to distinguish between “punch through” and avalanche breakdown of the drain junction the former technique was applied first and a typical result is shown in Fig. 5. The upper knee in each characteristic indicates the point at which the source and drain depletion regions meet thereby causing a rapid decrease in the gate capacitance. When the surface is accumulated the depletion regions meet in the bulk at a reverse-bias potential of about 12V and when this is substituted together with the measured substrate doping density of 5.5 x lOI cm-’ into the depietion layer eqn (3) a depletion length of 546 pm is obtained and hence a total channel length of 10.92km. The effective channel length may be less than this because of the channel shortening effect but the correction for this is readily obtained by substituting the appropriate values in eqn (3). Confirmation of the total channel length value was obtained from a breakdown voltage measurement which “walked-out”[lt] slowly until it saturated at a value of just under 5OV which is in good agreement with the “punch-through” voltage expected, (approximately four times the value required to make the two depletion regions meet). Having measured a value for the gate area, it is now possible to determine the surface state density as a function of gate voltage from the rising edge of the characteristics in Fig. 3 using eqn (2) and this provides a valuable basis for predicting the possible effects of surface states on the performance of integrated circuits fabricated using similar components. However if the energy distribution of surface states is required the gate voltage must be related to the surface potential and the normal method of determining this relationship is to measure the very low frequency or “quasi-static” C-V characteristic of the MOS structure[4]. Furthermore the “quasi-static” C-V measurement can be combined with a high frequency C-V measurement to provide an independent determination of the surface state energy distribution

CG-SUB gate-tosubstrate capacitance

PF 0.5-

substrate doping density I 54 x 1O”cm-3 I

10

O0-I “SUE-SO Fig. 5. High frequency

gate to substrate

substrate

I

15

to source and drain

20 voltage

capacitance as a function of the reverse-bias source and drain and the substrate.

voltage between a common

Charge pumping in MOS transistors

which can be compared with the distribution derived from the charge pumping characteristics. The use of a transistor in place of the more normal capacitor influences the measurement conditions and the analysis of the C-V characteristics. The source and drain of the transistor provide a sufficient supply of minority carriers to enable the inversion layer to follow the measurement signal and the equivalent circuit for the MOS structure [131reduces to the simple configuration in Fig. 6.(a) where CSc is the semiconductor space-charge capacitance, C,, is the surface state equivalent capacitance and R, and R, represent the charge transfer processes between the surface states and the conduction and valence band respectively. When making “quasistatic” measurements thermal equilibrium must be maintained and the rate at which this can be- achieved in a transistor structure is limited by the surface state time

trwmistor

(a) COX

quasi -

I

a

(b)

co,

4HV high

constants which have been shown by Nicollian and Goetzberger[5] to have an upper limit of 10m2 s (states due to traps in the oxide may be slower than this but they are ignored in the present analysis). The quasi-static measurements are all performed at a sweep-rate of lVs-’ which allows thermal equilibrium to be maintained and therefore short circuits R, and R,. to give the equivalent circuit in Fig. 6(b). Berglund[i4] has shown that the surface potential can be determined to within an additive constant from the “quasi-static” C-V characteristic by integrating the following expression

where Cox is the dielectric capacitance, A is an additive constant which must be obtained by comparison with ideal C-V characteristics and V. is any voltage in the strong accumulation region. Hence by using the relationship between surface potential and gate voltage determined from eqn (4), the energy distribution of surface states can be derived from the voltage distribution. However the measured quasi-static C-V plot for a typical commercial transistor contains parasitic capacitances due to the gate overlap of the source and drain diffusions, the gate bonding pad and the transistor package in parallel with the true gate to channel capacitance. But all of these additional capacitances are substantially independent of the gate voltage over the range of the quasi-static measurements and therefore the true C-V plot for the channel region can be obtained by setting the maximum capacitance equal to Cox. The value of Cox can be determined from a three terminal measurement of the gate to substrate capacitance as a function of gate bias [ IS]. At large positive gate bias, the surface is accumulated and the measured capacitance is equal to Cox plus the parasitic capacitances whereas at large negative gate bias the inverted surface shields the gate from the substrate and only the parasitic capacitances are measured. Hence Cox can be obtained from the difference in the measured capacitances and can be used together with a typical quasi-static C-V plot, such.as the one shown in Fig. 7, to

+qE!-iI

static

csc-cd~ci*c,

fnquency

(a Fig. 6. Equivalent circuits for an MOS transistor: (a) complete equivalent circuit for a transistor; (b) quasi-static equivalent circuit for a transistor; (c) hiih frequency equivalent circuit for a transistor.

gate

bias

or

245

pubc base level

Volts

Fig. 7. Quasi-static C-V, high frequency (I MHz) C-V and charge pumping current versus pulse base level plots for a typical commercial transistor.

246

A. B. M. ELLIOT

evaluate the surface potential as a function of the gate voltage. Because the determination of the surface potential from the quasi-static plot requires a numerical integration of eqn (4) the analogue results were converted into a digital form and stored on punched paper tape for subsequent processing. If the C-V plot is also measured at a frequency high enough to prevent any surface states responding to the test signal then R and R, are open circuited and hence the corresponding equivalent circuit is the one shown in Fig. 6(C). It follows from the equivalent circuits in Figs. 6(b) and 6(c) that

_-B___ c,, = cox Coxcm - Cqs Cox - Chf

(5)

>

where Cqs is the “quasi-static” capacitance and Chf is the high frequency capacitance. An independent measurement of the surface state energy distributions can then be obtained from the equation:

__GE_._ Chf CoX-cqs cox-Chf

>

(6)

where N,, is the density of surface states per eV. Because a transistor is used for these measurements the inversion layer can follow the high frequency test signal and therefore the equivalent circuit of Fig. 6(c) is valid into inversion. Consequently the surface state distribution can be obtained over most of the band gap whereas the analysis is limited to the onset of inversion when a capacitor is used[l6]. 4. ExpglllMBNTAL WrSJLTS Measurements were made on a set of six commerical p-channel metal gate transistors before and after a 24 hr period of temperature stress at 300°C during which a potential of -25V was applied to the gate of the transistors with respect to a common source, drain and substrate. The charge pumping measurements were made with a 20 kHz pulse of fixed amplitude (- 15V) and width (5~s) and a typical result obtained after stressing is shown in Fig. 7 together with the corresponding high-frequency and quasi-static C-V plots for the I

conddction band

quasi-static

*

results

after strwbs

bOlk Fermi lavel

transistor gate electrode. Charge pumping measurements were also made at 5 and 10kHz to ensure that the charge pumping current was proportional to frequency (this confirms that there are no significant leakage currents and that all the charged surface states are recombining during the “off” period). All the results were converted into digital form and stored on punched paper tape to facilitate the subsequent analysis of the surface state distributions. Figure 8 shows the distributions for a typical device before and after stressing as calculated from the charge-pumping measurements together with an independent assessment of the distribution after stressing, as obtained from a comparison of the quasi-static C-V plot and a high frequency C-V plot. This comparison technique does not have adequate resolution when applied to a transistor gate electrode to enable the distribution before stressing to be calculated. The characteristics obtained from the charge pumping analysis are likely to be fairly accurate near the middle of the band gap where the changes in the surface potential and the charge pumping current are quite substantial but towards the edges of the band-gap the surface state density is calculated from a ratio in which both the differential charge pumping current term in the numerator and the differential surface potential term in the denominator are small and therefore the larger scatter observed in the experimental results near the band edges is to be expected. This is a consequence of sampling at equal voltage increments instead of equal surface potential increments. The accuracy of the surface state results obtained from a comparison of the quasi-static and high frequency C-V plots is also very poor near the band edges because the surface state capacitance is in parallel with a very large semiconductor capacitance (see Fig. 6(b)). The gate capacitance of the transistors measured is only of the order of 1 pF. Hence the quasi-static measurement current at a ramp rate of IVs-’ is only lo-“A. Because it was not possible to reduce the current noise level below IO-“A the integrated error in the surface potential calculated from eqn (4) could be of the order of 2-3% of the integration range, i.e. up to O.lSV if the integration is over a range of 5V. The results in Fig. 8 clearly show the growth of charge .

pumping results before

stress

valence

band

Fig.8. Surface state energy distributions before and after negative bias-temperature stress.

Charge pumping in MOS transistors

interface states near the middle of the band-gap after a 24 hr negative-bias temperature stress at -25V and 300°C. Similar effects have been observed by Semushkina and Semushkin[l7] and by Geotzberger, Lopez and Strainfl81 but the former authors placed them 0.15 eV closer to the conduction band and the latter authors placed them 0.15 eV closer to the valence band.

CONCLUSIONS It has been demonstrated that charge-pumping current measurements can be combined with quasi-static C-V plots to determine the interface state energy distribution in an MOS transistor. The technique is only capable of providing energy distributions when the transistors have a gate capacitance of the order of 1 pF or larger because it is very difficult to obtain sufficiently accurate quasi-static C-V plots on gates with a lower capacitance. However even for devices with channel areas of only 10 x 10 pm and surface state densities as low as IO” cm-’ eV_’ the charge pumping measurements provide a useful and straightforward method of determining either the surface state density per unit energy as a function of gate voltage or an integrated value of the surface state density over the region of the band gap traversed by the surface potential in normal integrated circuit operation. Therefore the experimenter has available a method of separating the contributions made by the fast-states and fixed charges to shifts in threshold voltage during bias-temperature stress measurements. Metal-gate p-channel transistors investigated by the technique showed a large increase in the density per unit energy of interface states near the middle of the forbidden

241

energy band after a 24 hr stress at -25V (approximately 1.5 x IO6V cm-‘) and 300°C. Acknowledgemenr-Acknowledgement is made to the Director of Research, Post 05ce Telecommunications Headquarters for

permissionto publish*is paper.

1. S. R. Hofstein, Solid-St. Electron. lb, 657 (1967). 2. F. H. Reynolds, R. W. Parrott and D. Braithwaite, Pmt. Inst. Elect. Eng. 118,475(1971). 3. F. H. Reynolds, Pm. IEEE 62, 149 (1974). 4. M. Kuhn, Solid+ Elecrron. 13, 873 (1970). 5. E. H. Nicollian and A. Goetzberger, Bell Sysr. Tech. J. 46, 1055(1%7). 6. P. V. Gray and D. M. Brown, Appl. Phys. Lerrs 8,31(1%6). 7. J. S. Brugler and P. G. A. Jeapers, IEEE Trans. Electron Devices ED16, 297 (1%9). 8. S. M. Sze, Physics of Semiconductor Denices, p. 433. John Wiley New York (1%9). 9. A. S. Grove and D. J. Fitzgerald, Solid-St. Efecrron. 9, 783 (1%6). 10. J. A. van Nielen and 0. Memelink, Philips Res. Rpts. 22, 55 (1%7). 11. S. M. Sze, Physics of Semiconductor Dcuices, p. 90. John Wiley. New York (1%9). 12. J. W. Venvey, J. H. Aalberts and B. J. de Maagt, Microelectronics and Reliability 12, 51 (1973). _ 13. K. Lehovec and A. Slobodskv. Solid-St. Elecfmn. 1. 59

ww.

14. C. N. Berglund, IEEE Trans. EIecrron Devices BD-13, 701 (1966). IS. I. hf. Bateman and J. A. Magowan, Electronic Letts 6. 669 (1970). 16. R. Castagne, C.r. hebd. seanc. Acad. Sci. Paris 267,866(1%8). 17. N. A. Semushkina and G. B. Semushkin, Son Phys. Solid State 15, i (1973). 18. A. Goetzberger, A. D. Lopez and R. J. Strain, 1. Ekctmchem. Sot. 120, 90 (1973).