The use of state logic in biomedical instrumentation

COMPUTERS

The

AND

BIOMEDICAL

Use of State H.

THEODORE

7,294-303 (1974)

RESEARCH

Logic KEHL,

in Biomedical CHRISTINE

Moss,

Instrumentation AND

LAWRENCE

*

DUNKEL

Department of Physiology and Biophysics, University of Washington, Seattle, Washington 98195 Received

July 16,1973

In recent years biomedical research has seen the increasing use of digital logic not only in digital computer systems but in a variety of special purpose laboratory controllers. Integrated circuit technology has added impetus to the laboratory use of digital logic because of its low cost, high speed and the fact that complex functions may be purchased in single packages. However, all too often a designer of a digital logic device will insert gates and flip-flops wherever it occurs to him; that is, he will logically design from the inputs to the outputs placing logic components in an ad hoc design. Such a.design technique should be strongly discouraged because it requires maintenance personnel and/or other designers to reinvent the original design rationale. (Usually, after a few months, even the original designer cannot retrace his own design rationale.) To overcome this difficulty many designers use state logic. State logic represents a uniform, rigorous, and minimal solution to a design problem and has been used in the design of digital computers for several years. Its basic concept, the state diagram, derives from automata theory (a case-in-point illustrating the usefulness of basic research). It is possible to prove that the minimum state diagram for a process is the minimum logic required for that process (see Kohavi (1)). While this minimum logic is directly translated into a minimum of electronic components in the final device, it is not a minimum of components but a minimum in complexity which is sought. That is to say, given that the failure rate of TTL gates is .003 %/IO00 hours under severe test conditions (2) and the cost of a TTL gate is less than 10 cents, then most of the cost of a device is in its design and subsequent maintenance. Because state logic represents a rigorous, uniform (and simple) method of designing, both original design and maintenance costs are minimized. It makes little difference if gate count is minimized. However, state logic wilI result in both a minimum gate count and a simple, easy to understand design. State logic is not widely used in the design of devices for the biomedical research community. This paper will present, in tutorial fashion, an introduction to state logic. Additionally a new technique for implementing state logic will be given. *This research was supported by the National Institutes of Health, Division Resources, Biotechnology Research, RRO0374. 294 Copyright 0 1974 by Academic Press, Inc. All rights of reproduction Printed in Great Britain

in

my

form reserved.

of Research

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(Other, more theoretical techniques may be found in Ref. (3). In the two appendices an illustration of the use of state logic in a design of an A/D converter interface and a design for a behavioral experiment controller is presented. STATE LOGIC: THE STATE DIAGRAM A state diagram can be considered to be a flowchart of a sequence of actions to be performed by the desired device. In the state diagram each state evokes one or more special actions. State logic will only be in one state at any given time. Transition from state to state is conditioned on the presence of external or internal signals but will occur only when a clock pulse permits the transition. Thus state logic is completely synchronous. (It is possible to design asynchronous state logic and what is described in this paper is easily adapted to asynchronous devices.) Consider the state diagram in Fig. 1. Here state 0 (usually an idle state) is allowed to progress to state 1 when CMD comes true. We can describe the transition as: if

FIG.

state 0 and CMD

1. An example of a statediagram.

then go to state 1. Since a transition can only occur on clock pulses there is an implicit understanding that the transition will occur on the first clock pulse after the conditions are met. A transition from state 1 to state 2 or state 3 will occur conditioned on whether A or li is true. Since one or the other must be true, state 1 will last for exactly one clock time. Assume for the moment that A is true, which would cause a transition to state 3. State 3 is a gate term which triggers (starts) the execution of subprocess WRT. B is a term from subprocess WRT signaling that WRT has begun and the state logic can progress to state 4. Thus an interlock is defined. The state logic could remain in state 3 for as many clock pulses as is necessary to start the subprocess WRT. WRT, in turn, signals the state logic that the command to start has been received. There is no conditioning on the transition from state 4 to state 1. Therefore state 4

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will exist for a single clock period and in our example sets the flag flip-flop A before progressing back to state 1. Now that A is set, the transition from state 1 to state 2 will occur; when C is true state 5 will occur resetting A and finally, when DONE is true the state logic will recycle back to state 0, the idle state. Note that the state diagram compactly and yet completely describes the sequencing of this hypothetical device without a mention of how to implement it. Any device requiring sequential steps (i.e., a sequential state machine) can be described in a state diagram. Furthermore, a minimum number of states in a state diagram represents the true minimum of steps, no matter how it is implemented. That is to say, once a state diagram has been reduced to the minimum number of steps there is no other method which will yield fewer steps. A state diagram should never have a state that does not have a transition to another state. All conditional transitions should be labeled with the conditions of the transition. With these few rules the state diagram rigorously defines the sequencing of a state counter very easily. STATE COUNTER

The state counter is the hardware realization of a state diagram. Inasmuch as the state counter can only contain a single value at any given time there is no possibility of ambiguity. This seemingly trivial point has great impact on the design of a device because an often encountered design problem occurs when a device simultaneously issues two (or more) contradictory commands resulting in ambiguous action. No possibility exists for such ambiguity in state logic. Also it should be noted that a state counter does not necessarily count in linear sequences. The state counter in the example will count: 0, 1, 3, 4, 1, 2, 5, 0, etc. IMPLEMENTING

THE STATE COUNTER : A NEW TECHNIQUE

A great deal of investigation has been done on efficient methods of implementing devices such as state counters. Techniques such as diode minimization and Karnaugh maps are the results of the investigations. The reader who is interested in this older methodology might read Phister (5) or Chu (4) for a complete description. Today, with the advent of low cost, high speed medium and large scale integrated circuits, the designer is primarily concerned with minimizing integrated circuit count and connections between integrated circuits. It makes little difference if the logic within an integrated circuit is minimized. Using MS1 integrated circuits it is possible to design most of a state counter in a simple, rigorous way. Although we cannot prove the circuit is minimized (in terms of It’s), in every case we have tried, the IC count is less than the older methods (except in trivial cases where only one or two states are required). Most important of all, however, is the fact that the impIementation is simple to understand.

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The basic circuit is shown in Fig. 2. Implementation is shown for 7400~series transistor-transistor logic (TTL), currently the most commonly used digital logic. A 74175 quad D-flip-flop IC is used as the state counter register (SC4, SC2, SCl). A 7442 4-to-10 decoder is used to decode the binary number in the 74175 to a single line providing an indication of the current state (ST0 through ST7, complement). GND (EI)

I STOrl

CSTl-I

ST5 -

ST5 DONE

ST3SETSTO-

I\ r

ST3

SETSTZ-

FIG. 2. A state counter for the state diagram given in Fig. 1.

A 74148 8-to-3 priority encoder is used to interpret a series of “set state” terms. To set a state (cause a transition to a state) a single set state term is lowered and the output (SET4, SET2, SETl) will be encoded in binary. For example, if SETST4- is lowered a binary four will appear on the output of the 74148. If two set state terms are simultaneously lowered then the term with the highest priority (lowest numeric value) will be encoded without ambiguity. Additionally, when any set state term is lowered, EO goes low, which gates CLKto the 74175 via the nor gate. One can view this gating of the clock as a request by a set state for a clock pulse to change the 74175 to a new value. CLR is a term which will unconditionally reset the state counter to state 0. Usually it is used as a master reset to initialize all state counters to their idle state. IMPLEMENTINGTHESETSTATETERMS

Part of the rigor of this new technique stems from the fact that the counter/register is controlled only by positive assertions. With conventional state counter design one

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must be concerned with resetting counter flip-flops as well as setting them. Additional gating is required for reset terms and, worse yet, the additional gating confuses the reader. Simple gating is all that is required for set state terms. In the example, set state 2 is ST1 AND A; but because the bar-term is required, a nand gate is used. Notice that it is not necessary to define a set state 3 because one can take advantage of the priority encoding characteristics of the 74148. One can view this as a default option: if in state 1 and A is true then both SETSTZ- and SETST3- will be low; but since SETSTZ has priority, state 2 will be encoded and set. On the other hand, if A is false then the fact that state 1 is true is all that is required to set state 3. ADDITIONAL

COMMENTS

It is often desirable to connect light-emitting diodes to the state counter so as to provide a direct read-out of the current state. This is especially useful when performing maintenance in that it allows maintenance personnel a direct indication of the state in which the device is “hung up.” By referring to the state diagram one can deduce quite quickly the failure of a transition and begin to find the reasons for that failure. Although TTL logic has very good noise rejection characteristics. nevertheless electrically noisy devices such as solenoids can completely destroy normal operation if allowed to couple into the system. To prevent this occurrence we suggest the use of photo-optic devices with separate power supplies for the noisy equipment. This new method is in common use in our computer facility and scientists from several departments in the Medical School have begun to use state logic in their research equipment. CONCLUSIONS

The use of state logic in the design of digital devices has been described. Although used by some computer manufacturers, the application of state logic in biomedical research is almost nonexistent. Because it represents a simple, rigorous, minimal solution to the design of digital equipment of all types, the method should be included in instrumentation techniques for biomedical research. A principal advantage of state logic is the ability to represent in abstract form the sequential aspects of the device. Hence designers can communicate with others the logic flow in their devices without becoming entangled in the details of implementation. A new technique for implementing state logic is also described. Tn all but the most trivial cases this technique is probably minimal. More importantly the technique can be standardized for any digital device and its use is simple to understand, implement and debug.

STATE LOGIC

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A : A/D CONVERTER CONTROLLER

The following A/D converter controller illustrates the use of state logic (Fig. 3).

FIG. 3. State diagram for A/D converter controller.

Overall Design

A commercial A/D converter (DEC A81 1) capable of 100,000 lo-bit samples/set is sequenced in the following modes : (a) randomly addressed, where the multiplexer is set to a specific address; (b) sequentially addressed, in which the multiplexer is stepped to the next higher channel number before a conversion starts. A “goal’ register is provided so that, in the sequential mode, the multiplexer will step to the “goal” value and automatically recycle to zero (not shown on figure). When the recycle to “0” channel occurs a “special” interrupt is sent to the CPU (SPL-) (Fig. 4). In state 0 the A/D converter is in “idle” waiting for a command. Two different commands can start a conversion : either an MDCI 3 (no interrupt) or MDC12 (interrupt when conversion is complete). If the A/D converter is not in the process of converting (ADCDUNl is true) then go to state 1. State 1 sets the multiplexer from the data-out bus of the computer if the controller is in random mode or it counts the multiplexer to the next higher channel if in sequential mode. State 2 is entered on the next clock after state 1 unconditionally. State 2 echoes the CPU to indicate that the CPU can begin processing of the next command. The

300

KEHL,

MOSS

AND

DUNKEL

ST4 -

COMPAR

GND (EI),

ST7-

\-\

ST0 SETST5-

MDC If

SETSTO-

SETSTI

-

SETST2

-

SETSTB

-

EKO

FIG. 4. Controller for A/D converter. Several inverters and analog multiplexer not shown.

CPU, in turn, lowers either MDC12 or MDC13 (whichever was high) to indicate it is beginning the next instruction. As long as MDC12 or MIX13 is high the state logic remains in state 2. State 3 can be considered a time delay in the sense that it requires a clock interval to occur but accomplishes absolutely nothing. This delay is needed to ensure that

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the multiplexer, which requires 1 microsecond settling time, will have completely settled. State 4 issues the A/D convert command and the state logic unconditionally proceeds to state 0, the idle state. The basic clock frequency of this controller is 2.5 MHz or 400 nanoseconds. Thus 3 clock pulses (or 1.2 microseconds) elapse between setting the multiplexer (state 1) and starting the conversion (state 4). The sample converted by the A/D is gated to the CPU data-in bus whenever a conversion command (MDC12 or MDC13) is issued. Thus, for any conversion command, the last sample is sent to the CPU simultaneously with the start of the next conversion. For most of the 10 microsecond conversion time the CPU is free

FIG. 5. State diagram for simple reaction time with limited hold controller.

for other computation and, if the computation takes longer than 10 microseconds, only 800 nanoseconds of CPU time are required to take in the sample and to request the start of a new conversion, An MDC14 command sets the goal register and an MDCll command sets the random/sequential mode. MRSET is a master reset term that is distributed to all controllers in the system. The entire device can be fabricated for approximately $500 parts cost. APPENDIX

B : CONTROLLER POR SIMPLE REACTION TIME WITH LIMITED HOLD EXPERIMENTS

This controller has the following operation (Figs. 5 and 6).

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State 0 : Controller starts an intertrial interval timer (ITI) which insures that a minimum amount of time elapses between trials. Switch (SW) closures occurring before IT1 is complete recycle IT1 through State 2 back to State 0. State 1: Entered when ITI has elapsed without switch closures. Thus ready tone is turned on to indicate the beginning of the reaction time measurement. State 2 : Resets IT1 because of spurious switch closure. GND (EI)

[ST4-3

$nFT!?T

ST2 SW

ST5 sw-

SETST 3 -

SETSTG -

Ln SETST I ST5 LHSETSTP-

FIG. 6. State diagram for simple reaction time with limited hold controller.

State 3 : Turns off tone and starts the pseudorandom fore period timer (FP). State 4: When FP is completed the stimulus light, limited hold counter (LH) and reaction time counter are turned on, LH is set to maximum reaction latency which will be rewarded. State 5 : Waiting for decision to go to State 6 or 7. State 6 : If the switch has been opened before the LH period is complete, a successful trial has resulted; therefore record reaction time, turn on feeder and increment feed counter, recycle to start a new trial. State 7 : Limited period was completed without a switch opening and therefore no reward. Record an unsuccessful trial. Recycle to start a new trial. No attempt was made to show the various timers which could be made of either “one-shots” or counters.

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ACKNOWLEDGMENTS The authors wish to thank the editorial referees for referring to Zohavi and Glare. The book by Clare is especially useful for more advanced implementations of state logic while Zohavi’s book gives an excellent theoretical foundation. REFERENCES I. KOHAVI, ZVI. “Switching and Finite Automata,” McGraw-Hill, New York, 1970. 2. SMITH, STEPHEN, AND DAVID HOSTAK. Reliability Report for Series 54/74 TTL, Texas Instruments Publication Report CR-103. 3. CLARE, CHRISTOPHER. “Design Logic Systems Using State Machines,” McGraw-Hill, New York, 1973. 4. CHU, YAOCHAN. “Digital Computer Fundamentals,” McGraw-Hill, New York, 1962. 5. PHISTER, MONTGOMERY. “Logical Design of Digital Computers,” Wiley, New York, 1960.