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The VLSI design of a two dimensional image processing array
North-Holland Microprocessing and Microprogramming 14 (1984) 125-132
125
The VLSI Design of a Two Dimensional Image ProcessingArray Dimokritos Panogiotopoulos
Nikolaos Bourbakis
University of Maryland School of Engineering Dept. of Electrical Engineering College Park, MD 20742, USA
The State Univ. of Northern Virginia George Mason - Dept. of Electrical and Computer Eng., 4400 University Drive, Fairfax, VA 22030, USA
ABSTRACT This paper presents the VLSI design of a two dimensional Image Processing Logic Array (IPLA). The IPLA consists of a two dimensional logic frame of nxn photodiodes, a set of decoders, a counter and some other useful components such as amplifiers gates etc. The IPLA enables whichever digital version of the image is to be created either by hardwired logic or under computer control; it can rapidly give one or more picture scan outputs (set of pels) simultaneously. Also, that array can immediately provide the total average intensity of the whole image or image part, that is an important factor in making quick decisions for the further processing such as regular decomposition, transformation, transmlttlon etc. The IPLA attempts to speed up the picture processes such as creation of hierarchical data structures, object detection and extraction, parallel, plpelined hierarchical orthogonal transformations etc., by scanning the logic array in various desired ways and providing the scanned pixels to the processor(s).
I.
INTRODUCTION
The high evolution of the Integrated Circuits (IC) in the last decade push up the solid state image scanning devices. In many applications the CRT could be replaced with photosensive two-dimensional arrays and the main reasons are such as low cost, small size, little weight, high fidelity, high speed, low noise in [1,2,4,5,6,11,12,13,14,15,16] are explained. To date most of the developments of these image devices have centered on MOS-types devices, such as MOS, CCD or CID sensors and their performance have progressed to a level of practical usage; recently a plasmacoupled bipolar linear image sensor has been devised [I] which has improved performance over the precedings. The effort was made to replace the CRT with ICs, but not to improve the image scanning techniques that used the CRT. The proposed Image Processing Logic Array (IPLA) accepts the original image at its photosenslve grid of nxn photocells, Each photocell gives a current that goes into the corresponding amplifier. The produced currents are halted at the set of n amplifiers which do not allow the currents to pass to the next system parts unless if they are selected to do so. A counter, that counts from an initial number to a final one, determines the total number of cells which will be scanned. The choice of a proper decoder will determine the scanning mode of the cells. This means
that, a proper sequence of cell currents will pass from the amplifiers to the main amplifier and after that to the A/D converter in order to realize their equivalent digitized versions. The digitized version of each cell current (e.~. an 8-bit number if 256 grey levels are required enters) the main computer for further processing such as image data structures, feature extraction etc. The IPLA has the ability to produce the total average intensity of any image part, immediately, by using an internal automatic gain control (AGC) in its amplifier system. This feature is a significant factor for the decision making for a future picture processing such as regular decomposition (RD). The RD method defines a four successor tree which retains expllcity a hierarchical description of picture pattern elements and their geographical relationships [I0]. The IPLA can scan an image by raster or other method faster and more stable than a scanning CRT device [2,3,12]. It can also realize some scanning techlques that are not feasible with CRT devices such as Z-scan. The Z scanning method proceeds successively through image elements organized like the capital letter Z, repeating according to a larger Z until the last point of the image is adjusted. The Z-scan contributes for fast pyramid data structures [12]. This paper is divided into three main sections. The first section incoudes a brief description of the IPLA structure and operation. In the second section the detailed
D. Panogiotopoulos, N. Bourbakis / Design of a Two Dimensional Image ProcessingArraF
126
analysls-deslgn of the photo-senslve circuits and the integration technique of the IPLA are presented. The last section gives some comparisons of the IPLA with the Intel 8086 UP chip on complexity to show the behavior and the possibilities of the proposed array. 2.
If the EN input is one then the counter is activated, and with a proper DENi=I , i=l,...,m, one of the m decoders is chosen to be drlved from the counter. The Ith decoder determines a proper scanning of cells without the usage of a computer algorithm. The Ith decorder activates in a proper scanning sequence the ST inputs of the A j 1 < j < n~
IPLA STRUCTURE AND OPERATION
The structure and operation of the IPLA have been described in detail [18], thus a brief description is given at this section. Inltlaly, the original picture is applied on the IPLA photogrld by using a system and lens. The IPLA structure for n=4 is shown in Figure (1).
i,~. Llllle~e
:- 4 - ~
i~-~_-~c-
il
i
i
l
:
•
'~-~"
-
-
amplifies. From the switches the sequence of the cell currents proceed to the main system amplifier and that to the A/D converter to glve the corresponding sequence of digitized versions (b~inary numbers).
-
I .........
',
.p:-i.-i-~--..;
-I
In the Figure (I) the IPLA has only one output; however more than one outputs can b@ obtained if the nodes Ki, i=o, 1,2,...,n~-I are not immediately shorted, but are connected through a combination of digital switches (n l)(n +2)/2 and by addition of more than one output circuits [11,18].
.~ .~, f ' ~ . l - ~ F t ' t > , 3.
IPLA ANALYSIS AND DESIGN
. . . . .
~_-.:
In this section the analytical design and the integration technique of the IPLA are described. In the first part of this section the analytical design of the photosenslve circuits is given, while in the second the IPLA integration is presented.
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3.1. i &.
PHOTOSENSIVE CIRCUITS
#
The photosenslve circuits are basic components for the implementation of the IPLA, thus, an extented description is given here. In the Figure (2) an equivalent circuit for the Ao
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,,
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r--,,~.
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= + Vcc
7
I,
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~I
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11[
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M A • Sli. Ampl~iev Fig. l:The scanning system in block diagram,
for
n:~
When the EN input is zero the counter does not count and there is not2scannlng; then the Mean Value Decoder (g-to-n-) is chosen. The outputs from the M.V.D. turn the ST inputs of the amplifiers. Thus the photocurrents are summarized and averaged by using an internal Automatic Gain Control (AGC), and the input to the main amplifier is analogous to the total average intensity of the chosen part of the picture.
i .
',
$1r ' .... J Fig.
2:Phozosensing circuits.
amplifier is shown, with its connection to the corresponding photodlode, to the other A1 amplifiers and to the output circuit. All Ai amplifiers are identical.
D. Panogiotopoulos, N. Bourbakis / Design of a Two Dimensional Image ProcessingArray The stored charge in the photodiode is expressed the product of photodiode capacitance ~.i(V) and bias voltage V applied to the pMotodlode, or the product of photocurrent density Tph, the photosenslng window area Aw, and time t.
:_/¢
Q
_
Cj (V) dv = Aw . / o
Jphdt
(i)
assuming a one-slded abrupt Junction, where
but
where If
~
(5)
is the hfe parameter of the BJTs
Ra=RB=R
then
k~l (6+l)R-i=0
IRi
I+K(6+I)
K (6+1) >> i, they
VI =
R k~l IRi "i=O K
= IE, R
IE=
kil_ i=01Ri K
D NA_ ]
A is the photodlode Junction area, N A the density of acceptors in the p-type material, ND the density of donors in the n-type material, ~0 the built-in potential, and q, , g are the usual notations. B 7 ga~ing the stored charge in the photodiode, and input current i . is delivered to the n following A. amplifier. Its waveform is I expressed by i . = I ..exp (-t/z^), pn n u where zO is an experimental delay time constan~ which is determined by photodlode discharge, the amplifier frequency characteristics, and the pulse waveform applied on the ST input (fig. 2). The current rise time constant is governed by the RC-time constant of the photodlode, and neglected in the following analysis because is smaller than zO. The relation between Q and iph is expressed by
IE= I-R '
ic
=-
where
Ic
=
~
iphdt
=
(6)
I R is the arithmetic mean value of
• IR I' "''IR(k_l )"
Ka.~O +
I$ +Vcc
ZOlph
V~p-['[*O+ V~p-2 ( A w / K a ) ]
"
Thus the total current
[ = (IR+ k I R) j that flows from the cells and am~llfleF system, excluding the main amplifier into the chip of the imaging device is small enough even if k is very large, because IR is very small (a few ~A).
Substituting (2) into (I) the following expression for the photodlode charge Q results =
8 6+1 "IE
6+--T"
-7
. h~
j,
"
~a
Q
(4)
Vl= Ra + K ({Prl)Rb
Vl =
Q
V B E + 121" Ra
Appling KCL equations to node Ki, and using eq. (4), after manipulation, it is obtained that k~l (IJ+I)R.aR~" i=01Ri
Where V is the instantaneous photodlode potenti~l, V B the dc-bias pontentlal fed through the n-~-n and p-n-p transistors Fig. (2), and the function of Vcc, and Ts the integration time. The depletion capacitance C,(V) is a function of the bias voltage V and i~ given by K cj(v) = a (2) 1/2 2 (~o-V)
a
VA = i=O,l,2,...,k-I
where
127
l¢ Z, I
(~)
Is
In the following only the average peak value will be treated, such as Iph = Q/z O. A brief analysis of the circuit in fig. (2) is done below, to show how the internal AGC works. The nodes K i are short-clrculted and they have the same poEentlal V A.
1
,
v0
Fig.
3:Practical photosensing
circui%s,
D. Panogiotopoulos, N. Bourbakis / Design of a Two Dimensional ImageProcessingArray
128
In fig. (3) the actual circuit of the A i amplifier connected to the main amplifier (MA) is shown. The output voltage of the circuit in fig. (3a) is V 0 = - a.B.Iph. ~ (7) where
Iph
= Q/z 0
and substituting into
V0 = - a . ~ . ( Q / z o ) RL
(8)
The output circuit in fig (3b) uses a current Mode (Norton) Amplifier, the LMI59 (National Semiconductor). The diode D is added in order to prevent the precedent transistor from entering into saturation. The output voltage of this circuit is:
v 0 = a. - ~ TB - "
(Q/z0) Rf
(9)
From the photocurrent density J h=n.P.l.q/c h induced by the irradiation l~put power P ( w / c m ) and (8), (9) the voltage sensitivity per incident energy, V out S A .P .T
w
s
S.2 INTEGRATION OF THE IPLA In this paragraph, ideas about the integration of the IPLA are discussed. The IPLA (Fig. I) cannot be separated in more than one chips, except for the counter system and the main amplifier(s), if it is necessary, because its blocks are connected on the system bus, which consists of n lines, and in practical appllcation~ this'number is large enough; if n=256 then n~=65536. The presented array could be constructed on a silicon wafer, of a proper diameter using the usUall fabrication techniques, which recently have been improved [5,6]. Today the IC_ manufactures use the one side (surface) of a silicon wafer, in order to built the circuits. Of course this technique can be used for the fabrication of the proposed processing array but presents disadvantages because of the number of wirings and the fact that the photosensing area must not be covered from wirings and the partition lines between photodlodes must be e~tremely thin In order to have picture loss (P.L.) so that lim (PL)--~I, where
is determined by
Etotal 2 n
PL S = - a. fi n.X.q ch.z 0
.RL
(10)
i~I El
for the circuit In fig. (3a) or S
=
a.
~+1 "
n.l.~ ch.z 0
Rf
(11)
(E total is the total surface of the photosenslng area and E i is the surface of the i th photodlode).
for the circuit in fig. (3%). The advantage of the circuit in fig. (3a) is that it is very simple, so it is advantageous to use it when the number of outputs of the IPLA is big enough; the disadvantages of this circuit is that its output is depended directly on parameter B of the transistors in the output circuit, and on load ~ (equation 8). Thus all output circuits mus~ have transistors with the same parameter S for reliable results; also the total mean value of the picture, or part of the picture, must be read in the same speed as each plxel in the normal scanning because the parameter is depended on the frequency of operation. The only disadvantage of the circuit in fig. (3%) is its complexity comparing it with that of fig. (3a). The advantages of this circuit arise from its feedback; it is almost ~ n d e pended from parameter ~, because - = a, which is almost constant if ~ >> I ~a~d it is not depended on load. In both circuits it is easy to control the gain and so the output level, if the P~ is a Voltage Variable Resistor (V.V.R) in f~g. (3a), or if the Rf is a V.V.R in fig. (3%). This is important If a picture has to been scanned in darkness or strong light.
In order to solve these problems the usage of both side of a silicon disk is proposed. The ion implantation technique is used for the construction of photodiodes on one side, and the construction of the necessary circuits on the other side. The connection between photodlodes and A i amplifiers is done inside the wafer by diffused columns (Fig. 4).
~T T ~ .
of th, A;
Fig.
4:
If
n=256
NP, T~.~. of the A~
The c o n n e c t i o n A. a m p l i f i e r 1 the
of
photosensing
the
i ~- p h o t o d i o d e
area
is
LxL,
to
L=~m
and the width of partition lines is l~m, then the photodiode junction area is dxd, and d = (L/n) - 2xl~m d=llb~m. Under this
D. Panogiotopoulos, IV. Bourbakis / Design of a Two Dimensional Image Processing Array
area the A i amplifier is constructed (fig. 4). The A i amplifier, whose circuit diagram is shown in fig. (3), does not use two separate p-n-p transistors, but one p-n-p with two collectors (fig. 5a). In figure (Sb) the IC construction of the A i amplifier is shown; the p-n-p is a double diffused type transistor because high fT is needed. To i ~ o l o d i o d e
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',
ci
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,,
i
I
"
In this section some graphical presentations on complexity (c), number of outputs, (w) number of decoders (d), number of photocells (n) and scanning time ( t ) are presented to give an optical view of ~he behavior and the possibilities of the IPLA implementation. It is also given at these graphical representations the complexity (by capital letter O) of the known microprocessor 8086 chip (INTEL Co.) in order to be compared with the complexity of the proposed IPLA system.
better consideration of the theme. Concretely, two tables with significant points are given in [2,12]. The first table contains the construction sizes by IC technology of the IPLA for n=I,4,16,...,246, the refreshment time and the scanning time. In the second table are presented 20 different comparative points as: scanning time by several system types, picture loss, stability of scanning, cells overlapping, cost of system implemenptat[on, system complexity, inactivity, precision, discreetness, etc. at which a comparison among three image scanning systems (raster, vector, IPLA) takes place. After this comparison the advantage-points on which the IPLA excels over the other systems are 12, while has I negative-point on 20 comparative points.
I
(O) A L ~,epll,tillST
?
Fig.. 5:a)The circuit of the A. amplifier, b)Ti~c IC lmplementat~on " z of the Ai amplifier. .
In figure (6) a ground-plan of the IPLA is shown. If the IPLA is constructed to have only one output, the digital switches area and the output circuits area are omitted and the output circuit is constructed in the counter decoders area.
"//X/ ~, > 3,'#/ / / / / / / / ~ ,.. ~
SOME COMPARISONS OF IPLA WITH 8086 CHIP
Previously, some important features for the proposed IPLA are referred to assist in the
To ~.ode KL
I
ST
&.
129
-
//
T.,-L--,~,~?q !" "
The following diagrams show the variation of the decimal logarithm of the IPLA complexity (c) versus the binary logarithm of (n), with parameter (d), (w), (ts). The function c = f(n) is discrete and is determined for (log2n)a [Z]5 the parameter (d) represents the number o~ decoders except of the X,XY and M.V. decoders; and alternatively the number of the built in scanning techniques.
\~=0
J
71
l&~'/..II l ! ~ l \\-.>x,
Fig. 6:The g~.pund plan of zhe scanning system (it is not under scale).
Fig. 7:Graphicalpresentationof complexityC , numberof photosensltire elementsn, with the parameter~ fop one ouTpu~w-l.
D. Panogiotopoulos, N. 8ourbakis /Design of a Two Dimensional ImageProcessingArray
130
~//
q-w:! ~- w=&
I
)V= 2$&
I / /
W : 4615# 4-
0
I
2
3
&
S
6
7
8
9
40
4!
12
W : &S53~
,~3 I ~
Pig. ~O:Graphical presentalion of scannin~ lime in relallon ship with the photocells number n using neperlous logarilhms.
5. I
I
i
I
I
l
I
i
:
0
t
Z
S
4
5
6
7
t
9
Fig.
B:C~aphical preaentatlon of complexity C , number of outputs w
I~¢j:tW
with parameter n,
(n=6g,128,256,512), d-~.
t q . 156 --
w 1+121
~
w-6*,
~w,$Z
.--w:I
?t
CONCLUSION AND EXTENSION
In this paper the implementation of a realtlme and programmable image processing logic array by VLSI technology was discussed. Its operation way was also presented. However, there are some points which could be extented as the generalization for pictures nxm. The proposed array could be successfully used on a robot eye realizing different kinds of scanning (sequential, parallel or both) which approach to the human eye behavior [19]. Concretely, the human eye can in parallel give a global perception of all objects (which are contained into the optical area) which it covers, or immediately give significant details about an object which is found in the center of the optical area. The presented array can be operated by the same way, by supporting it with a proper system of lens and a hierarchical multimicroprocessors system [20].IPLA has an important feature, that can in parallel and immediately give the significant information for more than one objects which are found at different places into the optical area [19]. Another important feature of this array is that it can create data structures (as pyramid, cone [9,12] and the proper scanning for the easy, fast picture processing, [2,7,12]. Finally, the presented IPLA compared with he raster scanning, vector scanning systems presents significant advantages on the scanning time, applications, scanning techniques etc. and only one disadvantage, [2] the compllcatlty which moderates with the evolution of the I.C. technology.[18] Fig.
9:Graphical pmesentation of the variation of the decimal loEarlthm of the complexity of The scanning system versus the blnamy logarlthm of n, with parameter w, and Jar.
D. Panogiotopoulos,N. Bourbakis/ Design of a Two Dimensional ImageProcessingArray
131
REFERENCES
(1)
MASAHIRO SAKAUE, TERUO TAMAMA, and YOSHIHIKO MIZUSHIMA; "Plasma-Coupled Bipolar Linear Image Sensor", IEEE Trans. on Electron Devices May 1981, Vol. ED-28, pp. 517-522.
(2)
N.G. BOURBAKIS and D.A. PANAGIOTOPOULOS; "Image Scanning Techniques and Real Time Dynamic and Programmable Scanning System", Report, Univ. of Patras, Sch. of Engl., Chair of Comp. Sci., RRgl-01, 1981.
(3)
A. KLINGER and H. KELUDJIAN; "A Proposal for on-line feature Detection and Extration", Proceedings 1972, Computer Image Processing Recognition Symposium.
(4)
(5)
ESMAT Z. HAMDY, MOHAMED I. ELMASRY, YOUSEF A. EL-MANSY; 'Single-Device-well MOSFETs", IEEE Trans, on Electron Devices, March 1981, Vol. ED-28, pp. 322327. MARTIN P. LEPSELTER; "X-ray lithography breaks the aubmicrameter Barrier", IEEE Spectrum, May 1981, pp. 26-29.
(i 3)
L.E.TANNAS and W.F.COODE "APPLICATIONS DISPLAYS: Flat Panel Displays a Critique", IEEE Spectrum, July 1978, pp. 26-32.
(14)
P. STUCKI 'Solid State Area Scanning Arrays as Interface Devices between Optical and Digital Computing System, A Simulation Study", IEEE Trans. on Computers, Vol. C-24, No. 4, April 1975, pp. 370-380.
(15)
E. BRACHA "Digital Picture with a Parallel Processor System "IEEE Computer Society Report, R-78-235, Nov. 1978.
(16)
H. ANORIEWS "Spatial Resolution: Requirements for Real-Time Digital Displays", IEEE Trans on Computers.
(17)
N. BOURBAKIS, M. PAPAZOGLOU, C. ALEXOPOULOS and G. ALEXIOUS "An Efficient Preprocessing Image System" Proc. of Int. Symp. on MECO-83, Athens, Greece.
(la)
N.BOURBAKIS and D. PANAGIOTOPOULOS "An Efficient Real-Time Image Scanning System", Proc of IEEE Int. Conf. on Computers, Systems and Signal Processing, Bangalore, India, Dec. 10-12, 1984.
(6)
JOHN C. EIDSON; "Fast electrom-beam Lithography", IEEE Spectrum, July 1981, pp. 24-28.
(7)
N. BOURBAKIS "On microcomputers-based parallel image processing machine", Proc. of Forth lASTED international Symposium MECO-81, Aug. 31-Sept 3, Cairo, Egypt 1981.
(19)
N. BOURBAKIS and D. PANAGIOTOPOULOS "A Proposal for the Design of a Robot Eye" Proc. of Int. Symp. on Robotics, March 2-5, 1982, Davos, Switzerland, pp. 2023.
(8)
S. TANIMOTO and T. PAYLIDIS "A Hierarchical Data Structure for Picture Processing", Int. Journal on CGIP 4, pp. 104-119, 1975.
(2o)
(9)
S. TANIMOTO and A. KLINGER, "Structured Computer Vision", Academic Press 1980, New York.
BOURBAKIS N. and VAITSOS C. "A Multimicroprocessor Tree Network Configuration used on Robot Vision Systems", Proc. of Int. Meeting on Digltech-84, July 12-14, 1984, Patras, Greece, North Holand Pub. Co.
(lO)
A. KLINGER and R. C. DYER, "Experiments on Picture Represtation using Regular Decamposltion" Scientific Research, Air Force Systems Command USAF, undergrant No AFOSR-72-2384, July 1974.
(11)
D.A. PANAGIOTOPOULOS and N.G. BOURBAKIS, "A new dynamic, real-tlme and programmable image scanning system by VLSI technology", Research Report, Chair of Computer Science, Univ. of Patras, RR03-81, Patras, 1981, Greece.
(12)
N. BOURBAKIS "New, Real Time Processing Methods of Structured Images", PhD thesis, Univ. of Patras, Sch. of Eng., Dept. of Comp. Sci. Patras 1982.
132
D. Panogiotopoulos, N. Bourbakis /Design of a Two Dimensional Image ProcessingArray
DIMOKRITOS PANAGIOTOPOULOS was born in Thessaloniki Greece in 1960. He received his Diploma in Electrical Engineering from Patras University, Greece in 1982 and his MSc in Electrical Engineering from the University of Maryland. He is now a PhD student in the Electrical Engineering Department of Maryland University. He has given various courses in Computer Science, both as teaching assistant and lab instructor. His current intrests include Multimicroprocessor Systems, Robot Vision, Knowledge Systems, Expert Systems.
NIKOLAOS BOURBAKIS was born in Chania-Crete, Greece in 1950. He received his BS~ degree in Mathematics from the National University of Athens, Greece in 1975. He has studied towards his PhD in" the Department of Computer Engineering at the University of Patrasr Greece (1978) and he received his PhD in 1982. He has taught various courses in Computer Science as teaching assistant, lab instructor and lecturer in the Computer Engineering Department, Patras University, Greece (1978-1984). Now he is an Assistant Professor in Electrical and Computer Engineering at the G. Mason University. His current interests include Image Processing, Multimieroprocessor Systems, Data Structures, Robot Vision Systems, Expert Systems and Picture Information Systems.
125
The VLSI Design of a Two Dimensional Image ProcessingArray Dimokritos Panogiotopoulos
Nikolaos Bourbakis
University of Maryland School of Engineering Dept. of Electrical Engineering College Park, MD 20742, USA
The State Univ. of Northern Virginia George Mason - Dept. of Electrical and Computer Eng., 4400 University Drive, Fairfax, VA 22030, USA
ABSTRACT This paper presents the VLSI design of a two dimensional Image Processing Logic Array (IPLA). The IPLA consists of a two dimensional logic frame of nxn photodiodes, a set of decoders, a counter and some other useful components such as amplifiers gates etc. The IPLA enables whichever digital version of the image is to be created either by hardwired logic or under computer control; it can rapidly give one or more picture scan outputs (set of pels) simultaneously. Also, that array can immediately provide the total average intensity of the whole image or image part, that is an important factor in making quick decisions for the further processing such as regular decomposition, transformation, transmlttlon etc. The IPLA attempts to speed up the picture processes such as creation of hierarchical data structures, object detection and extraction, parallel, plpelined hierarchical orthogonal transformations etc., by scanning the logic array in various desired ways and providing the scanned pixels to the processor(s).
I.
INTRODUCTION
The high evolution of the Integrated Circuits (IC) in the last decade push up the solid state image scanning devices. In many applications the CRT could be replaced with photosensive two-dimensional arrays and the main reasons are such as low cost, small size, little weight, high fidelity, high speed, low noise in [1,2,4,5,6,11,12,13,14,15,16] are explained. To date most of the developments of these image devices have centered on MOS-types devices, such as MOS, CCD or CID sensors and their performance have progressed to a level of practical usage; recently a plasmacoupled bipolar linear image sensor has been devised [I] which has improved performance over the precedings. The effort was made to replace the CRT with ICs, but not to improve the image scanning techniques that used the CRT. The proposed Image Processing Logic Array (IPLA) accepts the original image at its photosenslve grid of nxn photocells, Each photocell gives a current that goes into the corresponding amplifier. The produced currents are halted at the set of n amplifiers which do not allow the currents to pass to the next system parts unless if they are selected to do so. A counter, that counts from an initial number to a final one, determines the total number of cells which will be scanned. The choice of a proper decoder will determine the scanning mode of the cells. This means
that, a proper sequence of cell currents will pass from the amplifiers to the main amplifier and after that to the A/D converter in order to realize their equivalent digitized versions. The digitized version of each cell current (e.~. an 8-bit number if 256 grey levels are required enters) the main computer for further processing such as image data structures, feature extraction etc. The IPLA has the ability to produce the total average intensity of any image part, immediately, by using an internal automatic gain control (AGC) in its amplifier system. This feature is a significant factor for the decision making for a future picture processing such as regular decomposition (RD). The RD method defines a four successor tree which retains expllcity a hierarchical description of picture pattern elements and their geographical relationships [I0]. The IPLA can scan an image by raster or other method faster and more stable than a scanning CRT device [2,3,12]. It can also realize some scanning techlques that are not feasible with CRT devices such as Z-scan. The Z scanning method proceeds successively through image elements organized like the capital letter Z, repeating according to a larger Z until the last point of the image is adjusted. The Z-scan contributes for fast pyramid data structures [12]. This paper is divided into three main sections. The first section incoudes a brief description of the IPLA structure and operation. In the second section the detailed
D. Panogiotopoulos, N. Bourbakis / Design of a Two Dimensional Image ProcessingArraF
126
analysls-deslgn of the photo-senslve circuits and the integration technique of the IPLA are presented. The last section gives some comparisons of the IPLA with the Intel 8086 UP chip on complexity to show the behavior and the possibilities of the proposed array. 2.
If the EN input is one then the counter is activated, and with a proper DENi=I , i=l,...,m, one of the m decoders is chosen to be drlved from the counter. The Ith decoder determines a proper scanning of cells without the usage of a computer algorithm. The Ith decorder activates in a proper scanning sequence the ST inputs of the A j 1 < j < n~
IPLA STRUCTURE AND OPERATION
The structure and operation of the IPLA have been described in detail [18], thus a brief description is given at this section. Inltlaly, the original picture is applied on the IPLA photogrld by using a system and lens. The IPLA structure for n=4 is shown in Figure (1).
i,~. Llllle~e
:- 4 - ~
i~-~_-~c-
il
i
i
l
:
•
'~-~"
-
-
amplifies. From the switches the sequence of the cell currents proceed to the main system amplifier and that to the A/D converter to glve the corresponding sequence of digitized versions (b~inary numbers).
-
I .........
',
.p:-i.-i-~--..;
-I
In the Figure (I) the IPLA has only one output; however more than one outputs can b@ obtained if the nodes Ki, i=o, 1,2,...,n~-I are not immediately shorted, but are connected through a combination of digital switches (n l)(n +2)/2 and by addition of more than one output circuits [11,18].
.~ .~, f ' ~ . l - ~ F t ' t > , 3.
IPLA ANALYSIS AND DESIGN
. . . . .
~_-.:
In this section the analytical design and the integration technique of the IPLA are described. In the first part of this section the analytical design of the photosenslve circuits is given, while in the second the IPLA integration is presented.
.... _?--,, ,,,
~i I,', ::~
iil ' l:i ,! J
i:ii : il ,,Ill
3.1. i &.
PHOTOSENSIVE CIRCUITS
#
The photosenslve circuits are basic components for the implementation of the IPLA, thus, an extented description is given here. In the Figure (2) an equivalent circuit for the Ao
I r !iii li.
i(,,
~ :''
F ! ' : T i '¸
!IL: ~it~il:!!
,,
/
¸:'
r--,,~.
Xr~ , ,, " ~,, -
= + Vcc
7
I,
r-T-
fT
'
.---j ° vA:
~ - "
~I
VoLd: ~VI
11[
,!
I
M A • Sli. Ampl~iev Fig. l:The scanning system in block diagram,
for
n:~
When the EN input is zero the counter does not count and there is not2scannlng; then the Mean Value Decoder (g-to-n-) is chosen. The outputs from the M.V.D. turn the ST inputs of the amplifiers. Thus the photocurrents are summarized and averaged by using an internal Automatic Gain Control (AGC), and the input to the main amplifier is analogous to the total average intensity of the chosen part of the picture.
i .
',
$1r ' .... J Fig.
2:Phozosensing circuits.
amplifier is shown, with its connection to the corresponding photodlode, to the other A1 amplifiers and to the output circuit. All Ai amplifiers are identical.
D. Panogiotopoulos, N. Bourbakis / Design of a Two Dimensional Image ProcessingArray The stored charge in the photodiode is expressed the product of photodiode capacitance ~.i(V) and bias voltage V applied to the pMotodlode, or the product of photocurrent density Tph, the photosenslng window area Aw, and time t.
:_/¢
Q
_
Cj (V) dv = Aw . / o
Jphdt
(i)
assuming a one-slded abrupt Junction, where
but
where If
~
(5)
is the hfe parameter of the BJTs
Ra=RB=R
then
k~l (6+l)R-i=0
IRi
I+K(6+I)
K (6+1) >> i, they
VI =
R k~l IRi "i=O K
= IE, R
IE=
kil_ i=01Ri K
D NA_ ]
A is the photodlode Junction area, N A the density of acceptors in the p-type material, ND the density of donors in the n-type material, ~0 the built-in potential, and q, , g are the usual notations. B 7 ga~ing the stored charge in the photodiode, and input current i . is delivered to the n following A. amplifier. Its waveform is I expressed by i . = I ..exp (-t/z^), pn n u where zO is an experimental delay time constan~ which is determined by photodlode discharge, the amplifier frequency characteristics, and the pulse waveform applied on the ST input (fig. 2). The current rise time constant is governed by the RC-time constant of the photodlode, and neglected in the following analysis because is smaller than zO. The relation between Q and iph is expressed by
IE= I-R '
ic
=-
where
Ic
=
~
iphdt
=
(6)
I R is the arithmetic mean value of
• IR I' "''IR(k_l )"
Ka.~O +
I$ +Vcc
ZOlph
V~p-['[*O+ V~p-2 ( A w / K a ) ]
"
Thus the total current
[ = (IR+ k I R) j that flows from the cells and am~llfleF system, excluding the main amplifier into the chip of the imaging device is small enough even if k is very large, because IR is very small (a few ~A).
Substituting (2) into (I) the following expression for the photodlode charge Q results =
8 6+1 "IE
6+--T"
-7
. h~
j,
"
~a
Q
(4)
Vl= Ra + K ({Prl)Rb
Vl =
Q
V B E + 121" Ra
Appling KCL equations to node Ki, and using eq. (4), after manipulation, it is obtained that k~l (IJ+I)R.aR~" i=01Ri
Where V is the instantaneous photodlode potenti~l, V B the dc-bias pontentlal fed through the n-~-n and p-n-p transistors Fig. (2), and the function of Vcc, and Ts the integration time. The depletion capacitance C,(V) is a function of the bias voltage V and i~ given by K cj(v) = a (2) 1/2 2 (~o-V)
a
VA = i=O,l,2,...,k-I
where
127
l¢ Z, I
(~)
Is
In the following only the average peak value will be treated, such as Iph = Q/z O. A brief analysis of the circuit in fig. (2) is done below, to show how the internal AGC works. The nodes K i are short-clrculted and they have the same poEentlal V A.
1
,
v0
Fig.
3:Practical photosensing
circui%s,
D. Panogiotopoulos, N. Bourbakis / Design of a Two Dimensional ImageProcessingArray
128
In fig. (3) the actual circuit of the A i amplifier connected to the main amplifier (MA) is shown. The output voltage of the circuit in fig. (3a) is V 0 = - a.B.Iph. ~ (7) where
Iph
= Q/z 0
and substituting into
V0 = - a . ~ . ( Q / z o ) RL
(8)
The output circuit in fig (3b) uses a current Mode (Norton) Amplifier, the LMI59 (National Semiconductor). The diode D is added in order to prevent the precedent transistor from entering into saturation. The output voltage of this circuit is:
v 0 = a. - ~ TB - "
(Q/z0) Rf
(9)
From the photocurrent density J h=n.P.l.q/c h induced by the irradiation l~put power P ( w / c m ) and (8), (9) the voltage sensitivity per incident energy, V out S A .P .T
w
s
S.2 INTEGRATION OF THE IPLA In this paragraph, ideas about the integration of the IPLA are discussed. The IPLA (Fig. I) cannot be separated in more than one chips, except for the counter system and the main amplifier(s), if it is necessary, because its blocks are connected on the system bus, which consists of n lines, and in practical appllcation~ this'number is large enough; if n=256 then n~=65536. The presented array could be constructed on a silicon wafer, of a proper diameter using the usUall fabrication techniques, which recently have been improved [5,6]. Today the IC_ manufactures use the one side (surface) of a silicon wafer, in order to built the circuits. Of course this technique can be used for the fabrication of the proposed processing array but presents disadvantages because of the number of wirings and the fact that the photosensing area must not be covered from wirings and the partition lines between photodlodes must be e~tremely thin In order to have picture loss (P.L.) so that lim (PL)--~I, where
is determined by
Etotal 2 n
PL S = - a. fi n.X.q ch.z 0
.RL
(10)
i~I El
for the circuit In fig. (3a) or S
=
a.
~+1 "
n.l.~ ch.z 0
Rf
(11)
(E total is the total surface of the photosenslng area and E i is the surface of the i th photodlode).
for the circuit in fig. (3%). The advantage of the circuit in fig. (3a) is that it is very simple, so it is advantageous to use it when the number of outputs of the IPLA is big enough; the disadvantages of this circuit is that its output is depended directly on parameter B of the transistors in the output circuit, and on load ~ (equation 8). Thus all output circuits mus~ have transistors with the same parameter S for reliable results; also the total mean value of the picture, or part of the picture, must be read in the same speed as each plxel in the normal scanning because the parameter is depended on the frequency of operation. The only disadvantage of the circuit in fig. (3%) is its complexity comparing it with that of fig. (3a). The advantages of this circuit arise from its feedback; it is almost ~ n d e pended from parameter ~, because - = a, which is almost constant if ~ >> I ~a~d it is not depended on load. In both circuits it is easy to control the gain and so the output level, if the P~ is a Voltage Variable Resistor (V.V.R) in f~g. (3a), or if the Rf is a V.V.R in fig. (3%). This is important If a picture has to been scanned in darkness or strong light.
In order to solve these problems the usage of both side of a silicon disk is proposed. The ion implantation technique is used for the construction of photodiodes on one side, and the construction of the necessary circuits on the other side. The connection between photodlodes and A i amplifiers is done inside the wafer by diffused columns (Fig. 4).
~T T ~ .
of th, A;
Fig.
4:
If
n=256
NP, T~.~. of the A~
The c o n n e c t i o n A. a m p l i f i e r 1 the
of
photosensing
the
i ~- p h o t o d i o d e
area
is
LxL,
to
L=~m
and the width of partition lines is l~m, then the photodiode junction area is dxd, and d = (L/n) - 2xl~m d=llb~m. Under this
D. Panogiotopoulos, IV. Bourbakis / Design of a Two Dimensional Image Processing Array
area the A i amplifier is constructed (fig. 4). The A i amplifier, whose circuit diagram is shown in fig. (3), does not use two separate p-n-p transistors, but one p-n-p with two collectors (fig. 5a). In figure (Sb) the IC construction of the A i amplifier is shown; the p-n-p is a double diffused type transistor because high fT is needed. To i ~ o l o d i o d e
'
',
ci
!
~
,,
i
I
"
In this section some graphical presentations on complexity (c), number of outputs, (w) number of decoders (d), number of photocells (n) and scanning time ( t ) are presented to give an optical view of ~he behavior and the possibilities of the IPLA implementation. It is also given at these graphical representations the complexity (by capital letter O) of the known microprocessor 8086 chip (INTEL Co.) in order to be compared with the complexity of the proposed IPLA system.
better consideration of the theme. Concretely, two tables with significant points are given in [2,12]. The first table contains the construction sizes by IC technology of the IPLA for n=I,4,16,...,246, the refreshment time and the scanning time. In the second table are presented 20 different comparative points as: scanning time by several system types, picture loss, stability of scanning, cells overlapping, cost of system implemenptat[on, system complexity, inactivity, precision, discreetness, etc. at which a comparison among three image scanning systems (raster, vector, IPLA) takes place. After this comparison the advantage-points on which the IPLA excels over the other systems are 12, while has I negative-point on 20 comparative points.
I
(O) A L ~,epll,tillST
?
Fig.. 5:a)The circuit of the A. amplifier, b)Ti~c IC lmplementat~on " z of the Ai amplifier. .
In figure (6) a ground-plan of the IPLA is shown. If the IPLA is constructed to have only one output, the digital switches area and the output circuits area are omitted and the output circuit is constructed in the counter decoders area.
"//X/ ~, > 3,'#/ / / / / / / / ~ ,.. ~
SOME COMPARISONS OF IPLA WITH 8086 CHIP
Previously, some important features for the proposed IPLA are referred to assist in the
To ~.ode KL
I
ST
&.
129
-
//
T.,-L--,~,~?q !" "
The following diagrams show the variation of the decimal logarithm of the IPLA complexity (c) versus the binary logarithm of (n), with parameter (d), (w), (ts). The function c = f(n) is discrete and is determined for (log2n)a [Z]5 the parameter (d) represents the number o~ decoders except of the X,XY and M.V. decoders; and alternatively the number of the built in scanning techniques.
\~=0
J
71
l&~'/..II l ! ~ l \\-.>x,
Fig. 6:The g~.pund plan of zhe scanning system (it is not under scale).
Fig. 7:Graphicalpresentationof complexityC , numberof photosensltire elementsn, with the parameter~ fop one ouTpu~w-l.
D. Panogiotopoulos, N. 8ourbakis /Design of a Two Dimensional ImageProcessingArray
130
~//
q-w:! ~- w=&
I
)V= 2$&
I / /
W : 4615# 4-
0
I
2
3
&
S
6
7
8
9
40
4!
12
W : &S53~
,~3 I ~
Pig. ~O:Graphical presentalion of scannin~ lime in relallon ship with the photocells number n using neperlous logarilhms.
5. I
I
i
I
I
l
I
i
:
0
t
Z
S
4
5
6
7
t
9
Fig.
B:C~aphical preaentatlon of complexity C , number of outputs w
I~¢j:tW
with parameter n,
(n=6g,128,256,512), d-~.
t q . 156 --
w 1+121
~
w-6*,
~w,$Z
.--w:I
?t
CONCLUSION AND EXTENSION
In this paper the implementation of a realtlme and programmable image processing logic array by VLSI technology was discussed. Its operation way was also presented. However, there are some points which could be extented as the generalization for pictures nxm. The proposed array could be successfully used on a robot eye realizing different kinds of scanning (sequential, parallel or both) which approach to the human eye behavior [19]. Concretely, the human eye can in parallel give a global perception of all objects (which are contained into the optical area) which it covers, or immediately give significant details about an object which is found in the center of the optical area. The presented array can be operated by the same way, by supporting it with a proper system of lens and a hierarchical multimicroprocessors system [20].IPLA has an important feature, that can in parallel and immediately give the significant information for more than one objects which are found at different places into the optical area [19]. Another important feature of this array is that it can create data structures (as pyramid, cone [9,12] and the proper scanning for the easy, fast picture processing, [2,7,12]. Finally, the presented IPLA compared with he raster scanning, vector scanning systems presents significant advantages on the scanning time, applications, scanning techniques etc. and only one disadvantage, [2] the compllcatlty which moderates with the evolution of the I.C. technology.[18] Fig.
9:Graphical pmesentation of the variation of the decimal loEarlthm of the complexity of The scanning system versus the blnamy logarlthm of n, with parameter w, and Jar.
D. Panogiotopoulos,N. Bourbakis/ Design of a Two Dimensional ImageProcessingArray
131
REFERENCES
(1)
MASAHIRO SAKAUE, TERUO TAMAMA, and YOSHIHIKO MIZUSHIMA; "Plasma-Coupled Bipolar Linear Image Sensor", IEEE Trans. on Electron Devices May 1981, Vol. ED-28, pp. 517-522.
(2)
N.G. BOURBAKIS and D.A. PANAGIOTOPOULOS; "Image Scanning Techniques and Real Time Dynamic and Programmable Scanning System", Report, Univ. of Patras, Sch. of Engl., Chair of Comp. Sci., RRgl-01, 1981.
(3)
A. KLINGER and H. KELUDJIAN; "A Proposal for on-line feature Detection and Extration", Proceedings 1972, Computer Image Processing Recognition Symposium.
(4)
(5)
ESMAT Z. HAMDY, MOHAMED I. ELMASRY, YOUSEF A. EL-MANSY; 'Single-Device-well MOSFETs", IEEE Trans, on Electron Devices, March 1981, Vol. ED-28, pp. 322327. MARTIN P. LEPSELTER; "X-ray lithography breaks the aubmicrameter Barrier", IEEE Spectrum, May 1981, pp. 26-29.
(i 3)
L.E.TANNAS and W.F.COODE "APPLICATIONS DISPLAYS: Flat Panel Displays a Critique", IEEE Spectrum, July 1978, pp. 26-32.
(14)
P. STUCKI 'Solid State Area Scanning Arrays as Interface Devices between Optical and Digital Computing System, A Simulation Study", IEEE Trans. on Computers, Vol. C-24, No. 4, April 1975, pp. 370-380.
(15)
E. BRACHA "Digital Picture with a Parallel Processor System "IEEE Computer Society Report, R-78-235, Nov. 1978.
(16)
H. ANORIEWS "Spatial Resolution: Requirements for Real-Time Digital Displays", IEEE Trans on Computers.
(17)
N. BOURBAKIS, M. PAPAZOGLOU, C. ALEXOPOULOS and G. ALEXIOUS "An Efficient Preprocessing Image System" Proc. of Int. Symp. on MECO-83, Athens, Greece.
(la)
N.BOURBAKIS and D. PANAGIOTOPOULOS "An Efficient Real-Time Image Scanning System", Proc of IEEE Int. Conf. on Computers, Systems and Signal Processing, Bangalore, India, Dec. 10-12, 1984.
(6)
JOHN C. EIDSON; "Fast electrom-beam Lithography", IEEE Spectrum, July 1981, pp. 24-28.
(7)
N. BOURBAKIS "On microcomputers-based parallel image processing machine", Proc. of Forth lASTED international Symposium MECO-81, Aug. 31-Sept 3, Cairo, Egypt 1981.
(19)
N. BOURBAKIS and D. PANAGIOTOPOULOS "A Proposal for the Design of a Robot Eye" Proc. of Int. Symp. on Robotics, March 2-5, 1982, Davos, Switzerland, pp. 2023.
(8)
S. TANIMOTO and T. PAYLIDIS "A Hierarchical Data Structure for Picture Processing", Int. Journal on CGIP 4, pp. 104-119, 1975.
(2o)
(9)
S. TANIMOTO and A. KLINGER, "Structured Computer Vision", Academic Press 1980, New York.
BOURBAKIS N. and VAITSOS C. "A Multimicroprocessor Tree Network Configuration used on Robot Vision Systems", Proc. of Int. Meeting on Digltech-84, July 12-14, 1984, Patras, Greece, North Holand Pub. Co.
(lO)
A. KLINGER and R. C. DYER, "Experiments on Picture Represtation using Regular Decamposltion" Scientific Research, Air Force Systems Command USAF, undergrant No AFOSR-72-2384, July 1974.
(11)
D.A. PANAGIOTOPOULOS and N.G. BOURBAKIS, "A new dynamic, real-tlme and programmable image scanning system by VLSI technology", Research Report, Chair of Computer Science, Univ. of Patras, RR03-81, Patras, 1981, Greece.
(12)
N. BOURBAKIS "New, Real Time Processing Methods of Structured Images", PhD thesis, Univ. of Patras, Sch. of Eng., Dept. of Comp. Sci. Patras 1982.
132
D. Panogiotopoulos, N. Bourbakis /Design of a Two Dimensional Image ProcessingArray
DIMOKRITOS PANAGIOTOPOULOS was born in Thessaloniki Greece in 1960. He received his Diploma in Electrical Engineering from Patras University, Greece in 1982 and his MSc in Electrical Engineering from the University of Maryland. He is now a PhD student in the Electrical Engineering Department of Maryland University. He has given various courses in Computer Science, both as teaching assistant and lab instructor. His current intrests include Multimicroprocessor Systems, Robot Vision, Knowledge Systems, Expert Systems.
NIKOLAOS BOURBAKIS was born in Chania-Crete, Greece in 1950. He received his BS~ degree in Mathematics from the National University of Athens, Greece in 1975. He has studied towards his PhD in" the Department of Computer Engineering at the University of Patrasr Greece (1978) and he received his PhD in 1982. He has taught various courses in Computer Science as teaching assistant, lab instructor and lecturer in the Computer Engineering Department, Patras University, Greece (1978-1984). Now he is an Assistant Professor in Electrical and Computer Engineering at the G. Mason University. His current interests include Image Processing, Multimieroprocessor Systems, Data Structures, Robot Vision Systems, Expert Systems and Picture Information Systems.