Thermal chemical vapor deposition of semiconductors for thin film transistor applications

MICROELECTRONIC ENGINEERING

ELSEVIER

Microelectronic

Thermal Chemical Vapor for Thin Film Transistor

Engineering 2.5 (1994) 337-344

Deposition of Semiconductors Applications

D.W. Greve Department of Electrical 15213, USA

and Computer Engineering,

Carnegie Mellon University,

Pittsburgh,

PA

Formation of the semiconducting layer is a crucial part of the fabrication of thin film Despite severe constraints on maximum process transistors for flat panel display applications. temperatures, control of grain size and surface roughness is essential in order to achieve good transistor characteristics. This paper reviews the various approaches which have been explored for deposition of the semiconducting thin films. I will show that the transistor characteristics are strongly influenced by nucleation processes in the bulk of the films and at the interfaces. Control of these nucleation processes will be best achieved by integrated processing where multiple layers are grown without exposure to contaminants. 1.

INTRODUCTION

Laptop computers presently represent a major application for liquid crystal flat panel displays of all types. Least expensive are passive multiplexed displays which suffer from poor contrast In contrast, active matrix flat panel displays and slow response to changing input signals. achieve superior performance by using a storage capacitor and thin film switching transistor at each pixel. Manfacturing of these displays is extremely challenging, as it requires the attainment of defect levels similar to current- technology DRAMS in a circuit fabricated on a large glass substrate. In current display technology, transistors are fabricated from plasma- deposited amorphous silicon, which yields effective field effect mobilities of about 1 cm2/Vsec. This performance is adequate for use within the active matrix but will not be adequate for next- generation displays which integrate driver circuitry onto the display panel. Thin film transistors used in the scan and data drive circuits must be capable of higher switching speed than that attainable with amorphous silicon transistors. In this paper, I discuss the deposition of polycrystalline semiconducting material for thin film transistors in flat panel displays. The characteristics of completed transistors depend strongly on the deposition and annealing conditions which are subject to severe constraints by the properties of the glass substrate. The discussion will be limited to polycrystalline silicon, germanium, and germaniumsilicon alloys. Polycrystalline cadmium selenide has also been used in display applications, but materials related to silicon have the advantage of a superior knowledge base and are therefore more likely to be successful in production. The primary constraint imposed by the flat panel display application is with respect to process temperature and time. Generally, glasses with higher strain points are more expensive and more difficult to obtain in the size and quality required. Thus even though fused silica substrates would permit process temperatures as high as those used in standard semiconductor processing, it is more practical to use a high temperature glass such as Coming 1735. This glass has a strain point of 665 C, although it is desirable to keep process temperatures somewhat lower. This is a severe constraint as it means that conventional implant annealing and thermal oxidation are impossible. In addition, it is not possible to increase the grain size of the polycrystalline material by annealing at high temperature, 0167-9317/94/$07.00 0 1994 - Elsevier SD1 0167-93 17(94)00034-R

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D.W. Grew I Thermal chemical vapor deposition C$semiconductors

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silicon active layer

Figure 1. NMOS thin film transistor fabricated on glass substrate.

Unfortunately, many of the characteristics of thin film transistors improve as the grain size is increased. Figure 1 shows a cross section of a thin film transistor. The semiconductor is undoped polycrystalline material which is 200- 1500 8, in thickness. In the ON state, a positive gate voltage induces additional electrons creating a channel from source to drain. Assuming that the Fermi level is initially pinned near midgap, the total charge ]coulcm-2] which must be supplied to the semiconductor is QT = q olyNTEG/2 where EG is the band gap of the semiconductor and N, [cm-2.eV-t]is the trap >ensity. Assuming the traps are mostly attributable to grain boundaries with a surface trap density of Nt[cm-2.eV-t], I can write NT = Nt/L and thus the threshold voltage

v, = QJIC,,

=

9tpoly~NtmEd2cox.

(1)

Low threshold voltages thus require low grain boundary trap density, large grain size, and small thickness of the polycrystalline layer. Other parameters such as effective field effect mobility ueff and subthreshold slope S = d(logI,)/dVD also improve with increasing grain size. In the following, I will discuss various approaches which have been explored in order to obtain large grain size polycrystalline films in a manner consistent with the constraints of the flat panel display application. Together with hydrogen passivation of grain boundary states (which reduces N.,) and high quality insulator deposition, these approaches permit the fabrication of thin film transistors of suitable performance. In this paper, I will focus on effective mobility as the figure of merit which is most important when the transistors are used in driver circuitry. Other parameters such as threshold voltage, subthreshold slope, and ON/ OFF ratio must of course also have acceptable values. 2.

POLYSILICON

DEPOSITION

PROCESSES

In ordinary semiconductor processes, polysilicon is deposited by LPCVD in a reactor which contains a large number (= 100) closely spaced wafers. Commonly deposition is perfomled near 625 r at a silane pressure of about 0.2 torr, consisting either of pure silane or silane plus a carrier gas. Films grown on silicon dioxide show a columnar grain structure, with numerous small grains at the initial growth interface. The films have predominant texture and have grain size near 500 A. Such films are unsuitable for fabrication of thin film transistors, exhibiting high threshold voltages and low field effect mobility. The grain size is unaffected by annealing except at high temperatures (= 1000 97) where secondary grain growth occurs. Several approaches have recently been developed which yield large grain material suitable for display applications. In all cases, larger grain size is obtained by reducing the nucleation rate of grains relative to the growth rate. Distinctly different results are obtained, however, depending upon whether the films are crystallized from the amorphous phase or grown directly as polycrystalline material from the gas phase. Details of the results obtained by various

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researchers are discussed below. 2.1. Crystallized Amorphous Silicon Crystallization of amorphous silicon has been extensively

studied and examination of published micrographs shows that quite large grains are obtained under some conditions. Anderson [l] performed an early study of the structure of APCVD and evaporated silicon films annealed under various conditions. He observed dendritic growth in amorphous material deposited by both techniques and observed grain sizes as large as 1 pm, with a general trend toward larger grain size at lower crystallization temperatures. Similar results were reported by Kijster [2], who measured the activation energies of grain nucleation and growth in e- beam evaporated material. Crystallization of silicon implant- amorphized films has also been studied and crystallization of amorphous LPCVD films at high temperatures (900- 1000 “c) was reported to result in improvement in surface smoothness and other properties [3]. The potential application of crystallized amorphous silicon to flat panel displays seems not to have been appreciated, however, before the work of Noguchi and coworkers [4,5]. They amorphized 200- 300 A LPCVD polycrystalline films by silicon implantation, followed by crystallization at 600 9J for 15 hours. Dendritic grains as large as 1 pm were observed after annealing, and thin film transistors fabricated from these films exhibited effective mobilities as high as 60 cm21Vsec.

Tanneal A 550°C o 95ooc

‘Ei 4oo S

Figure 2. Measured grain size of LPCVD silicon after annealing for complete crystallization. From [7], used by permission.

N” ‘Z .c E (3

200

-

, 500

I

I,

1

550 Deposition

,

,

,

,

,

600 Temperature

,

,

I 650

(“c)

Crystallization of an amorphous film requires the nucleation of crystallites followed by their growth by solid phase epitaxy. Large grains are favored at low annealing temperatures because the activation energy EA(nucleationJ>EA( oWth). The rate of grain growth (or solid phase epitaxy) at a particular temperature is influencefonly by relatively high concentrations of impurities [6]. However, the nucleation rate can be different in apparently amorphous materials deposited under different conditions, and excess nucleation is sometimes observed at interfaces. Thus many studies have been directed at optimizing the deposition of the amorphous material. Following the work of Noguchi et al., a coworker and I studied the crystallization of LPCVD- deposited amorphous silicon films [7]. The work was motivated by the observation that high- dose silicon implantation over large areas would be ultimately impractical in manufacturing. Figure 2 shows the measured grain size as a function of deposition temperature; clearly the optimum deposition temperature is 545 93. The figure also shows the trend toward larger grains at low annealing temperatures. Decreasing the annealling temperature below about 550 93 is however impractical because the time required for complete crystallization becomes unacceptably long. Thin film transistors fabricated in optimally crystallized material yielded

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effective mobilities as high as 32 cm2/ Vsec after hydrogen passivation [S]. In this work, a thermal oxide layer grown at 860 C was used as a gate insulator. Subsequently, similar results were reported using a 600 ‘c maximum temperature [9]. Subsequently, the observation of an optimum deposition temperature near 545 “c was confirmed and a crystallized amorphous silicon process was applied to the fabrication of a display with integrated drivers [lo]. Similar processes have been reported by other groups [11,12]. A detailed study of the nucleation and growth of dendritic grains in amorphous films was performed by Nakamura et al. [13). Initially grains are elliptical with a (111) twin boundary running along the major axis. In the later states of growth, protrusions develop along texture 110,141.

Figure 3. Characteristic shapes of grains: (a) dendritic polysilicon obtained by crystallization of amorphous silicon (plan view; adapted from [ 131): (b)“toothlike” grains in polysilicon deposited at low growth rates (cross sectional view; adapted from 1221). Another approach to controlling nucleation was reported by Kwisera and Reif [ 151 who implanted at a 45” angle with a dose just below that required to completely amorphize the film. This choice of implant angle was intended to enhance the predominantly texture of the de osited film. Although the greatest enhancement in texture was obtained for a dose of 1.1 x 1074 crn2, the largest grain size results after full amorphization (2 x 1Ol4 cme2) 116). Complete amorphization was subsequently used to fabricate n- and p- channel transistors [ 171. Implantation was also used by Wu et al., who observed nucleation at the bottom interface 1141. A relatively deep silicon implant was used to induce recoil of oxygen atoms into the lower part of the film thus reducing the nucleation rate. Finally, there has been some work on crystallization of amorphous films deposited from disilane, where the largest grain size is obtained for films deposited at 470 ‘C [ 181. Disilane also offers higher deposition rates at low temperatures because it can react with hydrogen- covered surfaces [19], and the grain sizes and effective mobilities are higher (up to 120 cm2/Vsec) [20]. In very recent work, two different growth rates were used in silane LPCVD to obtain an optimal density of nucleation sites together with reduced anneal times [2 11. 2.2.

As- Deposited Polycrystalline Silicon While crystallized amorphous silicon yields transistors with high performance, the extended crystallization time (possibly as long as 72 h at 550 97) is a significant liability. Thus a number of studies have addressed the direct deposition of a suitable polycrystalline silicon film. Meakin

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and coworkers [22] studied the effect of deposition pressure at constant temperature. At low silane pressures (P c 100 mTorr) and T = 630 r they observed larger grain sizes and a different growth mode. Figure 3b illustrates the structure of the resulting films. Fewer grains are nucleated than at high pressure and grains coalesce by lateral growth. The predominant texture is ~100~ and there is appreciable surface roughness due to the “toothlike” structure of the Field effect transistors fabricated in this material had effective mobilities in passivated z:ir& of order 10 cm2/Vsec and VT = 8 V [23]. These results are not as good as obtained from crystallized amorphous silicon, probably as a consequence of the non- planar surface. A comprehensive study of the effect of temperature and reactant partial pressure on the structure of polycrystalline films deposited from silane was recently reported by Voutsas and Hatalis [24]. Some results of that study are presented in Fig. 4. A critical deposition rate can be defined (which increases as a function of temperature) separating amorphous and polycrystalline phases. For films deposited at a particular temperature in the polycrystalline phase, a decrease in reactant pressure increases the grain size as more time is allowed for adatoms to migrate.

6

Figure 4. Structure of silicon films deposited by LPCVD as a function of temperature and pressure. From [29], used by permission.

520

540

560

Deposition

580 Temperature

600

620

(“C)

The grain size is of course also influenced by the number of stable nuclei formed on the substrate. I will consider here only nucleation on silicon dioxide; this surface has been most studied and represents the actual situation in display manufacture when the substrate is fused silica or has received an initial coating of silicon dioxide. Some insight into the nucleation process can be obtained from experiments on selective epitaxial growth from silane. On clean silicon surfaces, there are a large number of dangling bonds even after surface reconstruction (approximately equal to the number of surface atoms). The initial chemisorption of silane requires two dangling bonds and is given by [ 191 SiH, + 2* +

SiH3* + H*

(2)

where * represents a dangling bond (or surface site) and X* represents species X attached to a surface site. The nature of silicon dioxide surfaces is quite different. The surface chemistry of amorphous and crystalline silica surfaces has been reviewed by Iler [25]. At room temperature, wet

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chemical treatments and water vapor adsorbed from the air lead to a surface consisting of surface hydroxyl (Si-O-H) groups with additional hydrogen- bonded water molecules. The water molecules are desorbed at about 150 ‘c: and as the temperature is increased further the hydroxyl groups condense to form siloxane (Si-0-Si) groups. At typical growth temperatures (500- 600 T) the number of hydroxyl groups is about 20% of the number at room temperature. Unlike the clean silicon surface, then, the silicon dioxide surface does not have a large number of active sites. Indeed, it is not clear how polysilicon nucleates on the silicon dioxide surface, although is reasonable to expect nucleation to be influenced by surface defects and/ or surface treatments. The reduced reactivity of silane on oxygen- covered surfaces had been observed in early work where an induction period was observed before the beginning of epitaxial layer growth from silane. Recently, this phenomena has been used to grow a limited thickness of selective epitaxial layer on patterned silicon substrates [26]. At high pressures (= 0.2 Torr) typical of ordinary polysilicon deposition, the nucleation time is not discemable. Below I summarize the results of recent studies of the nucleation process under conditions of low pressure growth. Dana and coworkers [27,28] examined the nucleation of polycrystalline silicon on silicon dioxide at a pressure of about 1.6 mTorr in a UHV/ CVD system. Similar results were obtained for substrates which were oxidized and chemically cleaned before loading and substrates which were oxidized in situ. After exposure to silane for a particular time, the temperature was decreased (to freeze in the hydrogen surface concentration) and the silicon surface area was determined by measuring the hydrogen desorbed during a ramp to high temperatures. It was found that the surface area initially increased quite rapidly (-t4) followed by a slower increase (-t2). The t2 dependence is consistent with the dominance of grain enlargement over nucleation. The surface microstructure observed by SEM was similar to that reported by Meakin et al. [22]. The effect of various wet- chemical pretreatments on grain size and surface roughness has been investigated by Voutsas and Hatalis [29]. Depositions were performed at 570 93 and 140 mTorr and various wet chemical treatments were performed prior to deposition. All wet chemical treatments (HF dip, RCA clean, and H,SO,/H,O,) caused roughly a factor of two decrease in the grain size compared to freshly oxidized wafers. It is interesting that a large grain size was obtained after an RCA clean provided a 1100 ‘c1 anneal was performed just prior to deposition. These results were attributed to an unidentified surface impurity species introduced by the wet cleaning process. The dependence of grain size on surface preparation suggests that ultraclean deposition processes are highly desirable. In such a process, it will be possible to prepare the initial growth surface in situ in order to minimize or control the number of initial nucleation sites. A degree of surface roughness appears to be an intrinsic aspect of films which achieve large grain size by reducing the number of initial nucleation sites. Thus transistors fabricated in as- deposited polycrystalline films are likely to be inferior to those fabricated in crystallized amorphous silicon. A more serious problem is the low growth rates achievable when depositing directly in the polycrystalline form. For a deposition temperature of 550 T, polycrystalline material is deposited only for growth rates below 10 A/ min. Growth of a 1000 A film thus requires in excess of 100 min, which is unacceptable for production in a single- substrate system. (It may be possible, however, to deposit on multiple substrates simultaneously). In contrast, the best results for crystallized amorphous silicon are obtained for high deposition rates (up to at least 80 & min at 545 r [7]. These deposition rates may be practical for single substrates but an extended crystallization anneal is still required. 3.

GERMANIUM

AND

GERMANIUM-

SILICON

ALLOYS

The considerations above make germanium or germanium- silicon alloys attractive alternate materials. As the melting points are lower than silicon, it is reasonable to expect the amorphouscrystalline transition to occur at lower temperatures and also to expect larger grain sizes during

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A further advantage is that higher growth rates are deposition of polycrystalline material. obtained because hydrogen is more easily desorbed from a germanium- rich surface [191. To date, there have been two reports of the application of polycrystalline germanium- silicon alloys to thin film transistors. In a conference paper [30], two coworkers and I compared thin film transistors fabricated in polycrystalline silicon and polycrystalline Gq.&io 95 deposited by UHV/ CVD at 600 93 and about 1 mTorr. The polycrystalline silicon transistors exhibited (after hydrogen passivation) effective field effect mobility of about 2 cm2/Vsec and threshold voltage of about 12 V. SEM photographs showed a rough surface morphology similar to that reported by Meakin et al. [221 in the same pressure regime. These characteristics were considerably inferior to those of crystallized amorphous silicon transistors fabricated at the same time. Polycrystalline Ge, OsSi, 95 transistors were fabricated but not fully characterized because of a large negative threshold voltage. (This was a consequence of the gate insulator process used, which required a 600 C thermal oxidation step. Thermal oxidation is known to produce negative oxide charge in germaniumsilicon MOS capacitors). In this study and a previous study [26] of selective epitaxy, nucleation became increasingly more difficult as the germanium fraction increased. More promising results were obtained in a more recent report by King and Saraswat [31]. Deposition was by LPCVD using germane and silane as source gases, and both amorphous and polycrystalline material were deposited. The temperature of the amorphous/ polycrystalline transition decreased with increasing germanium fraction. Thin film transistors were fabricated from amorphous Ge0.20Si0.80 deposited at 490 93 and crystallized by a 24 h anneal at 550 9J. Observed mobilities were pn = 0.5 and cl, = 2 cm2/Vsec. A Ge0.25Si0.75 PMOS devices which had a slightly higher maximum process temperature (600 C) achieved up = 8 cm2/Vsec. Further improvements may result as the deposition and annealing processes are optimized. The germaniumsilicon films studied by King and Saraswat had relatively high oxygen concentrations (= 4 x 1Ol9 cm3). This is higher than typically observed in LPCVD polysilicon films and considerably in excess of the oxygen content in layers deposited under ultraclean conditions. The role of oxygen and other contaminants needs to be further explored. It is known that high concentrations of oxygen reduce the growth rate by solid phase epitaxy [6] and oxygen can also introduce trap states. Oxygen and other impurities might also have an influence on grain nucleation. Finally, there is one recent report of the fabrication of transistors using evaporated polycrystalline germanium [32]. This is a CMOS CdSe technology with a maximum process temperature of 400 C. A germaniumcopper film was evaporated and annealed to form polycrystalline germanium. The copper is reported to act as a recrystallization catalyst and a ptype dopant. Mobilities were in the range of 5 15 cm2/Vsec. The results obtained so far using germanium and germanium- silicon are encouraging but so far not superior to the results obtained with polycrystalline silicon. I believe that additional work is warranted because of the potential for a decrease in maximum process temperature. All other things being equal, better results may be anticipated for pure germanium than for alloys, because of lower crystallization and deposition temperatures. Major issues which need study are the nucleation of the germanium thin film and development of an appropriate gate insulator technology.

4.

CONCLUSIONS

Several distinct approaches have been explored for the deposition of semiconducting layers suitable for high- mobility thin film transistors. In all cases, large grain size is desirable and is obtained by the control of nucleation, either in the solid phase or on the surface. The best results so far have been obtained using crystallized amorphous silicon. Direct deposition of polycrystalline silicon is a close second while germanium- silicon and germanium technologies

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are still at an early stage of development. Integrated processing can make a major contribution through its potential for control of contaminants at surfaces and in the bulk. Systems will probably have very different architectures depending upon the technology chosen. The crystallized amorphous silicon process may permit a single- panel reactor, while the low deposition rates required for direct deposition of polycrystalline silicon will probably require multiple- panel systems. ACKNOWLEDGEMENTS I gratefully acknowledge the contributions of my coworkers M.K. Hatalis, B.-C. Hseih, T.-Y. Ma, and M. Racanelli, and particularly M.K. Hatalis for discussions during the preparation of this manuscript. I also acknowledge support from Panelvision; Philips Research Laboratories; Sunnyvale; the Ben Franklin Partnership; Litton; and IBM. REFERENCES 1. R.M. Anderson, J. Elecfrochem. Sot. 120 (1973) 1540. U. KCister, Phys. Stat. Sol. A48 (1978) 3132. G. Harbeke, L. Krausbauer, E.F. Stegmeicr, A.E.Widmer, H.F. Kapperl, and G. Neugebauer,.I. Elecfrochem. Sot. 131 (1984) 675. 4. T. Ohshima, T. Noguchi, and H. Hayashi, Japan. J. Appl. Phys. 25 (19X6) L291. 5. T. Noguchi, H. Hiyashi, and T. Ohshima, J. Electrochem. Sot. 134 (1987) 1771. 6. E.F. Kennedy, L.Csepregi, J.W. Mayer, and T.W. Sigmon, J. Appl. Phys. 48 (1977) 4241. 7. M.K. Hatalis and D.W. Greve, J. Appl. Phys. 63 (1988) 2260. 8. M.K. Hatalis and D.W. Greve,lEEE Elecfron Dev. Letr. EDL-8 (1987) 361. 9. B.-Y. Hseih, M.K. Hatalis, and D.W. Greve,IEEE Trans. Electron Dev. ED-35 (1988) 1842. 10.A. Mimura, N. Konishi, K. Ono, J.-I. Ohwada, Y. Hosokawa, Y. A. Ono, T. Suzuki, K. Miyata, and H. Kawakami,lEEE Trans. Electron Dev. ED-36 (1989) 351. 11. A.C. Ipri, S. Policastro, and D. PancholyJEEE Trans. Electron Dev. ED-37 (1990) 313. 12. T.-J. King and K. Saraswat,lEEE Trans. ElecfronDev. ED-13 (1992) 309. 13. A. Nakamura, F. Emoto, E. Fujii, A. Yamamoto, Y. Uemoto, K. Senda, and G. Kano, J. Appl. Phys. 66, 2. 3.

(1989) 4249. 14. I.-W. Wu, A. Chiang, M. Fuse, L. &qoglu, and T.Y. Huang, J. Appl. Phys. 65 (1989) 4036. 15. P. Kwisera and R. Reif,Appl. Phys. Lett. 41 (1982) 379. 16. K.T.-Y. Kung and R. Reif, J. Appl. Phys. 59 (1986) 2422. 17. K.T.-Y. Kung and R. Reif,J. Appl. Phys. 61 (1987) 163X. 18. A.T. Voutsas and M.K. Hatalis,J. Elecfrochem. Sot. 140 (1993) 871 and references therin.

19. See D.W. Greve,Mar. Sci. Engrg. B18 (1993) 22and references therein. 20. A. Nakamura, F. Emoto, E. Fujii, A. Yamamoto, Y. Uemoto, H. Hayashi, K. Senda, IEDM 1990 p. X47. 21.M.K. Hatalis, D.N. Kouvatsos, J.-H. Kung, A.T. Voutsas, F.P. Fehlner, and J. Kanicki, Proc. SID 1993. 22. D.B. Meakin, J. Stoemenos, P. Migliorato, and N.A. Economou, J. Appl. Phys. 6 1 (19X7) 5031. 23. D.B. Meakin, P.A. Coxon, P. Migliorato, J. Stoemenos, and N.A. Economou,Appl. Phys. Lefr. 50 (19X7) 1x94. 24. A.T. Voutsas and M.K. Hata1is.J. Elecfrochem. Sot. 139, 2659 (1992) 2659. 25. R.K. Iler, The Chemistry of Silica, (J. Wiley and Sons, New York, 1979, p. 622- 648). 26. M. Racanelli and D.W. Greve,Appl. Phys. Letf. 58 (1991) 2096and references therein. 27. S.S. Dana, M. Liehr, M. Anderle, and G.W. Rubloff, Appl. Phys. Letf. 61 (1992) 3035. 28. M. Liehr, S.S. Dana and M. Anderle, J. Vat. Sci. Technol. A 10 (1992) 869. 29. A.T. Voutsas and M.K. Hatalis,J. Elecfrochem. Sot. 140 (1993) 282. 30. D.W. Greve, T.Y. Ma and M. Racanelli, Recent News Paper, 1990 Electrochem. Sot. Fall Meeting, Seattle, WA. 31. T.-J. King and K.C. Saraswat, IEDM 1991 p. 567. 32. J. Doutreloigne. J. De Baets, I. De Rycke, H. De Smet, A. Van Calster, and J. Vanfleteren, Solid Sf. Electron. 34 (1991)

143.