Thermal enhancement of plastic IC packages

World abstracts on microelectronics and reliability of various aspect ratios and pitch were plated on the active areas of the power amplifier wafers. Bump profiles of hourglass shape compliant to substrate nonplanarity as well as conducive to improved joint reliability were deposited. Ideal bump geometries were also selected based on the ability of available plating processes to produce bondable bumps. Several flip chip bonding techniques (gold-gold thermosonic as well as gold tin eutectic) were developed for those active area bumps and evaluated with respect to bondability and bond thermal resistance. Some examples will be provided to illustrate the effects of bonding variables, e.g. chip and substrate temperatures, load and pulse strength on the bonds, and device active area for each of these bonding methods. These data were obtained by metallurgical analyses as well as thermal resistance measurements under d.c. bias. Fine line circuit manufacturing technology with electroless copper plating. HARUO AKAHOSHI et al., I EEE Transactions on Components, Packaging and Manufacturing Technology, Part A, 18(1), 127 (March 1995). Two types of additive processes for fine circuit pattern manufacturing technology using electroless copper plating have been developed. The processes offer high dimensional accuracy. Technical aspects of the additive processes, materials for the fabrication of additive circuits, and the performance of these circuits are reported here. Effects of die coatings, mold compounds, and test conditions on temperature cycling failures. LUU T. NGUYEN, STEVEN A. GEE, MARTIN R. JOHNSON, HERB E. GRIMM, HECTOR BERARDI and RANDY L. WALBERG. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part A, 18(1), 15 (March 1995). When a plastic package is subjected to repeated thermal excursions such as during thermal cycling or thermal shock, progressive damage to the silicon die occurs. Damage can be initiated in the form of interfacial delamination accompanied by passivation cracking, and subsequently, by dielectric fracture that may ultimately lead to device failure. The extent of damage depends on the interaction between the various components in the package. In this study, thermal cycling of PLCC packages indicated that the die design configuration, the nature of the coating and its thickness, the formulation of the molding compound, the preconditioning of the packages, and the thermal excursion conditions all govern the electrical failure rates observed. Thus, careful selection of the proper combination of parameters can offer improved device reliability. Thermal enhancement of plastic IC packages. DARVIN R. EDWARDS, M I N G H W A N G and BILL STEARNS. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part A, 18(1), 57 (March 1995). Plastic package thermal

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enhancement techniques that improve the heat dissipating capabilities of the packages are available to IC package design engineers. Evaluations of these techniques have been performed using test structure measurements and thermal FEA modeling. The techniques studied include the use of additional metal traces on the PCB to spread the heat away from the package, the use of heat slugs and heat spreaders inside the package to enhance heat transfer to the package leads and package body, and the use of high thermal conductivity mold compounds to improve thermal performance. Package types ranged from 8 pin SOIC's to 208 PQFP's with a broad range of chip sizes. Details of the measurement and modeling techniques are given with comparison of the models to the experimental results in many instances. To cut or not to cut: a thermomechanieal stress analysis of polyimide thin-film on ceramic structures. MICHAEL PECHT, XIN WU, K Y U N G W. PAIK and S. NAVIN BHANDARKAR. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B, 18(1), 150 (February 1995). When thin-film polyimide-on-ceramic multilayered structures are subjected to thermal loads during manufacturing processes, stresses can be produced at the interface of the film and ceramic due to a mismatch in the coefficients of thermal expansion of the materials. These stresses, which may cause delamination and peeling of the films, are typically largest near the free edge of the structure. This has raised the question of whether cross-sectioning these structures to examine the interior for such defects as interracial de-adhesion or delamination may change the stress distribution and actually generate flaws, thereby defeating the purpose of the cross-sectioning. In this paper, thermally induced stresses are evaluated for laminated thin-film Kapton ~ on alumina structures, taking into account creep deformation and stress relaxation of the Kapton '~ layer. After experimentation temperature and stressdependent creep-strain constitutive models were developed; the properties of nonlinear temperaturedependent elastic plastic and the coefficient of thermal expansion were also described. Stress analysis was performed, using plane-strain finite element analysis. It was found that sufficient stress relaxation can occur to arrest interface peeling and delamination at the free edge. Large area fine line patterning by scanning projection lithography. HEINRICH G. MULLER, YANRONG YUAN and RONALD E. SHEETS. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B, 18(1), 33 (February 1995). A new type of photolithography tool has been developed, addressing the specific needs of MCM manufacture. It is based on scanning projection exposure. It can expose panels at variable sizes up to 500 mm x 600 mm (typical laminate size), with an optical resolution of less than 5 jam and an overlay accuracy of 2 jam